CVS log for src/sys/arch/sbmips/sbmips/sb1250_icu.c

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Keyword substitution: kv
Default branch: MAIN

use kcpuset_isset() and pass second (NULL) argument to mips_fixup_exceptions()
to fix build for GENERIC(64).MP kernel configs.

update from HEAD

Sync with HEAD

Sync with HEAD

make this compile.

cleanup machine includes

Sync with HEAD.

sync with head

Sync with HEAD

Merge from matt-nb5-mips64.
Add pci support.
new interrupt code.
Adapt to new world order for MIPS

Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits.  Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

seperate initializing spl is from initizlizing the PIC:
setting ipl_sr_map is moved from sb1250_icu_init to sb1250_ipl_map_init.

Add IPL_DDB.  This is needed for watchdog on sbmips and for IPIs used by DDB.
It's above IPL_SCHED but below IPL_HIGH.

Make the sibyte watchdog establish an interrupt, and if taken, drop into DDB.
Make sure these interrupt are not blocked by IPL_HIGH.

Force the Watchdog interrupts to NMI and don't mask them.

Use dclz directly since gcc4.1 doesn't to with clzdi properly.

Want until sb1250_cpu_init to establish interrupts.

establish IPI intrs in sb1250_cpu_init

Move cpu_softc to <machine/cpuvar.h>
#include <machine/cpuvar.h> appropriately
Change cpu_softc prefix from cpu_ to sb1cpu_

sync with head

Use a cpu_softc to keep per-cpu things like interrupts, intr masks, etc.

Add MP interrupts, IPIs, and secondary CPU spinup.
(compile tested only).

#define __INTR_PRIVATE

Instead of a read-only ipl_sr_bits, define a ipl_sr_map struct and fill that
in the interrupt init routine.  There's a default ipl_sr_map will operate
correctly, but isn't performant.

Change to deal with new method of invoking softints.  Remove mips/softintr.c
from config files.  Fix SYMTAB_SPACE for WGT62V43

Merge from matt-nb5-mips64
Merge mips-specific arch files.

Use vaddr_t instead uint32_t for storing a pc since the latter won't work in
a LP64 kernel.

mips3_ld/mips3_sd need to be passed a volatile uint64_t *

sync with HEAD

Sync with HEAD.

Sync with HEAD.

sync with head

Sync with HEAD.

Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

Sync with head.

sync with head.

merge yamt-splraiseipl branch.

	- finish implementing splraiseipl (and makeiplcookie).
	  http://mail-index.NetBSD.org/tech-kern/2006/07/01/0000.html
	- complete workqueue(9) and fix its ipl problem, which is reported
	  to cause audio skipping.
	- fix netbt (at least compilation problems) for some ports.
	- fix PR/33218.

implement splraiseipl for sbmips.

sync with head.

Sync with head.

Switch to the MIPS generic soft interrupt code instead of using
port-specific code.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

Apply patch (requested by dbj in ticket 1724):
Fix problems when building the netbsd-1-6 branch with GCC 3.3.3.

Switch from intrcnt interrupt account to event counters.

Add "ULL" to large constant; keeps gcc331 happy.

__KERNEL_RCSID()

Update to consistently use Broadcom GPL-compatible license on all SiByte code.

catch up with -current on kqueue branch

Neaten slightly.

file sb1250_icu.c was added on branch nathanw_sa on 2002-03-06 07:51:03 +0000

file sb1250_icu.c was added on branch kqueue on 2002-06-23 17:40:24 +0000

Neaten slightly.

A basic port to the Broadcom/SiByte SB1250 evaluation board (the
"swarm").  Other SB-cpu boards will be supported by this port in
the future.

Includes support for on-chip ethernet and serial.  Many features
still missing - notably SMP, PCI/LDT and IDE.

This code is provided by the Broadband Processor Business Unit at
Broadcom Corp with minor updates by me.