version 1.40, 2021/08/09 20:49:09 |
version 1.41, 2022/02/16 23:49:27 |
Line 1034 delay(unsigned n) |
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Line 1034 delay(unsigned n) |
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tb += ((uint64_t)n * 1000 + ns_per_tick - 1) / ns_per_tick; |
tb += ((uint64_t)n * 1000 + ns_per_tick - 1) / ns_per_tick; |
tbh = tb >> 32; |
tbh = tb >> 32; |
tbl = tb; |
tbl = tb; |
asm volatile ("1: mftbu %0; cmpw %0,%1; blt 1b; bgt 2f; mftb %0; cmpw 0, %0,%2; blt 1b; 2:" : "=&r"(scratch) : "r"(tbh), "r"(tbl)); |
asm volatile( |
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"1: mftbu %0;" |
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" cmpw %0,%1;" |
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" blt 1b;" |
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" bgt 2f;" |
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" mftb %0;" |
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" cmpw 0, %0,%2;" |
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" blt 1b;" |
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"2:" |
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: "=&r"(scratch) |
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: "r"(tbh), "r"(tbl) |
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: "cc"); |
} |
} |
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void |
void |
Line 1042 _wb(uint32_t adr, uint32_t siz) |
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Line 1053 _wb(uint32_t adr, uint32_t siz) |
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{ |
{ |
uint32_t bnd; |
uint32_t bnd; |
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asm volatile("eieio"); |
asm volatile("eieio" ::: "memory"); |
for (bnd = adr + siz; adr < bnd; adr += dcache_line_size) |
for (bnd = adr + siz; adr < bnd; adr += dcache_line_size) |
asm volatile ("dcbst 0,%0" :: "r"(adr)); |
asm volatile("dcbst 0,%0" :: "r"(adr) : "memory"); |
asm volatile ("sync"); |
asm volatile("sync" ::: "memory"); |
} |
} |
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void |
void |
Line 1053 _wbinv(uint32_t adr, uint32_t siz) |
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Line 1064 _wbinv(uint32_t adr, uint32_t siz) |
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{ |
{ |
uint32_t bnd; |
uint32_t bnd; |
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asm volatile("eieio"); |
asm volatile("eieio" ::: "memory"); |
for (bnd = adr + siz; adr < bnd; adr += dcache_line_size) |
for (bnd = adr + siz; adr < bnd; adr += dcache_line_size) |
asm volatile ("dcbf 0,%0" :: "r"(adr)); |
asm volatile("dcbf 0,%0" :: "r"(adr) : "memory"); |
asm volatile ("sync"); |
asm volatile("sync"); |
} |
} |
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void |
void |
Line 1067 _inv(uint32_t adr, uint32_t siz) |
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Line 1078 _inv(uint32_t adr, uint32_t siz) |
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off = adr & (dcache_line_size - 1); |
off = adr & (dcache_line_size - 1); |
adr -= off; |
adr -= off; |
siz += off; |
siz += off; |
asm volatile ("eieio"); |
asm volatile("eieio" ::: "memory"); |
if (off != 0) { |
if (off != 0) { |
/* wbinv() leading unaligned dcache line */ |
/* wbinv() leading unaligned dcache line */ |
asm volatile ("dcbf 0,%0" :: "r"(adr)); |
asm volatile("dcbf 0,%0" :: "r"(adr) : "memory"); |
if (siz < dcache_line_size) |
if (siz < dcache_line_size) |
goto done; |
goto done; |
adr += dcache_line_size; |
adr += dcache_line_size; |
Line 1080 _inv(uint32_t adr, uint32_t siz) |
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Line 1091 _inv(uint32_t adr, uint32_t siz) |
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off = bnd & (dcache_line_size - 1); |
off = bnd & (dcache_line_size - 1); |
if (off != 0) { |
if (off != 0) { |
/* wbinv() trailing unaligned dcache line */ |
/* wbinv() trailing unaligned dcache line */ |
asm volatile ("dcbf 0,%0" :: "r"(bnd)); /* it's OK */ |
asm volatile("dcbf 0,%0" :: "r"(bnd) : "memory"); /* it's OK */ |
if (siz < dcache_line_size) |
if (siz < dcache_line_size) |
goto done; |
goto done; |
siz -= off; |
siz -= off; |
} |
} |
for (bnd = adr + siz; adr < bnd; adr += dcache_line_size) { |
for (bnd = adr + siz; adr < bnd; adr += dcache_line_size) { |
/* inv() intermediate dcache lines if ever */ |
/* inv() intermediate dcache lines if ever */ |
asm volatile ("dcbi 0,%0" :: "r"(adr)); |
asm volatile("dcbi 0,%0" :: "r"(adr) : "memory"); |
} |
} |
done: |
done: |
asm volatile ("sync"); |
asm volatile("sync" ::: "memory"); |
} |
} |
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static inline uint32_t |
static inline uint32_t |
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uint64_t tb; |
uint64_t tb; |
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asm ("1: mftbu %0; mftb %0+1; mftbu %1; cmpw %0,%1; bne 1b" |
asm ("1: mftbu %0; mftb %0+1; mftbu %1; cmpw %0,%1; bne 1b" |
: "=r"(tb), "=r"(scratch)); |
: "=r"(tb), "=r"(scratch) :: "cc"); |
return tb; |
return tb; |
} |
} |
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