CVS log for src/sys/arch/riscv/riscv/vm_machdep.c

Up to [cvs.NetBSD.org] / src / sys / arch / riscv / riscv

Request diff between arbitrary revisions

Keyword substitution: kv
Default branch: MAIN

spaces to tabs

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

ASSERT that md_astpending it zero for the new lwp.

Use similar macro-magic to aarch64 armreg.h to add per-csr
read/write/set-bits/clear-bits inline functions.  Keep the
open-coded 32-bit version of riscvreg_cycle_read() than reads
a 64-bit cycle counter values.

Added benefit of fixing these so that the inline asm uses __volatile
and aren't opmtimised to nops by the compiler.

Remove unnecessary include of <sys/malloc.h>.

Sync w/ HEAD.

Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@

Mostly merge changes from HEAD upto 20200411

Merge changes from current as of 20200406

Trailing whitespace

Clean-up unnecessary inclusions of opt_coredump.h

update from HEAD

Sync with HEAD

file vm_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000

file vm_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000

Beginnings of RISCV kernel support.  Note that the pmap support is not yet
committed and probably won't be for awhile.  This is mostly preliminary
waiting for the supervisor specification to come out.  Lots of missing pieces
but it mostly builds.