CVS log for src/sys/arch/riscv/riscv/pmap_machdep.c

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Keyword substitution: kv
Default branch: MAIN

risc-v: probe the number of supported ASIDs

Flush the entire TLB if no ASIDs are supported on pmap_activate.

Fix and enable MULTIPROCESSOR

risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.

Whitespace.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Fix RV builds

Use similar macro-magic to aarch64 armreg.h to add per-csr
read/write/set-bits/clear-bits inline functions.  Keep the
open-coded 32-bit version of riscvreg_cycle_read() than reads
a 64-bit cycle counter values.

Added benefit of fixing these so that the inline asm uses __volatile
and aren't opmtimised to nops by the compiler.

tlb_update_addr gets called with the KERNEL_PID (ASID) so handle this
case.

#define<tab>

Checkpoint WIP.

QEMU RV64 virt can boot into virtual mode

OpenSBI v1.0
   ____                    _____ ____ _____
  / __ \                  / ____|  _ \_   _|
 | |  | |_ __   ___ _ __ | (___ | |_) || |
 | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
 | |__| | |_) |  __/ | | |____) | |_) || |_
  \____/| .__/ \___|_| |_|_____/|____/_____|
        | |
        |_|

Platform Name             : riscv-virtio,qemu
Platform Features         : medeleg
Platform HART Count       : 1
Platform IPI Device       : aclint-mswi
Platform Timer Device     : aclint-mtimer @ 10000000Hz
Platform Console Device   : uart8250
Platform HSM Device       : ---
Platform Reboot Device    : sifive_test
Platform Shutdown Device  : sifive_test
Firmware Base             : 0x80000000
Firmware Size             : 252 KB
Runtime SBI Version       : 0.3

Domain0 Name              : root
Domain0 Boot HART         : 0
Domain0 HARTs             : 0*
Domain0 Region00          : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01          : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02          : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address      : 0x0000000080200000
Domain0 Next Arg1         : 0x00000000bfe00000
Domain0 Next Mode         : S-mode
Domain0 SysReset          : yes

Boot HART ID              : 0
Boot HART Domain          : root
Boot HART ISA             : rv64imafdcsuh
Boot HART Features        : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count       : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count      : 16
Boot HART MIDELEG         : 0x0000000000001666
Boot HART MEDELEG         : 0x0000000000f0b509

------------
NetBSD start

sp:      0x0000_0000_80a0_2000
pc:      0x0000_0000_8020_0090
hart:    0x0000_0000_0000_0000
dtb:     0x0000_0000_bfe0_0000
l1:      0x0000_0000_80a0_2000
l2:      0x0000_0000_80a0_3000
uspace:  0x0000_0000_80a0_0000
bootstk: 0x0000_0000_80a0_2000
vtopdiff:0xffff_ffbf_7fe0_0000

bss:     0x0000_0000_808a_8bdc - 0x0000_0000_80a0_4000

0x0000_0000_80a0_3800: 0x0000_0000_2028_0821

kern 0x0000_0000_80a0_2000: 0x0000_0000_2008_002f
kern 0x0000_0000_80a0_2008: 0x0000_0000_2010_002f
kern 0x0000_0000_80a0_2010: 0x0000_0000_2018_002f
kern 0x0000_0000_80a0_2018: 0x0000_0000_2020_002f
kern 0x0000_0000_80a0_2020: 0x0000_0000_2028_002f
kern 0x0000_0000_80a0_2028: 0x0000_0000_2030_002f
kern 0x0000_0000_80a0_2030: 0x0000_0000_2038_002f
kern 0x0000_0000_80a0_2038: 0x0000_0000_2040_002f
kern 0x0000_0000_80a0_2040: 0x0000_0000_2048_002f
kern 0x0000_0000_80a0_2048: 0x0000_0000_2050_002f
kern 0x0000_0000_80a0_2050: 0x0000_0000_2058_002f
kern 0x0000_0000_80a0_2058: 0x0000_0000_2060_002f
kern 0x0000_0000_80a0_2060: 0x0000_0000_2068_002f
kern 0x0000_0000_80a0_2068: 0x0000_0000_2070_002f
kern 0x0000_0000_80a0_2070: 0x0000_0000_2078_002f
kern 0x0000_0000_80a0_2078: 0x0000_0000_2080_002f
dtb  0x0000_0000_80a0_2080: 0x0000_0000_2ff8_0027
PM
[   1.0000000] FDT<0xffffffc002000000>
[   1.0000000] consinit ok
[   1.0000000] NetBSD/riscv (fdt) booting ...
[   1.0000000] FDT /memory @ 0x80000000 size 0x40000000
[   1.0000000] init_riscv: memory start 80000000 end c0000000 (len 40000000)
[   1.0000000] bootargs: root=ld4a -v -x
[   1.0000000] bootflag 'r' not recognised
[   1.0000000] bootflag 'o' not recognised
[   1.0000000] bootflag 'o' not recognised
[   1.0000000] bootflag 't' not recognised
[   1.0000000] bootflag '=' not recognised
[   1.0000000] bootflag 'l' not recognised
[   1.0000000] bootflag ' ' not recognised
[   1.0000000] bootflag ' ' not recognised
[   1.0000000] ------------------------------------------
[   1.0000000]            kern_vtopdiff = 0xffffffbf7fe00000
[   1.0000000]             memory_start = 0x        80000000
[   1.0000000]               memory_end = 0x        c0000000
[   1.0000000]              memory_size = 0x        40000000
[   1.0000000]           kernstart_phys = 0x        80200000
[   1.0000000]             kernend_phys = 0x        80a00000
[   1.0000000]    VM_MIN_KERNEL_ADDRESS = 0xffffffc000000000
[   1.0000000]           kernstart_mega = 0xffffffc000000000
[   1.0000000]                kernstart = 0xffffffc000000000
[   1.0000000]                  kernend = 0xffffffc000800000
[   1.0000000]             kernend_mega = 0xffffffc000800000
[   1.0000000]    VM_MAX_KERNEL_ADDRESS = 0xffffffd000000000
[   1.0000000] ------------------------------------------
[   1.0000000] panic: kernel diagnostic assertion "msgbufaddr != 0" failed: file "/home/nick/netbsd/nbcvs/src/sys/arch/riscv/riscv/riscv_machdep.c", line 564

Fix thinko in tlb_record_asids memset size calculation.

Hacky build fixes

Pass the pmap in tlb_set_asid for the benefit of aarch64.

Sync with HEAD.

Fixup some pmap / VM related #defines and code

Mostly merge changes from HEAD upto 20200411

Merge changes from current as of 20200406

Trailing whitespace

With DEBUG defined, it's possible to execute a TLB-vs-segmap consistency
check from a (soft) interrupt handler.  But if a platform does not otherwise
require the pmap_tlb_miss_lock, then where will be a brief window of
inconsistency that, while harmless, will still fire an assertion in the
consistency check.

Fix this with the following changes:
1- Refactor the pmap_tlb_miss_lock into MI code and rename it from
   pmap_tlb_miss_lock_{enter,exit}() to pmap_tlb_miss_lock_{enter,exit}().
   MD code can still define the "md" hooks as necessary, and if so, will
   override the common implementation.
2- Provde a pmap_bootstrap_common() function to perform common pmap bootstrap
   operations, namely initializing the pmap_tlb_miss_lock if it's needed.
   If MD code overrides the implementation, it's responsible for initializing
   its own lock.
3- Call pmap_bootstrap_common() from the mips, powerpc booke, and riscv
   pmap_bootstrap() routines.  (This required adding one for riscv.)
4- Switch powerpc booke to the common pmap_tlb_miss_lock.
5- Enable pmap_tlb_miss_lock if DEBUG is defined, even if it's not otherwise
   required.

PR port-mips/55062 (Failed assertion in pmap_md_tlb_check_entry())

Misc changes in RISC-V.

Sync with HEAD

Misc changes in RISC-V. Start changing the memory layout, too.

update from HEAD

Sync with HEAD

file pmap_machdep.c was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000

file pmap_machdep.c was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000

Use sfence.vm instruction and change ptbr cse to sptbr csr

Beginnings of RISCV kernel support.  Note that the pmap support is not yet
committed and probably won't be for awhile.  This is mostly preliminary
waiting for the supervisor specification to come out.  Lots of missing pieces
but it mostly builds.