CVS log for src/sys/arch/riscv/riscv/locore.S

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Keyword substitution: kv
Default branch: MAIN

fix spelling mistakes, mainly in comments and log messages.

fix various typos in comments.

Fix and enable MULTIPROCESSOR

risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

Fix CONSADDR and save a label

Map the DTB using VM_KERNEL_DTB_BASE and CONSADDR using VM_KERNEL_IO_BASE

Use a local label

More register re-org

Fix after register re-org

More register use re-org.

Shuffle some register usage

Comment re-arragement

Remove unnecessary register assignments

Pretty print

Split out a bunch of functions from locore.S into cpu_switch.S

NFC

Don't set A, D in page table pointers, but do set them in leaf entries.

Beagle-v now boots to the msgbufaddr panic same as qemu

Use legacy SBI Console GetChar for earlycons.  It works on qemu.

Fix RV32 so it gets to the same point as RV64

Basic ddb and backtrace support.

[   1.0000000] panic: kernel diagnostic assertion "msgbufaddr != 0" failed: file "/home/nick/netbsd/nbcvs/src/sys/arch/riscv/riscv/riscv_machdep.c", line 564
[   1.0000000] cpu0: Begin traceback...
[   1.0000000] trace fp ffffffc000801dd0
[   1.0000000] fp ffffffc000801e10 ?() at ffffffc0001eee98
[   1.0000000] fp ffffffc000801e30 ?() at ffffffc0002ad984
[   1.0000000] fp ffffffc000801ee0 ?() at ffffffc000005430
[   1.0000000] cpu0: End traceback...
[   1.0000000] Trapframe @ 0xffffffc000801cb0 (cause=3 (breakpoint), status=0x100, pc=0xffffffc0000007e4, va=0):
[   1.0000000] ra =0xffffffc0001eee9c, sp =0xffffffc000801dd0, gp =0xffffffc0006a8f40, tp =                 0
[   1.0000000] s0 =0xffffffc000600ac0, s1 =            0x1000, s2 =0xffffffc000438df0, s3 =0xffffffc000801d80
[   1.0000000] s4 =0xffffffc0001eed78, s5 =0xffffffc0006d55f8, s6 =0xffffffc000801d88, s7 =0xffffffc0006dfdb8
[   1.0000000] s8 =0xffffffc000428c18, s9 =0xffffffc000801dd0, s10=0xffffffc0000a3822, s11=0xffffffc0006d55f8
[   1.0000000] a0 =              0x17, a1 =               0xa, a2 =                 0, a3 =0xffffffc00041f658
[   1.0000000] a4 =                 0, a5 =               0x1, a5 =                 0, a7 =               0x1
[   1.0000000] t0 =0xffffffc0006dfe30, t1 =0xffffffc000801bb8, t2 =0xffffffc000803000, t3 =              0x75
[   1.0000000] t4 =                 0, t5 =              0x63, t6 =               0x1
[   1.0000000] kernel: breakpoint
Stopped in pid 0.0 (system) at  ffffffc0000007e4:       c.ebreak
db>

Checkpoint WIP.

QEMU RV64 virt can boot into virtual mode

OpenSBI v1.0
   ____                    _____ ____ _____
  / __ \                  / ____|  _ \_   _|
 | |  | |_ __   ___ _ __ | (___ | |_) || |
 | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
 | |__| | |_) |  __/ | | |____) | |_) || |_
  \____/| .__/ \___|_| |_|_____/|____/_____|
        | |
        |_|

Platform Name             : riscv-virtio,qemu
Platform Features         : medeleg
Platform HART Count       : 1
Platform IPI Device       : aclint-mswi
Platform Timer Device     : aclint-mtimer @ 10000000Hz
Platform Console Device   : uart8250
Platform HSM Device       : ---
Platform Reboot Device    : sifive_test
Platform Shutdown Device  : sifive_test
Firmware Base             : 0x80000000
Firmware Size             : 252 KB
Runtime SBI Version       : 0.3

Domain0 Name              : root
Domain0 Boot HART         : 0
Domain0 HARTs             : 0*
Domain0 Region00          : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01          : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02          : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address      : 0x0000000080200000
Domain0 Next Arg1         : 0x00000000bfe00000
Domain0 Next Mode         : S-mode
Domain0 SysReset          : yes

Boot HART ID              : 0
Boot HART Domain          : root
Boot HART ISA             : rv64imafdcsuh
Boot HART Features        : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count       : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count      : 16
Boot HART MIDELEG         : 0x0000000000001666
Boot HART MEDELEG         : 0x0000000000f0b509

------------
NetBSD start

sp:      0x0000_0000_80a0_2000
pc:      0x0000_0000_8020_0090
hart:    0x0000_0000_0000_0000
dtb:     0x0000_0000_bfe0_0000
l1:      0x0000_0000_80a0_2000
l2:      0x0000_0000_80a0_3000
uspace:  0x0000_0000_80a0_0000
bootstk: 0x0000_0000_80a0_2000
vtopdiff:0xffff_ffbf_7fe0_0000

bss:     0x0000_0000_808a_8bdc - 0x0000_0000_80a0_4000

0x0000_0000_80a0_3800: 0x0000_0000_2028_0821

kern 0x0000_0000_80a0_2000: 0x0000_0000_2008_002f
kern 0x0000_0000_80a0_2008: 0x0000_0000_2010_002f
kern 0x0000_0000_80a0_2010: 0x0000_0000_2018_002f
kern 0x0000_0000_80a0_2018: 0x0000_0000_2020_002f
kern 0x0000_0000_80a0_2020: 0x0000_0000_2028_002f
kern 0x0000_0000_80a0_2028: 0x0000_0000_2030_002f
kern 0x0000_0000_80a0_2030: 0x0000_0000_2038_002f
kern 0x0000_0000_80a0_2038: 0x0000_0000_2040_002f
kern 0x0000_0000_80a0_2040: 0x0000_0000_2048_002f
kern 0x0000_0000_80a0_2048: 0x0000_0000_2050_002f
kern 0x0000_0000_80a0_2050: 0x0000_0000_2058_002f
kern 0x0000_0000_80a0_2058: 0x0000_0000_2060_002f
kern 0x0000_0000_80a0_2060: 0x0000_0000_2068_002f
kern 0x0000_0000_80a0_2068: 0x0000_0000_2070_002f
kern 0x0000_0000_80a0_2070: 0x0000_0000_2078_002f
kern 0x0000_0000_80a0_2078: 0x0000_0000_2080_002f
dtb  0x0000_0000_80a0_2080: 0x0000_0000_2ff8_0027
PM
[   1.0000000] FDT<0xffffffc002000000>
[   1.0000000] consinit ok
[   1.0000000] NetBSD/riscv (fdt) booting ...
[   1.0000000] FDT /memory @ 0x80000000 size 0x40000000
[   1.0000000] init_riscv: memory start 80000000 end c0000000 (len 40000000)
[   1.0000000] bootargs: root=ld4a -v -x
[   1.0000000] bootflag 'r' not recognised
[   1.0000000] bootflag 'o' not recognised
[   1.0000000] bootflag 'o' not recognised
[   1.0000000] bootflag 't' not recognised
[   1.0000000] bootflag '=' not recognised
[   1.0000000] bootflag 'l' not recognised
[   1.0000000] bootflag ' ' not recognised
[   1.0000000] bootflag ' ' not recognised
[   1.0000000] ------------------------------------------
[   1.0000000]            kern_vtopdiff = 0xffffffbf7fe00000
[   1.0000000]             memory_start = 0x        80000000
[   1.0000000]               memory_end = 0x        c0000000
[   1.0000000]              memory_size = 0x        40000000
[   1.0000000]           kernstart_phys = 0x        80200000
[   1.0000000]             kernend_phys = 0x        80a00000
[   1.0000000]    VM_MIN_KERNEL_ADDRESS = 0xffffffc000000000
[   1.0000000]           kernstart_mega = 0xffffffc000000000
[   1.0000000]                kernstart = 0xffffffc000000000
[   1.0000000]                  kernend = 0xffffffc000800000
[   1.0000000]             kernend_mega = 0xffffffc000800000
[   1.0000000]    VM_MAX_KERNEL_ADDRESS = 0xffffffd000000000
[   1.0000000] ------------------------------------------
[   1.0000000] panic: kernel diagnostic assertion "msgbufaddr != 0" failed: file "/home/nick/netbsd/nbcvs/src/sys/arch/riscv/riscv/riscv_machdep.c", line 564

fix various typos in comments and output/log messages.

Fix various typos in comments. Also add missing NetBSD RCS Id in some of these files.

Sync w/ HEAD.

sync with head

s/ENTRY/ENTRY_NP/ in a few places

Sync with HEAD.

Quick hack to make this link

Sync w/ HEAD.

Fix register usage

Fix a typo

Remove unnecessary local labels

Use correct instruction to load address of exception_userexit into RA

Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@

RCSID and whitespace police...

Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@

Use the 'mv' pseudo-instruction instead of the 'move' equivalent as 'mv'
is mentioned in the ISA documentation and it's used elsewhere.  That is,
let's use 'mv' everywhere for consistency.

Mostly merge changes from HEAD upto 20200411

Merge changes from current as of 20200406

Trailing whitespace

Sync with head.

oldlwp is always non-NULL in cpu_switchto so remove the test for NULL.

Hopefully fix some problems seen with MP support on non-x86, in particular
where curcpu() is defined as curlwp->l_cpu:

- mi_switch(): undo the ~2007ish optimisation to unlock curlwp before
  calling cpu_switchto().  It's not safe to let other actors mess with the
  LWP (in particular l->l_cpu) while it's still context switching.  This
  removes l->l_ctxswtch.

- Move the LP_RUNNING flag into l->l_flag and rename to LW_RUNNING since
  it's now covered by the LWP's lock.

- Ditch lwp_exit_switchaway() and just call mi_switch() instead.  Everything
  is in cache anyway so it wasn't buying much by trying to avoid saving old
  state.  This means cpu_switchto() will never be called with prevlwp ==
  NULL.

- Remove some KERNEL_LOCK handling which hasn't been needed for years.

Misc changes in RISC-V.

Sync with HEAD

Misc changes in RISC-V. Start changing the memory layout, too.

Fix tyop

update from HEAD

Sync with HEAD

Sync with HEAD.  (Note that most of these changes are simply $NetBSD$
tag issues.)

file locore.S was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000

Fix cpu_switchto(9) prototype in a comment

Sync with HEAD

file locore.S was added on branch nick-nhusb on 2015-04-06 15:18:01 +0000

Accept the one instruction penalty and just use PTR_LA instead of doing
the relocs ourselves.

Fix botch on putting user stack pointer into trapframe.

Optimize the exception handle a little bit more.

Since there is only "scratch" system register for use on exception, come
up with a new scheme for its use.  Use PTR_LA, INT_S/INT_L, etc.  Disable
interrupts when returning from exceptions.  Use L_CPU(tp) to get the curcpu
pointer.

When the cpu gets an exception from kernel mode, the sscratch register will be
0 and curlwp will be in the "tp" register.  When the cpu gets an exception from
user mode, the sscratch register will be a pointer to the current lwp.

When an exception happends, the sp is atomically swapped with the sscratch
register.

	If the sp is zero, the exception was a kernel exception and the
	kernel exception path is taken: sp and sscratch are swapped again
	so sscratch is zero again and then a trapframe is allocated from
	the kernel stack.  The t1 register is saved and then the pre-trapframe
	sp is written to the trapframe.

	If sp was non-zero, the exception was from user mode.  The tp register
	is temporarily saved in L_MD_TP(sp) and sp is moved tp.  tp now
	contains a pointer to the current lwp.  A pointer to the user
	trapframe is loaded from L_MD_UTF(tp).  Then t1 is saved in the
	trapframe so it can be used.  The old sp is fetched from sscratch
	while sscratch is zeroed (indicated kernel mode).  The old sp is
	saved in the trapframe.

	Upon exiting the exception, if the exception is returning to user
	mode, the contents of tp is written to sscratch.

Beginnings of RISCV kernel support.  Note that the pmap support is not yet
committed and probably won't be for awhile.  This is mostly preliminary
waiting for the supervisor specification to come out.  Lots of missing pieces
but it mostly builds.