CVS log for src/sys/arch/riscv/riscv/interrupt.c

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Default branch: MAIN

risc-v: expose intr_establish_xname

risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).