CVS log for src/sys/arch/riscv/riscv/cpu_switch.S

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Default branch: MAIN

Revision 1.4 / (download) - annotate - [select for diffs], Wed Mar 1 08:18:24 2023 UTC (4 weeks, 4 days ago) by riastradh
Branch: MAIN
CVS Tags: HEAD
Changes since 1.3: +8 -2 lines
Diff to previous 1.3 (colored)

riscv: Optimization: Omit needless membar when triggering softint.

When we are triggering a softint, it can't already hold any mutexes.
So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is
always done with atomic r/m/w, and we need not issue any explicit
barrier between ci->ci_curlwp = softlwp and a potential load of
mtx->mtx_owner in mutex_exit.

PR kern/57240

Revision 1.3 / (download) - annotate - [select for diffs], Thu Feb 23 14:56:23 2023 UTC (5 weeks, 2 days ago) by riastradh
Branch: MAIN
Changes since 1.2: +26 -1 lines
Diff to previous 1.2 (colored)

riscv: Add missing barriers in cpu_switchto.

Details in comments.

PR kern/57240

Revision 1.2 / (download) - annotate - [select for diffs], Sun Dec 4 16:29:35 2022 UTC (3 months, 3 weeks ago) by skrll
Branch: MAIN
CVS Tags: netbsd-10-base, netbsd-10
Changes since 1.1: +3 -3 lines
Diff to previous 1.1 (colored)

Restore t5 and t6 from the correct locations in exception_kernexit.

From Simon.

Revision 1.1 / (download) - annotate - [select for diffs], Fri Oct 14 07:58:30 2022 UTC (5 months, 2 weeks ago) by skrll
Branch: MAIN

Split out a bunch of functions from locore.S into cpu_switch.S

NFC

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