CVS log for src/sys/arch/riscv/riscv/cpu.c

Up to [cvs.NetBSD.org] / src / sys / arch / riscv / riscv

Request diff between arbitrary revisions

Keyword substitution: kv
Default branch: MAIN

Recognise the T-Head 9-Series CPU^Whart.

From Rui-Xiang Guo.

riscv: Make sure cpu0->ci_cpu_freq is initialized by cpu_attach.

Otherwise this stays zero, which screws up cpu_ipi_wait.

Fix and enable MULTIPROCESSOR

Remove duplicate .ci_cpl initialiser.

Always initialise ci_tlb_info in cpu_info_store[0].

Fixes non-MP boot for me.

risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).