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CVS log for src/sys/arch/riscv/riscv/cpu.c

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Default branch: MAIN


Revision 1.5 / (download) - annotate - [select for diffs], Sun Sep 3 08:48:20 2023 UTC (5 months, 3 weeks ago) by skrll
Branch: MAIN
CVS Tags: thorpej-ifq-base, thorpej-ifq, thorpej-altq-separation-base, thorpej-altq-separation, HEAD
Changes since 1.4: +24 -25 lines
Diff to previous 1.4 (colored)

Fix and enable MULTIPROCESSOR

Revision 1.4 / (download) - annotate - [select for diffs], Mon Aug 28 11:12:42 2023 UTC (5 months, 3 weeks ago) by skrll
Branch: MAIN
Changes since 1.3: +2 -3 lines
Diff to previous 1.3 (colored)

Remove duplicate .ci_cpl initialiser.

Revision 1.3 / (download) - annotate - [select for diffs], Sat Jun 24 07:23:07 2023 UTC (8 months ago) by skrll
Branch: MAIN
Changes since 1.2: +3 -3 lines
Diff to previous 1.2 (colored)

Always initialise ci_tlb_info in cpu_info_store[0].

Fixes non-MP boot for me.

Revision 1.2 / (download) - annotate - [select for diffs], Mon Jun 12 19:04:14 2023 UTC (8 months, 1 week ago) by skrll
Branch: MAIN
Changes since 1.1: +121 -12 lines
Diff to previous 1.1 (colored)

risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.

Revision 1.1 / (download) - annotate - [select for diffs], Sun May 7 12:41:48 2023 UTC (9 months, 2 weeks ago) by skrll
Branch: MAIN

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

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