CVS log for src/sys/arch/riscv/include/sysreg.h

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riscv: No volatile needed on asm to _read_ rounding mode, exceptions.

These instructions can be omitted if the return values are unused.
In contrast, _writes_ to the rounding mode or exceptions must not be
omitted (even if we ignore the return value, which is the old value
of the field).

I think "memory" is the wrong clobber on these asm blocks too; they
can't be reordered around _floating-point_ instructions, while
reordering around loads and stores is fine.  But I don't know how to
spell the right thing in gcclish.

riscv: Fix reading and writing frm and fflags.

The FRRM/FSRM and FRFLAGS/FSFLAGS instructions do all the masking and
shifting needed -- __SHIFTIN/__SHIFTOUT is wrong.

fix various typos in comments.

G/C ununsed and incorrect SIE_IM

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

leading whitespace... oops

Fix SR_WPRI.

Tweak csr_cycle_read and csr_asid_write for code style, and add some
KNF whitespace.

Document lots of bits.
Remove bits no longer in the RISC-V supervisor spec.
Update defines for the user-mode sstatus value.

Use similar macro-magic to aarch64 armreg.h to add per-csr
read/write/set-bits/clear-bits inline functions.  Keep the
open-coded 32-bit version of riscvreg_cycle_read() than reads
a 64-bit cycle counter values.

Added benefit of fixing these so that the inline asm uses __volatile
and aren't opmtimised to nops by the compiler.

Comment fix

Use uintptr_t consistently rather than register_t

The supervisor status register is the native word width, not fixed
at 32 bits.

Parentheses police.

Add cause register trap types, and some macros to access cause register
fields.

whitepsace nit

Fix typo in SATP_MODE_SV64

Consistency nit: use "__volatile" instead of "volatile" with asm()s.

Add SATP modes for bare, SV57 and SV64.

#define<tab>

Remove unnecessary cast.

Sync with HEAD.

Provide riscvreg_satp_{read,write}

Indent the FCSR_FRM value #defines

Sync w/ HEAD.

interupt -> interrupt

Sync w/ HEAD.

Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@

Miscellaneous updates to reflect riscv-privileged-20190608.pdf

Some from zmcgrew@

Add SATP_MODE values

Whitespace

Update CAUSE_* defines to reflect riscv-privileged-20190608.pdf

Mostly merge changes from HEAD upto 20200411

Merge changes from current as of 20200406

Trailing whitespace

Misc changes in RISC-V.

update from HEAD

Sync with HEAD

file sysreg.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000

No more fatc (replaced by sfence.vm instruction).

Beginnings of RISCV kernel support.  Note that the pmap support is not yet
committed and probably won't be for awhile.  This is mostly preliminary
waiting for the supervisor specification to come out.  Lots of missing pieces
but it mostly builds.

New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)