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CVS log for src/sys/arch/riscv/fdt/riscv_fdtvar.h

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Revision 1.2 / (download) - annotate - [select for diffs], Mon Jan 1 13:51:56 2024 UTC (2 months ago) by skrll
Branch: MAIN
Changes since 1.1: +2 -1 lines
Diff to previous 1.1 (colored)

Perform more checks before establishing external interrupt handlers for
each hart.  The VisionFive2 DTS list the S7 core with status = "disabled".

Revision 1.1 / (download) - annotate - [select for diffs], Mon Jun 12 19:04:13 2023 UTC (8 months, 3 weeks ago) by skrll
Branch: MAIN
CVS Tags: thorpej-ifq-base, thorpej-ifq, thorpej-altq-separation-base, thorpej-altq-separation

risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.

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