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CVS log for src/sys/arch/riscv/fdt/cpu_fdt.c

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Keyword substitution: kv
Default branch: MAIN

Revision 1.4: download - view: text, markup, annotated - select for diffs
Mon Jan 1 13:51:56 2024 UTC (11 months ago) by skrll
Branches: MAIN
CVS tags: perseant-exfatfs-base-20240630, perseant-exfatfs-base, perseant-exfatfs, HEAD
Diff to: previous 1.3: preferred, colored
Changes since revision 1.3: +6 -7 lines
Perform more checks before establishing external interrupt handlers for
each hart.  The VisionFive2 DTS list the S7 core with status = "disabled".
Revision 1.3: download - view: text, markup, annotated - select for diffs
Sun Sep 3 08:48:19 2023 UTC (14 months, 4 weeks ago) by skrll
Branches: MAIN
CVS tags: thorpej-ifq-base, thorpej-ifq, thorpej-altq-separation-base, thorpej-altq-separation
Diff to: previous 1.2: preferred, colored
Changes since revision 1.2: +25 -33 lines
Fix and enable MULTIPROCESSOR
Revision 1.2: download - view: text, markup, annotated - select for diffs
Mon Jun 12 19:04:13 2023 UTC (17 months, 2 weeks ago) by skrll
Branches: MAIN
Diff to: previous 1.1: preferred, colored
Changes since revision 1.1: +156 -2 lines
risc-v: MULTIPROCESSOR support

Add MULTIPROCESSOR support for RISC-V, but leave disabled for the moment
as it's not 100% stable.

Some other improvements to spl and cpu identification / reporting.
Revision 1.1: download - view: text, markup, annotated - select for diffs
Sun May 7 12:41:48 2023 UTC (18 months, 3 weeks ago) by skrll
Branches: MAIN
RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).
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