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CVS log for src/sys/arch/riscv/dev/plic_fdt.c

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Default branch: MAIN


Revision 1.5 / (download) - annotate - [select for diffs], Fri Feb 9 18:39:53 2024 UTC (3 weeks, 3 days ago) by andvar
Branch: MAIN
CVS Tags: HEAD
Changes since 1.4: +3 -3 lines
Diff to previous 1.4 (colored)

s/incompatiable/incompatible/ in error messages.

Revision 1.4 / (download) - annotate - [select for diffs], Mon Jan 1 13:51:56 2024 UTC (2 months ago) by skrll
Branch: MAIN
Changes since 1.3: +57 -45 lines
Diff to previous 1.3 (colored)

Perform more checks before establishing external interrupt handlers for
each hart.  The VisionFive2 DTS list the S7 core with status = "disabled".

Revision 1.3 / (download) - annotate - [select for diffs], Sat Sep 2 09:58:15 2023 UTC (6 months ago) by skrll
Branch: MAIN
CVS Tags: thorpej-ifq-base, thorpej-ifq, thorpej-altq-separation-base, thorpej-altq-separation
Changes since 1.2: +7 -7 lines
Diff to previous 1.2 (colored)

Be clear about hart vs cpu. NFCI.

Revision 1.2 / (download) - annotate - [select for diffs], Sat Sep 2 09:29:59 2023 UTC (6 months ago) by skrll
Branch: MAIN
Changes since 1.1: +4 -10 lines
Diff to previous 1.1 (colored)

Simplify plic_fdt_intr_disestablish by calling plic_intr_disestablish

Revision 1.1 / (download) - annotate - [select for diffs], Sun May 7 12:41:48 2023 UTC (9 months, 4 weeks ago) by skrll
Branch: MAIN

RISC-V support that works on QEMU with a single hart.

Thanks for Simon Burge for plic(4).

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