CVS log for src/sys/arch/powerpc/powerpc/trap_subr.S

Up to [cvs.NetBSD.org] / src / sys / arch / powerpc / powerpc

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Keyword substitution: kv
Default branch: MAIN

fix typos in word "access" and it derivatives, mainly in comments.

Sync with HEAD.

Add a provision for a per-cpu battable.  Each CPU starts with the global
one, but this allows CPUs to temporarily switch to an alternate battable
if needed.

No need to work around for IBM405 Errata 77; ibm4xx does not use this file.

Include required opt_*.h for sure.

Style and cosmetic changes. No binary changes intended.

Merge changes from current as of 20200406

Pull up following revision(s) (requested by rin in ticket #755):

	sys/arch/evbppc/conf/std.virtex: revision 1.4
	sys/arch/powerpc/powerpc/trap_subr.S: revision 1.81
	sys/arch/powerpc/ibm4xx/4xx_trap_subr.S: revision 1.8
	sys/arch/evbppc/conf/std.walnut: revision 1.9
	common/lib/libc/arch/powerpc/atomic/atomic_op_asm.h: revision 1.7
	sys/arch/powerpc/include/asm.h: revision 1.49
	common/lib/libc/arch/powerpc/atomic/atomic_cas.S: revision 1.9
	sys/arch/powerpc/ibm4xx/trap_subr.S: revision 1.28
	sys/arch/powerpc/include/lock.h: revision 1.15
	sys/arch/evbppc/conf/std.obs266: revision 1.3
	common/lib/libc/arch/powerpc/atomic/atomic_swap.S: revision 1.8
	sys/arch/powerpc/powerpc/locore_subr.S: revision 1.61
	sys/arch/powerpc/powerpc/lock_stubs.S: revision 1.12
	sys/arch/evbppc/conf/std.obs200: revision 1.5

Implement workaround for IBM405 Errata 77 (aka CPU_210), where
interrupted stwcx. may errantly write data to memory:

     https://elinux.org/images/1/1d/Ppc405gp-errata.pdf

This is because stwcx. is split into two pieces in the pipeline.

We need to
(1) insert dcbt before every stwcx. instruction, as well as
(2) insert sync before every rfi/rfci instruction.

It is unclear which processors are affected, but according to Linux,
all 405-based cores up until 405GPR and 405EP are affected:

     https://github.com/torvalds/linux/blob/master/arch/powerpc/platforms/40x/Kconfig#L140

For kernel, this workaround can be restricted to affected processors.

However, for kernel modules and userland, we have to enable it for all
32bit powerpc archs in order to share common binaries as before.
Proposed on port-powerpc:

     http://mail-index.netbsd.org/port-powerpc/2020/02/21/msg003583.html

Implement workaround for IBM405 Errata 77 (aka CPU_210), where
interrupted stwcx. may errantly write data to memory:

    https://elinux.org/images/1/1d/Ppc405gp-errata.pdf

This is because stwcx. is split into two pieces in the pipeline.

We need to
(1) insert dcbt before every stwcx. instruction, as well as
(2) insert sync before every rfi/rfci instruction.

It is unclear which processors are affected, but according to Linux,
all 405-based cores up until 405GPR and 405EP are affected:

    https://github.com/torvalds/linux/blob/master/arch/powerpc/platforms/40x/Kconfig#L140

For kernel, this workaround can be restricted to affected processors.
However, for kernel modules and userland, we have to enable it for all
32bit powerpc archs in order to share common binaries as before.

Proposed on port-powerpc:

    http://mail-index.netbsd.org/port-powerpc/2020/02/21/msg003583.html

Sync with HEAD

Sync with HEAD

Retire ipkdb entirely. The option was removed from the config files
yesterday.

ok kamil christos

Sync with HEAD

Fixed non-critical typo in tlbdsmiss: %r8 -> 8.

Rebase to HEAD as of a few days ago.

Rebase.

cmpl wants four operands, so use the shorter cmplw instead.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Avoid a few instructions since we know CURLWP is in %r13

resync from head

make PPC_OEA64_BRIDGE mode work
from Phileas Fogg

sync with head

Use %r6 for setting PSL_RI, not %r30 since r30 needs to be preserved.

Add conditionals so this should work for the MPC8XX SoCs.
Turn on PSL_RI in interrupts.

sync with head

merge to -current.

Enable XBSEN and HIGHBAT for OEA 7455 and related CPUs.
The BAT entries now have a resolution of 8MB.  (Adjacent entries are merged
up to a total of 2GB per entry).

Remove white-spaces.

Catchup with rmind-uvmplock merge.

Remove #if 0 block

Let ext_intr adjust ci_idepth.
Remove some dead code.
Use the right register for SRR1

sync with head

Sync with HEAD.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

sync with head

Fix bogus idepth on OEA.

Don't store the new idepth into the trapframe, use the idepth at the start
of the interrupt.

sync with head

If a CPU has HIGHBAT, then use them.  We dynamically change dsitrap to
select between bats 4-7 when HIGHBAT is detected.

Change battable to have a granularity of 8MB.

Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

Add SPE (signal processing engine) support for mpc85xx/booke.  Think of it
as AltiVec-lite (really lite).  Genercize AltiVec support so that it could
the same interface could support SPE as well.  Rework the FPU support along
the same lines.  Move the __asm() to their own XXX_subr.S (altivec, fpu, spe).

Deal with trapframe changes.  Rework trap_subr.S to take advantage of the
simplier world.

sync with head

Fix language.

sync with head.

Sync with HEAD.

Sync with HEAD.

Sync with wrstuden-revivesa-base-2.

Sync with netbsd-4.

Pull up following revision(s) (requested by matt in ticket #1174):
	sys/arch/powerpc/powerpc/trap_subr.S: revision 1.65
Fix bug where SRR1 (%r2) was being accidently misused and modifed
in place of segreg (%r1).
> From Konrad Karpowicz <konradk at pacomp dot pl>.

Pull up following revision(s) (requested by matt in ticket #1950):
	sys/arch/powerpc/powerpc/trap_subr.S: revision 1.65
Fix bug where SRR1 (%r2) was being accidently misused and modifed
in place of segreg (%r1).
> From Konrad Karpowicz <konradk at pacomp dot pl>.

Fix bug where SRR1 (%r2) was being accidently misused and modifed
in place of segreg (%r1).

From Konrad Karpowicz <konradk at pacomp dot pl>.

Sync w/ -current. 34 merge conflicts to follow.

sync with head

Sync with HEAD.

Make oea_init() support systems with high-vector configurations (i.e exception
vectors at 0xfff00000), and trap_subr.S allows the kernel to be in a memory
region which is not reachable by absolute branch instructions (ba and bla).

High-vector support can be enabled by option PPC_HIGH_VEC, and long-branches
to the kernel are enabled by the option DISTANT_KERNEL.

sync with HEAD

Sync with HEAD.

sync with head.

Code to disable BAT use on cpu's that either don't have BAT's, or don't
gain any benefit from them.  This nets a small speedup on the POWER3, and
is probably needed for POWER5, which might not emulate BATs like the 3 does.
Also, thanks to Matt Thomas, who suggested re-using alitrap rather than
writing a new dsinobattrap that would have looked remarkably identical
when finished.

Ifdef out all the MPC601 code with PPC_OEA601.  Now only arches that have the
possibility of running on an MPC601, are infected with all the extra code
and nops that it added.

Also, fix compilation that I broke with the pmap code, by adding
oeacpufeat to the locores of various ppc arches.  Noted by mlelstv.

Rewrite a big chunk of the pmap and locore code for powerpc to better
deal with the 64bit bridge mode.  pmap changes by Matt Thomas, rest by myself.

Change pmap.c to work similar to exec_elf.c to allow us to compile in
multiple pmaps to a single kernel.  This allows the pmap for bridge64 to
co-exist with the 32bit pmap.

Yank __HAVE_PMAP_PHYSSEG from all the oea code.

Add a new global, "oeacpufeat", which is used early in locore to determine
certain cpu features.  This allows us to conditionalize code early in the boot
for certain CPUs that have special needs.

Yank most of the ifdef PPC_OEA_BRIDGE64 code from almost every file it was
found in.  Some of it seemed incorrect, and my 7044 booted just fine
without it.  It would appear that the bridge cpus treat BAT instructions
as nops, so they seem to be safe.

In ofppc, check the oeacpufeat, and if we are on a 64bit proc, clear
MSR[SF], and ASR[V].

With all of these changes, a kernel with both PPC_OEA and PPC_OEA_BRIDGE64
will boot on the POWERIII-2 cpu.  However, it will not yet boot on a 32bit
cpu, because of CACHELINESIZE.  Work remains to be done there to fix that.

sync with head

Sync with HEAD

Add support to ofppc for the IBM 7044-270 machine.  This is a POWER3-II
based machine.  Currently the kernel to run on this machine is
incompatible with the standard GENERIC kernel, so for now, we have a
separate GENERIC_B64. Eventually, I hope to combine the two.

Please note, this is a port of 32bit ofppc, not a powerpc64 port.

Thanks to Matt Thomas and Kevin Bowling for helping to make this port
possible.

Summary of changes:

Change ofwpci to use the ofmethod config for configuring the PCI bus,
rather than indirect configuration.
Move the wiring of the interrupt controllers from at the start of the
boot, into the configuration of the first PCI bus.
Rewrite the map_isa_ioregs() hack to work on a machine without BATs
Fix a ton of bugs in the genofw_find_pics routine, and in the map_space code.
Split the pic_openpic into openpic_common and pic_openpic.
Create a new pic_distopenpic driver, for the distributed openpic found on
some newer IBM machines.
Fix a bad panic in pmap_extract on 64bit bridge mode

sync with head.

sync with head

sync with head

1st cut of Powermac G5 support (uses bridge mode).

merge ktrace-lwp.

Pull up revision 1.57 (requested by matt in ticket #1286):
Don't enable interrupts while calling trap() if the trapping frame
didn't have them enabled either.
Addresses PR port-macppc/29559.

Pull up revision 1.57 (requested by matt in ticket #1286):
Don't enable interrupts while calling trap() if the trapping frame
didn't have them enabled either.
Addresses PR port-macppc/29559.

sync with -current

sync with head.  xen and whitespace.  xen part is not finished.

Sync with HEAD.

Don't enable interrupts while calling trap() if the trapping frame
didn't have them enabled either.

Addresses PR port-macppc/29559.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

Get rid of the silly CPU601 hooks and move BAT register restoration and
obliteration to RESTORE_{KERN,USER}_SRS, respectively; have oea_init()
patch these sequences to be skipped on non-MPC601s.  The code sequence
matching heuristic isn't as pretty as the one for VRSAVE and MQ but works
well enough with the current structure of the trap code, and can be easily
updated when necessary.

Repair a comment misplaced in rev. 1.43.

Make some comments line up.

Remove unused ddbsave define.

Restore ci_curpm since it re-enables 603 to working state.

Rework ddblow so that if PSL_PR == 1, it dispatches directly to the
trap handler and bypasses the ddbtrap code.

Add code to drop into DDB if you get a DSI fault on the current stack page.

D'oh!  The PCB can't be accessed with the MMU off.  So get the pmap pointer
*before* disabling the MMU.

Nuke ci_curpm and curpm.  Nuke pcb_pmreal.  Those were use for spill stacks
and those no longer exist.  for few uses that need CURPM, use CURPCB/PCB_PM

Nuke ci_spillstk/CI_SPILLSTK.  No longer needed.

Add a type for trapstart so ddb will use it.

Don't overwrite the value of DAR in r30.  Use r31 instead.

Change bc x,y,z to their simplified mnemonics.  During a kernel DSI fault,
if the exception address is < 1 page away from the KSP, switch to the that
CPU's spill stack to handle the trap.  Otherwise you can get in a infinite
DSI fault loop.

Eliminate stmw/lmw substituting the individual load/store instructions.
Use more symbolic constants.  These are now safe for use on PPC64.

Use symbolic register names (%rN and %crN) throughout.  Change a few more
numeric constants to their symbolic counterparts.

Convert most numeric constants to their symbolic equivalents.  (step 2 of
cleaning up this file).

Replace 'm[tf]sprg x,y' with the appropriate 'm[tf]sprg[0-3] r' (this makes the
SPRG used unambiguous).  This causes no change in the generated object.

Enhance db_trace to understand syscalls and print the syscall number
that the user requested.  For example:

0xd5c56f40: SC trap #240 by 0x15668c60: srr1=0xd032
            r1=0xffffe470 cr=0x44000045 xer=0 ctr=0xeff27ab8

Put an isync at the end of the RESTORE_SRS() macro. This is the
recommended workaround for a mtsr/mtsrin errata with PPC750 cpus.

Add LINTSTUBs and make oea_init() agree with them.

Pass the address of the intrframe to the ext_intr routine.

witch from xor r,r,r to li r,0 to set a register to 0.  It's clearer (and
better for G4 processors).

Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

Perform a rototill of the powerpc code.  Mandate use of SPRG0 to store
a pointer to current cpu's cpu_info structure.  Use cpu_info for
intstk,intr_depth,still_stk,idle_pcb,curpcb,curlwp,etal even on
non-MULTIPROCESSOR machines.  Add common macros GET_CPUINFO and
INIT_CPUINFO to get and initialize the cpu_info struct on startup.  Make
ibm4xx use the standard <powerpc/frame.h>.  Use IFRAME_xx in ibm4xx
trap_subr.S instead of explicit magic offsets.  Move INTSTK and SPILLSTK
to std.<platform>.  Change faultbuf to a struct instead of an array.

On MPC6XX cpus, stop using the vector page for temporary space and use
reserved space in cpu_info.

Whitespace nit in previous.

MPC601 support bits:
* install 601-specific DSI and RUNMODETRC trap handlers
* save/restore MQ in trapframe, add MQ hooks to DDB
* extend battable to 512 entries to hold the 601's 8M translations
* instead of adding I/O to BAT starvation, set up segment registers
  for Memory-Forced I/O Controller Interface Access
* sync after tlbie

Merge the nathanw_sa branch.

Remove superflous "#endif" invented by last pullup which causes build
failures on PPC architectures. (requested by jdolecek in ticket #970)

Pull up revision 1.22 (requested by matt in ticket #373):
Revamp how SR(s) are loaded on the user/kernel boundary.  We now load all
16 SR registers when transitioning between kernel and user.  Also, don't
reload the kernel SR(s) on every trap but only on traps from user space.
Instead of loading magic SRs for the kernel, load the kernel SRs from the
kernel_pmap_.  This makes trap_subr.S completely ignorant of SR uses and
so they can change with having to change trap_subr.S.  Also note that
since the user and kernel get complete SR sets, user VA space can now be
increased to 4GB if desired.

Catch up to -current.

Move pte_spill calls from trap_subr to trap().  Count the number of
"evictions" and avoide calling pmap_pte_spill if there are no evictions
for the current pmap.  Make the ISI execption use the default exception
code.  Remove lots of dead stuff from trap_subr.

Make olink use TAILQ instead of LIST and be sorted with evicted entries
first and resident entries last.  Make use of this knowledge to make
pmap_pte_spill do a fast exit.

sync kqueue branch with HEAD

catch up with -current.

Catch up with powerpc rototilling.

be sure to re-enable interrupts before calling trap() a second time
due to an AST.  the rule is that we must always have interrupts
enabled when acquiring kernel_lock, so that we can process blocking IPIs
from another CPU which is already holding kernel_lock.
reduce differences between the MP and non-MP versions of this file.

use a completely separate trap handler for syscall traps.
this reduces syscall overhead by 10% to 20% depending on cpu type.

Catch up to -current.

resync the MP and non-MP trap_subr's.

Cleanup AltiVec data stream issues with context switching.  Don't stop
data streams on execptions/interrupts since the processor will suspend
them for us.  Only stop them on 1) process exit, 2) another process gets
its address space loaded, and 3) (for completeness only) we save a process's
AltiVec context.

catch up with -current.

Peform a rototill over the powerpc-based ports.

Move the trap/vector initialization for MPC6xx ports to mpc6xx_machdep.c
Also move softnet, install_extintr, mapiodev, kvtop.  Add common BAT
initialization code.

Add user Altivec support.

Fix calls to OF_call_method in macppc/macppc/machdep.c.

Use ci_fpuproc in cpu_info instead of separate fpuproc.

Add separate syscall.c and defined __HAVE_SYSCALL_INTERN.

Make traps even smaller by noticing the checking of privilege mode and
use of curpcb/USPACE is common and move that into the common trap processing.

Revamp how SR(s) are loaded on the user/kernel boundary.  We now load all
16 SR registers when transitioning between kernel and user.  Also, don't
reload the kernel SR(s) on every trap but only on traps from user space.
Instead of loading magic SRs for the kernel, load the kernel SRs from the
kernel_pmap_.  This makes trap_subr.S completely ignorant of SR uses and
so they can change with having to change trap_subr.S.  Also note that
since the user and kernel get complete SR sets, user VA space can now be
increased to 4GB if desired.

catch up with -current on kqueue branch

Catch up to -current.

* On the 601, obliterate all BAT entries when returning from kernel to
  userlevel; this is necessary due to the 601, unlike other 6xx, having
  no concept of separated Valid_user vs. Valid_supervisor for BATs.
* When crossing the kernel/userlevel boundary, have platform-provided
  hooks set up the two fixed BAT entries, and possibly additional
  segment registers to redeem the 601's BAT limitations.

Both of the above are only built if the $MACHINE provides these hooks,
sparing others the pain.

Express tempsave and disisave addresses using the symbolic names of the
exception handlers which they are `borrowed' from.

Fix a swapped register pasto(?) introduced in rev. 1.17.

Convert the spill stack frame to use symbolic offset names; inspired by
a conversation with Matt Thomas.

Use a common genassym.cf for all the PPC_MPC6XX ports.  Add a makeoptions to
std.foo to indicate the directory to get genassym.cf from.  Add an intrframe
to <powerpc/frame.h> and make trap_subr.S use symbolic offsets into it.

Don't do random replacement in isitrap601; just like isitrap.

Catch up to -current.
(CVS: It's not just a program. It's an adventure!)

Add separate 601 versions of DSI/ISI trap entries, considering the
different battable entry format and the combined BAT implementation.

Catch up with -current.

Also reset segment register 0 on kernel entry: there may not always be
a fixed BAT entry covering segment 0, or not completely covering it,
and we do restore it on return to user level already.

Catch up to -current.

Add a comment to where we increment intr_depth to show that intstk+INTSTK
== intr_depth. (gag)

More catchup.

Sync kqueue branch with -current.

add support for kgdb over zs

Update the kqueue branch to HEAD.

file trap_subr.S was added on branch nathanw_sa on 2002-01-11 23:38:43 +0000

Make sure to restore SR 0 since returning from a syscall is actually
one way of doing a process context switch.

Reset segment registers 1-7 upon entry to kernel (via trap or interrupts)
so that the bat spill code won't run into spurious valid user pages and
treat them as kernel pages.  Restore segment registers 1-7 upon return to
user mode from either a trap or interrupt.   XXX  eventually do all 16 SRs

Use SPR_xxx for the *MISS HASH CMP, etc.

Catch up to -current.

Use _C_LABEL() for externally referenced symbols.

Globalize trapexit.  Improve db_trace.c so that you can trace thru traps!
Rework the output so that is also prints the frame address by default.

Rename pte_spill to pmap_pte_spill.  Fix pmap_clear_{referenced,modify}
to return the previous state of the bit.  Make it compile under
-Wmissing-prototypes -Wall.  Change around some debug stuff.

Introduce a new & faster pmap for the MPC6xx (60x, 7xx, 7xxx) PPC CPUs.
Move MPC6xx dependent header files to powerpc/include/mpc6xx/

Catch up with -current.

Sync with HEAD.

Remove MULTIPROCESSOR part.  (moved to separate file)

Sync with HEAD

Make want_resched and astpending per-CPU.
Add some per-CPU variables to cpu_info.

Sync with HEAD.

Move INTSTK and SPILLSTK definitions to locore.[Ss] to allow allocation of
them in early startup.

Sync with HEAD.

file trap_subr.S was added on branch thorpej_scsipi on 2000-11-22 16:01:30 +0000

Trap routines from the macppc port, to be used by other PowerPC
ports (only amigappc's differs).