CVS log for src/sys/arch/powerpc/powerpc/pmap_subr.c

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Default branch: MAIN

Include missing opt_ppcarch.h.

Style and cosmetic changes. No binary changes intended.

Sync with HEAD

disable the MULTIPROCESSOR case in pmap_syncicache() because:
- __syncicache() wants a virtual address, not a pa
- this crashes on G5 SMP
- the rest of the function does the same as __syncicache() except it turns
  the MMU off first so physical addresses work
with this, my PCIe G5 boots SMP

sync with head

merge to -current.

Use kmem instead of malloc.  Remove unneeded <sys/malloc.h> includes.

Sync with HEAD.

sync with head

Sync with HEAD

When an OEA kernel is configured for multiple MMU types, use the new
powerpc fixup mechanism to bind the kernel to a particular MMU.  This
avoids an indirect call for every pmap call.

Put VM_PAGE_TO_MD() definition in one place.  No functional changes.

Machine dependent code is considered as part of UVM.  Include
internal API header.

Sync with HEAD.

Use VM_PAGE_TO_MD() to locate struct vm_page_md.  No functional
changes.

Fix build.

sync with head

Use VM_PAGE_TO_MD().  Only compile tested.

Fixed typo: PPC_OEA64_BIRDGE -> PPC_OEA64_BRIDGE

Sync with HEAD.

sync with head.

sync with head.

Remove clause 3 and 4 from TNF licenses

sync with HEAD

Sync with HEAD.

sync with head.

Rewrite a big chunk of the pmap and locore code for powerpc to better
deal with the 64bit bridge mode.  pmap changes by Matt Thomas, rest by myself.

Change pmap.c to work similar to exec_elf.c to allow us to compile in
multiple pmaps to a single kernel.  This allows the pmap for bridge64 to
co-exist with the 32bit pmap.

Yank __HAVE_PMAP_PHYSSEG from all the oea code.

Add a new global, "oeacpufeat", which is used early in locore to determine
certain cpu features.  This allows us to conditionalize code early in the boot
for certain CPUs that have special needs.

Yank most of the ifdef PPC_OEA_BRIDGE64 code from almost every file it was
found in.  Some of it seemed incorrect, and my 7044 booted just fine
without it.  It would appear that the bridge cpus treat BAT instructions
as nops, so they seem to be safe.

In ofppc, check the oeacpufeat, and if we are on a 64bit proc, clear
MSR[SF], and ASR[V].

With all of these changes, a kernel with both PPC_OEA and PPC_OEA_BRIDGE64
will boot on the POWERIII-2 cpu.  However, it will not yet boot on a 32bit
cpu, because of CACHELINESIZE.  Work remains to be done there to fix that.

sync with HEAD

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

sync with head.

sync with HEAD

Sync with head.

Sync with head.

Update to HEAD.

Fix for yamt-idlelwp merge.

merge yamt-idlelwp branch.  asked by core@.  some ports still needs work.

from doc/BRANCHES:

	idle lwp, and some changes depending on it.

	1. separate context switching and thread scheduling.
	   (cf. gmcgarry_ctxsw)
	2. implement idle lwp.
	3. clean up related MD/MI interfaces.
	4. make scheduler(s) modular.

Adapt powerpc to yamt-idlelwp.  Nuke cpu_setfunc.
Don't define _HAVE_BITENDIAN_BITOPS.  Misc cleanups.

- sync with head.
- move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.

sync with head.

TRUE -> true, FALSE -> false

Replace the Mach-derived boolean_t type with the C99 bool type.  A
future commit will replace use of TRUE and FALSE with true and false.

sync with head.

sync with head

sync with head

1st cut of Powermac G5 support (uses bridge mode).

sync with head.

Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

Stop false uninitialized variable warning.

__KERNEL_RCSID()

Use PAGE_SIZE rather than NBPG.

Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

Sync with HEAD.

If MULTIPROCESSOR, just accept the penalties of doing BAT flipping when
syncing the icache.

sync kqueue branch with HEAD

catch up with -current.

Catch up to -current.

file pmap_subr.c was added on branch kqueue on 2002-09-06 08:39:26 +0000

Use "b" constraint for base registers (indexed addressing mode).

Add evcnt's for common pmap activities when PMAPCOUNTERS is defined
in the config file.

Re-enable PTE_EXEC.  PTE_EXEC is now also cleared in pmap_zero_page,
pmap_copy_page, and pmap_clear_modify (pmap_clear_bit).  Remove #ifdef
MULTIPROCESSOR since the cache instructions operate on all caches on
all processors.

Catch up to -current.

file pmap_subr.c was added on branch nathanw_sa on 2002-08-01 02:43:10 +0000

remove a local copy of mfmsr().

catch up with -current.

file pmap_subr.c was added on branch gehenna-devsw on 2002-07-21 13:00:49 +0000

Make sure that pmap_zero_page and pmap_copy_page don't make calls or
reference while relocation is disabled since the stack will be inaccessible.
Add support for using AltiVec in pmap_zero_page and pmap_copy_page on
AltiVec capable processors.

Add a common file to do pmap_zero_page/pmap_copy_page/pmap_pageidlezero and
pmap_syncicache.  This file uses a ppc feature in a sick and twisted way
to avoid mapping the physical pages used by those routines.  It performs
the operations with the MMU disabled but PPC exception save and retstore
the machine state and are invoked with the MMU disabled, this doesn't have
an adverse effect on the system.

Currently only enable for MPC6xx and !OLDPMAP.