CVS log for src/sys/arch/powerpc/powerpc/locore_subr.S

Up to [cvs.NetBSD.org] / src / sys / arch / powerpc / powerpc

Request diff between arbitrary revisions

Keyword substitution: kv
Default branch: MAIN

Pull up following revision(s) (requested by riastradh in ticket #1859):

	sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
	sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
	sys/arch/aarch64/aarch64/locore.S: revision 1.91
	sys/arch/mips/include/asm.h: revision 1.74
	sys/arch/hppa/include/cpu.h: revision 1.13
	sys/arch/arm/arm/armv6_start.S: revision 1.38
	 (applied also to sys/arch/arm/cortex/a9_mpsubr.S,
	 sys/arch/arm/cortex/a9_mpsubr.S,
	 sys/arch/arm/cortex/cortex_init.S)
	sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
	sys/arch/mips/mips/locore.S: revision 1.229
	sys/arch/alpha/include/asm.h: revision 1.45
	 (applied to sys/arch/alpha/alpha/multiproc.s)
	sys/arch/sparc64/sparc64/locore.s: revision 1.432
	sys/arch/vax/vax/subr.S: revision 1.42
	sys/arch/mips/mips/locore_mips3.S: revision 1.116
	sys/arch/ia64/ia64/machdep.c: revision 1.44
	sys/arch/arm/arm32/cpuswitch.S: revision 1.106
	sys/arch/sparc/sparc/locore.s: revision 1.284
	(all via patch)

aarch64: Add missing barriers in cpu_switchto.
Details in comments.

Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.

PR kern/57240

alpha: Add missing barriers in cpu_switchto.
Details in comments.

arm32: Add missing barriers in cpu_switchto.
Details in comments.

hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?

ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)

mips: Add missing barriers in cpu_switchto.
Details in comments.

powerpc: Add missing barriers in cpu_switchto.
Details in comments.

sparc: Add missing barriers in cpu_switchto.

sparc64: Add missing barriers in cpu_switchto.
Details in comments.

vax: Note where cpu_switchto needs barriers.

Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.

Pull up following revision(s) (requested by riastradh in ticket #1676):

	sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
	sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
	sys/arch/aarch64/aarch64/locore.S: revision 1.91
	sys/arch/mips/include/asm.h: revision 1.74
	sys/arch/hppa/include/cpu.h: revision 1.13
	sys/arch/arm/arm/armv6_start.S: revision 1.38
	sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
	sys/arch/mips/mips/locore.S: revision 1.229
	sys/arch/aarch64/aarch64/cpuswitch.S: revision 1.40
	sys/arch/alpha/include/asm.h: revision 1.45
	sys/arch/sparc64/sparc64/locore.s: revision 1.432
	sys/arch/vax/vax/subr.S: revision 1.42
	sys/arch/mips/mips/locore_mips3.S: revision 1.116
	sys/arch/ia64/ia64/machdep.c: revision 1.44
	sys/arch/arm/arm32/cpuswitch.S: revision 1.106
	sys/arch/sparc/sparc/locore.s: revision 1.284
	(all via patch)

aarch64: Add missing barriers in cpu_switchto.
Details in comments.

Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.

PR kern/57240

alpha: Add missing barriers in cpu_switchto.
Details in comments.

arm32: Add missing barriers in cpu_switchto.
Details in comments.

hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?

ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)

mips: Add missing barriers in cpu_switchto.
Details in comments.

powerpc: Add missing barriers in cpu_switchto.
Details in comments.

sparc: Add missing barriers in cpu_switchto.

sparc64: Add missing barriers in cpu_switchto.
Details in comments.

vax: Note where cpu_switchto needs barriers.

Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.

Pull up following revision(s) (requested by riastradh in ticket #264):

	sys/arch/ia64/ia64/vm_machdep.c: revision 1.18
	sys/arch/powerpc/powerpc/locore_subr.S: revision 1.67
	sys/arch/aarch64/aarch64/locore.S: revision 1.91
	sys/arch/mips/include/asm.h: revision 1.74
	sys/arch/hppa/include/cpu.h: revision 1.13
	sys/arch/arm/arm/armv6_start.S: revision 1.38
	sys/arch/evbmips/ingenic/cpu_startup.S: revision 1.2
	sys/arch/mips/mips/locore.S: revision 1.229
	sys/arch/aarch64/aarch64/cpuswitch.S: revision 1.40
	sys/arch/alpha/include/asm.h: revision 1.45
	sys/arch/sparc64/sparc64/locore.s: revision 1.432
	sys/arch/vax/vax/subr.S: revision 1.42
	sys/arch/mips/mips/locore_mips3.S: revision 1.116
	sys/arch/riscv/riscv/cpu_switch.S: revision 1.3
	sys/arch/ia64/ia64/machdep.c: revision 1.44
	sys/arch/arm/arm32/cpuswitch.S: revision 1.106
	sys/arch/sparc/sparc/locore.s: revision 1.284

aarch64: Add missing barriers in cpu_switchto.
Details in comments.

Note: This is a conservative change that inserts a barrier where
there was a comment saying none is needed, which is probably correct.
The goal of this change is to systematically add barriers to be
confident in correctness; subsequent changes may remove some bariers,
as an optimization, with an explanation of why each barrier is not
needed.

PR kern/57240

alpha: Add missing barriers in cpu_switchto.
Details in comments.

arm32: Add missing barriers in cpu_switchto.
Details in comments.

hppa: Add missing barriers in cpu_switchto.
Not sure hppa has ever had working MULTIPROCESSOR, so maybe no
pullups needed?

ia64: Add missing barriers in cpu_switchto.
(ia64 has never really worked, so no pullups needed, right?)

mips: Add missing barriers in cpu_switchto.
Details in comments.

powerpc: Add missing barriers in cpu_switchto.
Details in comments.

riscv: Add missing barriers in cpu_switchto.
Details in comments.

sparc: Add missing barriers in cpu_switchto.

sparc64: Add missing barriers in cpu_switchto.
Details in comments.

vax: Note where cpu_switchto needs barriers.

Not sure vax has ever had working MULTIPROCESSOR, though, and I'm not
even sure how to spell store-before-load barriers on VAX, so no
functional change for now.

powerpc: Optimization: Omit needless membar when triggering softint.

When we are triggering a softint, it can't already hold any mutexes.
So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is
always done with atomic r/m/w, and we need not issue any explicit
barrier between ci->ci_curlwp = softlwp and a potential load of
mtx->mtx_owner in mutex_exit.

PR kern/57240

XXX pullup-8
XXX pullup-9
XXX pullup-10

powerpc: Add missing barriers in cpu_switchto.

Details in comments.

PR kern/57240

XXX pullup-8
XXX pullup-9
XXX pullup-10

s/frmae/frame/

Sync with HEAD.

For ibm4xx and booke, restore saved PSL_EE bit as done for oea,
instead of forcibly enabling interrupts.

For booke and ibm4xx, switch to software-based single-stepping for PT_STEP
ptrace(2) command from broken hardware-based implementation.

As described in proposal on port-powerpc@,

http://mail-index.netbsd.org/port-powerpc/2021/02/26/msg003597.html

hardware debug facilities of booke and 4xx use critical interrupts, that
are difficult to handle for this purpose; they are not automatically masked
when entering kernel mode via system call trap or hardware interrupt.
See my proposal above for more details.

Now, hardware debug facilities are exclusively usable by kernel itself.
They are much more functional than PSL_SE MSR bit of oea, and should be
useful to, e.g., support byte-granular watchpoint for DDB in the future.

Drop unused opt_lockdebug.h.

Style and cosmetic changes. No binary changes intended.

Merge changes from current as of 20200406

Pull up following revision(s) (requested by rin in ticket #755):

	sys/arch/evbppc/conf/std.virtex: revision 1.4
	sys/arch/powerpc/powerpc/trap_subr.S: revision 1.81
	sys/arch/powerpc/ibm4xx/4xx_trap_subr.S: revision 1.8
	sys/arch/evbppc/conf/std.walnut: revision 1.9
	common/lib/libc/arch/powerpc/atomic/atomic_op_asm.h: revision 1.7
	sys/arch/powerpc/include/asm.h: revision 1.49
	common/lib/libc/arch/powerpc/atomic/atomic_cas.S: revision 1.9
	sys/arch/powerpc/ibm4xx/trap_subr.S: revision 1.28
	sys/arch/powerpc/include/lock.h: revision 1.15
	sys/arch/evbppc/conf/std.obs266: revision 1.3
	common/lib/libc/arch/powerpc/atomic/atomic_swap.S: revision 1.8
	sys/arch/powerpc/powerpc/locore_subr.S: revision 1.61
	sys/arch/powerpc/powerpc/lock_stubs.S: revision 1.12
	sys/arch/evbppc/conf/std.obs200: revision 1.5

Implement workaround for IBM405 Errata 77 (aka CPU_210), where
interrupted stwcx. may errantly write data to memory:

     https://elinux.org/images/1/1d/Ppc405gp-errata.pdf

This is because stwcx. is split into two pieces in the pipeline.

We need to
(1) insert dcbt before every stwcx. instruction, as well as
(2) insert sync before every rfi/rfci instruction.

It is unclear which processors are affected, but according to Linux,
all 405-based cores up until 405GPR and 405EP are affected:

     https://github.com/torvalds/linux/blob/master/arch/powerpc/platforms/40x/Kconfig#L140

For kernel, this workaround can be restricted to affected processors.

However, for kernel modules and userland, we have to enable it for all
32bit powerpc archs in order to share common binaries as before.
Proposed on port-powerpc:

     http://mail-index.netbsd.org/port-powerpc/2020/02/21/msg003583.html

Implement workaround for IBM405 Errata 77 (aka CPU_210), where
interrupted stwcx. may errantly write data to memory:

    https://elinux.org/images/1/1d/Ppc405gp-errata.pdf

This is because stwcx. is split into two pieces in the pipeline.

We need to
(1) insert dcbt before every stwcx. instruction, as well as
(2) insert sync before every rfi/rfci instruction.

It is unclear which processors are affected, but according to Linux,
all 405-based cores up until 405GPR and 405EP are affected:

    https://github.com/torvalds/linux/blob/master/arch/powerpc/platforms/40x/Kconfig#L140

For kernel, this workaround can be restricted to affected processors.
However, for kernel modules and userland, we have to enable it for all
32bit powerpc archs in order to share common binaries as before.

Proposed on port-powerpc:

    http://mail-index.netbsd.org/port-powerpc/2020/02/21/msg003583.html

Sync with head.

Pull up following revision(s) (requested by rin in ticket #737):

	sys/arch/powerpc/powerpc/trap.c: revision 1.157
	sys/arch/powerpc/powerpc/locore_subr.S: revision 1.60

Comment out do_ucas_32(), only user of which, _ucas_32(), is commented out
since powerpc/trap.c rev 1.156:
     http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/arch/powerpc/powerpc/trap.c#rev1.156

Comment out do_ucas_32(), only user of which, _ucas_32(), is commented out
since powerpc/trap.c rev 1.156:

    http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/arch/powerpc/powerpc/trap.c#rev1.156

Sync with head.

oldlwp is always non-NULL in cpu_switchto so remove the test for NULL.

Hopefully fix some problems seen with MP support on non-x86, in particular
where curcpu() is defined as curlwp->l_cpu:

- mi_switch(): undo the ~2007ish optimisation to unlock curlwp before
  calling cpu_switchto().  It's not safe to let other actors mess with the
  LWP (in particular l->l_cpu) while it's still context switching.  This
  removes l->l_ctxswtch.

- Move the LP_RUNNING flag into l->l_flag and rename to LW_RUNNING since
  it's now covered by the LWP's lock.

- Ditch lwp_exit_switchaway() and just call mi_switch() instead.  Everything
  is in cache anyway so it wasn't buying much by trying to avoid saving old
  state.  This means cpu_switchto() will never be called with prevlwp ==
  NULL.

- Remove some KERNEL_LOCK handling which hasn't been needed for years.

Sync with HEAD

Overhaul the API used to fetch and store individual memory cells in
userspace.  The old fetch(9) and store(9) APIs (fubyte(), fuword(),
subyte(), suword(), etc.) are retired and replaced with new ufetch(9)
and ustore(9) APIs that can return proper error codes, etc. and are
implemented consistently across all platforms.  The interrupt-safe
variants are no longer supported (and several of the existing attempts
at fuswintr(), etc. were buggy and not actually interrupt-safe).

Also augmement the ucas(9) API, making it consistently available on
all plaforms, supporting uniprocessor and multiprocessor systems, even
those that do not have CAS or LL/SC primitives.

Welcome to NetBSD 8.99.37.

Sync with HEAD

when spinning up secondary CPUs, put them in bridge mode if the primary cpu is

update from HEAD

Sync with HEAD

Sync with HEAD

Pull up following revision(s) (requested by phx in ticket #1382):
	sys/arch/powerpc/powerpc/locore_subr.S: revision 1.55
in cpu_switchto() and the fast-softint context switch code,
put back the stwcx. instruction to clear the reservation.
we used to have this in the old cpu_switch() until it was
if-0'd in 2003 and removed completely in 2007.
this fixes hangs I've seen where a softint thread is
blocked waiting for a mutex that is not held.
this should also fix PR 44387.

Sync with HEAD

in cpu_switchto() and the fast-softint context switch code,
put back the stwcx. instruction to clear the reservation.
we used to have this in the old cpu_switch() until it was
if-0'd in 2003 and removed completely in 2007.
this fixes hangs I've seen where a softint thread is
blocked waiting for a mutex that is not held.
this should also fix PR 44387.

Rebase to HEAD as of a few days ago.

Rebase.

Fix diagnostic trap to be correct.  PSL_EE@l would be sign-extended and this
could never match the result of the andi. before it.

Correct last, ha+l uses lis+addi, so use h+l.

Build 32bit constant with lis+ori, not lis+addi. The instructions
differ on the sign extension handling of the immediate.

Official PPC ISA documentation has no SP register, so use R1 directly.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Simplify since we know curlwp is in %r13

sync with head

Add diagnostic code emptyidlespin verifying that the current IPL
is IPL_NONE and EE is set in the MSR.

sync with head

sync to -current.

Remove COMPAT_SA / KERN_SA.  Welcome to 6.99.3!
Approved by core@.

merge to -current.

Remove white-spaces.

Catchup with rmind-uvmplock merge.

remove a #if 0 block

If this is a MODULAR kernel, export USRSTACK and CPU_MAXNUM as linker symbols
so modules can access them.

Call splraise(IPL_HIGH) instead splhigh.  Easier to a nasty problem.

USPRG0 is only on BOOKE

sync with head

Sync with HEAD.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

sync with head

Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

Add fast softint support.
Add booke support.

Sync with HEAD.

sync with head.

implement ucas_* for powerpc/oea.

sync to netbsd-5

sync with head

Rename L_ADDR to L_PCB and amend some comments accordingly.

sync with head

Pull up following revision(s) (requested by martin in ticket #801):
	sys/arch/powerpc/powerpc/locore_subr.S: revision 1.38
	sys/arch/powerpc/powerpc/vm_machdep.c: revision 1.77
Do not use the same trampoline for cpu_setfunc and cpu_lwp_fork, the
latter does a lot more work.

Pull up following revision(s) (requested by martin in ticket #801):
	sys/arch/powerpc/powerpc/locore_subr.S: revision 1.38
	sys/arch/powerpc/powerpc/vm_machdep.c: revision 1.77
Do not use the same trampoline for cpu_setfunc and cpu_lwp_fork, the
latter does a lot more work.

Do not use the same trampoline for cpu_setfunc and cpu_lwp_fork, the
latter does a lot more work.

Sync with HEAD.

On MP systems, make sure to update l->l_cpu with the cpu_info of the current
processor (in case it was running on a different processor before).

SMP support for ofppc.  (finally)  Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc.  Tested with a
quad-proc 7044-270.
Summary of changes:

Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR.  Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000.  Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu().  Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.

sync with HEAD

sync with head.

Sync with HEAD.

Some powerpc cleanup.  Remove unneeded/bad usage of extern oeacpufeat.
Convert asm code to use %r register format.  Done by comparison to
disassembled output, double checked with diff of dissasembled output
before and after, and test booted on my 7044.

sync with head.

Rewrite a big chunk of the pmap and locore code for powerpc to better
deal with the 64bit bridge mode.  pmap changes by Matt Thomas, rest by myself.

Change pmap.c to work similar to exec_elf.c to allow us to compile in
multiple pmaps to a single kernel.  This allows the pmap for bridge64 to
co-exist with the 32bit pmap.

Yank __HAVE_PMAP_PHYSSEG from all the oea code.

Add a new global, "oeacpufeat", which is used early in locore to determine
certain cpu features.  This allows us to conditionalize code early in the boot
for certain CPUs that have special needs.

Yank most of the ifdef PPC_OEA_BRIDGE64 code from almost every file it was
found in.  Some of it seemed incorrect, and my 7044 booted just fine
without it.  It would appear that the bridge cpus treat BAT instructions
as nops, so they seem to be safe.

In ofppc, check the oeacpufeat, and if we are on a 64bit proc, clear
MSR[SF], and ASR[V].

With all of these changes, a kernel with both PPC_OEA and PPC_OEA_BRIDGE64
will boot on the POWERIII-2 cpu.  However, it will not yet boot on a 32bit
cpu, because of CACHELINESIZE.  Work remains to be done there to fix that.

sync with HEAD

sync with head.

Sync with HEAD.

Follow the merge of pmap.c on i386 and amd64 and move
pmap_init_tmp_pgtbl into arch/x86/x86/pmap.c. Modify the ACPI wakeup
code to restore CR4 before jumping back into kernel space as the large
page option might cover that.

Sync with HEAD.

Sync with head.

sync with head.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Move a bunch of the macppc SMP code out of macppc, and down into the
generic OEA code.  Add a set of md callbacks into these shared routines,
that any oeappc SMP machine needs to provide.  This allows for generally
shared SMP startup code, but still allows for machine-specific
differences in the setup and kicking of the new CPU.

Convert macppc to this new layout.  Tested by Macallan.

Add an initial attempt at SMP to prep.  Tested on UP machine only,
untested on SMP yet.

Sync with HEAD

sync with head.

Sync with HEAD.

Sync with HEAD.

Sync with HEAD.

sync with HEAD

Don't call proc_trampoline_mp when starting a lwp.  (XXX why did we do this
before?)

Sync with head.

Sync with head.

Update to HEAD.

merge yamt-idlelwp branch.  asked by core@.  some ports still needs work.

from doc/BRANCHES:

	idle lwp, and some changes depending on it.

	1. separate context switching and thread scheduling.
	   (cf. gmcgarry_ctxsw)
	2. implement idle lwp.
	3. clean up related MD/MI interfaces.
	4. make scheduler(s) modular.

More cleanup:
1) Remove lcsplx, strayintr, and foosoft from all the converted ports.
None of this stuff is needed anymore.
2) because lcsplx is just "return spllower", just call spllower from
locore_subr.S instead.
3) Every port (except macppc) had a pretty similar cpu_configure(), so
take the common parts out and make a genppc_cpu_configure() in an attempt
to stop using imask[] outside of intr.c

Save curlwp in cpu_switchto

Adapt powerpc to yamt-idlelwp.  Nuke cpu_setfunc.
Don't define _HAVE_BITENDIAN_BITOPS.  Misc cleanups.

sync with head.

Merge newlock2 to head.

For now always call sched_unlock_idle/sched_lock_idle. They will be
removed by yamt's cpu_switchto() changes.

powerpc changes.

sync with head.

sync with head

sync with head

1st cut of Powermac G5 support (uses bridge mode).

merge ktrace-lwp.

sync with -current

Sync with HEAD.

Split the hw-dependent powermanglement into its own function and make
Idle call that.  Add a ci_idlespin function pointer to cpu_info.
Update INIT_CPUINFO to initialize it to a naked 'blr' instruction.
In oea/cpu_subr.c, add cpu_idlespin and make ci_idlespin point to it.

Sync with HEAD.

Make sure to enable interrupts before lower IPL so we don't block any
interrupts (IPI) we shouldn't.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

Add some comments, clean things up so routines can be called from the
idle loop.

Restore ci_curpm since it re-enables 603 to working state.

Remove worthless load.
Save curcpu before doing uniprocessor dispatch.

Don't zero curlwp/curpcb in cpu_switchto.
Use correct register in the store conditional.
Add DIAGNOSTIC check for null curpcb on cpu_switch exit.

Add siginfo support for PowerPC.

Move SFRAMELEN to frame.h and use it in vm_machdep.c.  In setfunc, setup
callframe linkages correctly.  Restore use of ldptr to locore_subr.S
[pthreads and gdb no longer crash/hang the system]

Switch back to adjusting stack by addi instead of ldptr until I can locate
who's setting up the stack wrong.

Cleanup/rework cpu_switch*, switch_exit, Idle routine.  Remove pcb_psl
since it was write-only.  When setting up a process, make sure the fake
callframes are properly linked together.

Only lower SPL when in Idle loop.  Raise spl to previous level (which would
be IPL_SCHED) when exiting Idle loop.  Never lower SPL anyplace else.

Nuke ci_curpm and curpm.  Nuke pcb_pmreal.  Those were use for spill stacks
and those no longer exist.  for few uses that need CURPM, use CURPCB/PCB_PM

When getting the lwp to switch to, test to see if the scheduling queue is
empty, and if so panic.  Change references to "proc/process" to lwp.

Eliminate stmw/lmw substituting the individual load/store instructions.
Use more symbolic constants.  These are now safe for use on PPC64.

Switch to regiser prefixes.  Also change numeric constants to symbolic ones.

Make sure to include opt_foo.h if a defflag option FOO is used.

Same code exists in both halves in #ifdef/#else/#endif.  move it outside.

Add support for the IBM 403GCX cpu. Enabled with "options PPC_IBM403".

  - different set of device control registers.
  - non-standard access to the time base.
  - 16 byte cache lines.

Approved by: Eduardo Horvath <eeh@netbsd.org>

witch from xor r,r,r to li r,0 to set a register to 0.  It's clearer (and
better for G4 processors).

Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).

Perform a rototill of the powerpc code.  Mandate use of SPRG0 to store
a pointer to current cpu's cpu_info structure.  Use cpu_info for
intstk,intr_depth,still_stk,idle_pcb,curpcb,curlwp,etal even on
non-MULTIPROCESSOR machines.  Add common macros GET_CPUINFO and
INIT_CPUINFO to get and initialize the cpu_info struct on startup.  Make
ibm4xx use the standard <powerpc/frame.h>.  Use IFRAME_xx in ibm4xx
trap_subr.S instead of explicit magic offsets.  Move INTSTK and SPILLSTK
to std.<platform>.  Change faultbuf to a struct instead of an array.

On MPC6XX cpus, stop using the vector page for temporary space and use
reserved space in cpu_info.

Merge the nathanw_sa branch.

* Merge switch_exit() and switch_lwp_exit().
* Keep the stack 16-byte aligned; adjust by USPACE-16, not USPACE-20.

Rename cpu_preempt() to cpu_switchto(), and make the caller remove the
new process from its run queue before calling cpu_switchto().

While here, make a few cpu_switch() and cpu_switchto() implementations
get the outgoing LWP from the args, rather than looking at the curlwp
variable.

Add IBM 4xx case to cpu_preempt().

Sync with HEAD.

Merge the IBM 4xx into the common powerpc/locore_subr.S, and
eliminate all the duplicated context switch related code in
the IBM 4xx port.

sync kqueue branch with HEAD

catch up with -current.

Catch up to -current.

propagate the MP idle-loop fix to ppc from the other ports:

  Move call to sched_unlock_idle to later in the context switch to
  eliminate a race where another processor could grab the outgoing
  process before we were done saving our state into it, with predictable
  results.

  Bug spotted by Frank van der Linden <fvdl@wasabisystems.com>

also, don't re-enable interrupts temporarily in the middle of
switching to a new process, just wait until we're completely switched.
this didn't work on MP and it's not worth the effort.

catch up with -current.

Add machdep.powerpc sysctl.  Change the default value of powersave to -1
(< 0 mean no powersave available).  Enable powersave by default for
750/7400/7410 but leave if off for 7450/7455.

catch up with -current.

Curproc->curlwp renaming.

Change uses of "curproc->l_proc" back to "curproc", which is more like the
original use. Bare uses of "curproc" are now "curlwp".

"curproc" is now #defined in proc.h as ((curlwp) ? (curlwp)->l_proc) : NULL)
so that it is always safe to reference curproc (*de*referencing curproc
is another story, but that's always been true).

Pull up revision 1.3 (requested by matt in ticket #334):
Don't load the SR registers on a context switch.  They get switched from
the user's SR registers to the kernel's SR registers on an exception or
interrupt from user level and restored with the user's SR register when the
exception or interrupt returns back to user level.

Don't load the SR registers on a context switch.  They get switched from
the user's SR registers to the kernel's SR registers on an exception or
interrupt from user level and restored with the user's SR register when the
exception or interrupt returns back to user level.

Update sched_whichqs properly in cpu_preempt().
Ensure cpu_preempt() stack hack keeps stack pointer 16-byte aligned.
Reduce code duplication by jumping from cpu_preempt() into cpu_switch()
	to do post-new-lwp-selection work (thanks for the idea, thorpej).

Improve upcall to better work with libpthread.

Ensure cpu_preempt and cpu_switch both use the same amount of stack.
Go ahead and fill lwp->l_cpu with &cpu_info_store on !MULTIPROCESSOR.

Initial SA support for ppc.  Test-booted on sandpoint, macppc, & walnut.
mcontext and cpu_getmcontext()/cpu_setmcontext() from Klaus Klein
<kleink@netbsd.org>.

Sync with HEAD.

file locore_subr.S was added on branch thorpej_scsipi on 2001-03-12 13:29:14 +0000

Fix a bug in cpu_switch().
Reported by Tad Hunt <tad@entrisphere.com> on port-powerpc.

Get the ofppc/prep/macppc/sandpoint/bebox to share the process switch
/ setfault / fork_trampoline code.