CVS log for src/sys/arch/powerpc/pic/intr.c

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powerpc: Sprinkle "memory" clobbers on eieio and nearby asm blocks.

Otherwise the compiler may reorder these around loads and stores,
which mostly defeats the purpose.  `asm volatile' just ensures the
instruction isn't _deleted_; it may still move around.

Sync with HEAD.

Sync with HEAD.

KNF

Brush up previous, or make things more similar to x86:

- Prevent pic_name from appearing vmstat(1) twice.
- Restore "irq" in interrupt id fields of intrctl(8).

For these purposes,

- Add is_evname member to struct intr_source.
- Bump size of is_source to INTRIDBUF, and rename it to is_intrid for clarity.

Now, outputs from vmstat(1) and intrctl(8) are like:

----
$ vmstat -ev
...
openpic irq 39                                 3967   26 intr
...
$ intrctl list
interrupt id   CPU0  device name(s)
...
openpic irq 39 3967* wdc1
...
----

Include PIC name to interrupt source, instead of just "irq", so that
it appears in "interrupt id" field of intrctl(8).

Should be useful when multiple PICs are simultaneously available as in
405EX (where uic[12] are cascaded to uic0).

Turn imask into static.

XXX
Other macro etc. in powerpc/intr.h should also be moved into
powerpc/pic/intr.c, or protected by __INTR_PRIVATE.

Include missing opt_ppcarch.h.

Style and cosmetic changes. No binary changes intended.

Merge changes from current as of 20200406

Sync with head.

Pull up following revision(s) (requested by rin in ticket #730):

	sys/arch/powerpc/conf/files.powerpc: revision 1.93
	sys/arch/powerpc/include/pio.h: revision 1.8
	sys/arch/powerpc/pic/intr.c: revision 1.27
	sys/arch/powerpc/powerpc/bus_dma.c: revision 1.50
	sys/arch/powerpc/powerpc/pio_subr.S: revision 1.17

Add PPC_IBM440 flag as 440 is significantly different from 40x processors.
(It may be more easily supported by booke than by ibm4xx.)

 -

eieio is implemented as sync on 40x. Therefore, "sync; eieio" and
"eieio; sync" can be replaced by a single sync.

eieio is implemented as sync on 40x. Therefore, "sync; eieio" and
"eieio; sync" can be replaced by a single sync.

Sync with HEAD

Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)

Rename min/max -> uimin/uimax for better honesty.

These functions are defined on unsigned int.  The generic name
min/max should not silently truncate to 32 bits on 64-bit systems.
This is purely a name change -- no functional change intended.

HOWEVER!  Some subsystems have

	#define min(a, b)	((a) < (b) ? (a) : (b))
	#define max(a, b)	((a) > (b) ? (a) : (b))

even though our standard name for that is MIN/MAX.  Although these
may invite multiple evaluation bugs, these do _not_ cause integer
truncation.

To avoid `fixing' these cases, I first changed the name in libkern,
and then compile-tested every file where min/max occurred in order to
confirm that it failed -- and thus confirm that nothing shadowed
min/max -- before changing it.

I have left a handful of bootloaders that are too annoying to
compile-test, and some dead code:

cobalt ews4800mips hp300 hppa ia64 luna68k vax
acorn32/if_ie.c (not included in any kernels)
macppc/if_gm.c (superseded by gem(4))

It should be easy to fix the fallout once identified -- this way of
doing things fails safe, and the goal here, after all, is to _avoid_
silent integer truncations, not introduce them.

Maybe one day we can reintroduce min/max as type-generic things that
never silently truncate.  But we should avoid doing that for a while,
so that existing code has a chance to be detected by the compiler for
conversion to uimin/uimax without changing the semantics until we can
properly audit it all.  (Who knows, maybe in some cases integer
truncation is actually intended!)

update from HEAD

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Added MSI/MSI-X and interrupt_distribute(9) support for powerpc.

Sync with HEAD

treat IPIs like regular interrupts at IPL_HIGH
should fix port-powerpc/44387
tested by chuq

sync with netbsd-6-0-RELEASE.

sync with head

Pull up following revision(s) (requested by macallan in ticket #535):
	sys/arch/powerpc/pic/intr.c: revision 1.23
when calculating per-IPL virq masks, take into account that shared =20
IRQs may
request different IPLs
fixes vr(4)-related problems seen on ofppc

when calculating per-IPL virq masks, take into account that shared IRQs may
request different IPLs
fixes vr(4)-related problems seen on ofppc

Pull up following revision(s) (requested by macallan in ticket #320):
	sys/arch/powerpc/pic/intr.c: revision 1.21
	sys/arch/powerpc/pic/intr.c: revision 1.22
look at the right cpu_softints bits in pic_do_pending_int()
so we call the right softint handlers
fix same thinko as in previous commit, in have_pending_intr_p()

fix same thinko as in previous commit, in have_pending_intr_p()

look at the right cpu_softints bits in pic_do_pending_int()
so we call the right softint handlers

sync with head

merge to -current.

Use kmem instead of malloc.  Remove unneeded <sys/malloc.h> includes.

Some PICs have the capability to define the interrupt's polarity (OpenPIC
for example). So the accepted interrupt types have been extended to:
- IST_EDGE_FALLING (which is the same as IST_EDGE)
- IST_EDGE_RISING (new)
- IST_LEVEL_LOW (is the same as IST_LEVEL)
- IST_LEVEL_HIGH (new)
Old code will continue to work without modification.

Modify *ASSERTMSG() so they are now used as variadic macros. The main goal
is to provide routines that do as KASSERT(9) says: append a message
to the panic format string when the assertion triggers, with optional
arguments.

Fix call sites to reflect the new definition.

Discussed on tech-kern@. See
http://mail-index.netbsd.org/tech-kern/2011/09/07/msg011427.html

Catchup with rmind-uvmplock merge.

Make it compile when PIC_DEBUG is defined.

Cleanup includes.  Explicitly include <powerpc/psl.h>

intr.h must not include cpu due to deadly embrace with SOFTINT_COUNT.
Cleanup intr.h so MD definitions can overload common definitions.
Rototill pic/intr.c.  Virtual IRQs can now be reclaimed.  separate virq
from hwirq from picirq.  Redo intr mask calculations.
tested on pmppc and macppc (MP).

Change from level to ipl since we aren't dealing a mask anymore, just a
simple value.
Fix intr_calculatemasks to deal with ipl isn't a mask.  Let establish
and disestablish determine the highest ipl for the interrut source being
modified.  No reason to recompute that for every source when only one changes
at a time.  Only change idepth while in the loop.

Make sure OEA ports without __HAVE_FAST_SOFTINTS still compile.

enable FAST_SOFTINTR support for all ports that use powerpc/pic/
This has been successfully tested on macppc
TODO:
- ibm4xx needs to be adapted
- SMP doesn't work yet, 2nd CPU crashes when trying to leave the idle loop

sync with head

Sync with HEAD.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

sync with head

Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits.  Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

Sync with HEAD.

sync with head.

sync with head

make this work again

Sync with HEAD.

Support 64-bit imask for powerpc/pic.

Remove white-spaces.

Sync with HEAD.

sync with head.

sync with head.

Convert to new 2 clause license

SMP support for ofppc.  (finally)  Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc.  Tested with a
quad-proc 7044-270.
Summary of changes:

Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR.  Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000.  Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu().  Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.

sync with head

sync with HEAD

Sync with HEAD.

Sync with head.

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sync with head.

Fix the endless stream of 7's problem on i8259-like interrupt controllers
once and for all.  The i8259 does not like to be read in a loop, when an
interrupt comes in, it will return a valid value, however, if you keep
reading it until there are no outstanding interrupts, it will return 7
(which is the lpt interrupt).  Change the pic handler to give an argument
to the get_irq functions of mode, which indicates if this is the first
time we are asking, or if we are just rechecking in a loop.  Non-i8259
handlers can safely ignore this argument.

Tested to fix the stream of 7's problem on prep and ofppc.  Got rid of
the nasty hack in ofppc with this too, and the prep machine seems to take
less interrupts now, which is a good thing.

Sync with HEAD.

Sync with HEAD.

sync with head

Sync with HEAD.

Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

sync with HEAD

More diff reduce to HEAD due to botched up merging.

sync with head.

Sync with head.

sync with head.

file intr.c was added on branch matt-armv6 on 2007-11-06 23:20:53 +0000

file intr.c was added on branch yamt-lazymbuf on 2007-10-27 11:27:59 +0000

file intr.c was added on branch vmlocking on 2007-10-23 20:36:17 +0000

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

remove code that would restrict IRQs and softintrs to cpu0

don't declare ipiops again

New ppcoea-MI IPI infrastructure.  This is similar to the PIC
infrastructure, but simplified greatly.

Also, convert macppc (the only port currently using IPI's) over to this new
infrastructure.  Still some minor work left to do here.

fix pasto - now we actually run IPIs on cpu0 again

calculate interrupt maks after establishing the handler - otherwise the
last established IRQ handler would never be unblocked

Change the biomask printf to aprint_normal.

More cleanup:
1) Remove lcsplx, strayintr, and foosoft from all the converted ports.
None of this stuff is needed anymore.
2) because lcsplx is just "return spllower", just call spllower from
locore_subr.S instead.
3) Every port (except macppc) had a pretty similar cpu_configure(), so
take the common parts out and make a genppc_cpu_configure() in an attempt
to stop using imask[] outside of intr.c

Simplify intr_typename

nuke #if(n)def __HAVE_GENERIC_SOFT_INTERRUPTS

Rewrite how shared isa is done slightly.  This will allow the individual
ports to override the shared functions if needed.  Also, implement
isa_intr_alloc, which needed to be done inside pic/intr.c because it
needs access to structs which are static to the file.

follow up to the previous change for struct pic_ops, and make
pic_i8259.c compilable.

adapt to picvar changes, call pic_establish_irq() with max priority in use on
the resp. IRQ

Add splraise, splx, spllower and softintr here.

Move the functions down from openpic.c into pic_openpic.c, as there
really is no need to have them over there when all the interrupt routines
will be using pic_openpic.c
Change the openpic setup to set all the irqs except 0 to negative polarity.
Set the spurious vector reg to 0xff.
Emit a nice printf showing the version of the openpic, and getrid of the
maxint thing.
Add a global, primary_pic, so machines can elect any registered pic as
the primary interrupt controller.
Clean up a few nits in pic_prepivr to make it more similar to the openpic
one, add a prototype for the setup_prepivr function, etc etc.

These two have no <machine/autoconf.h> dependency.

add dummy establish_intr method

Fix typo in pic_ack_irq

Add some additional functions (pic_establish_irq) to enable use with an 8259

remove pic_reenable_irq() from pic_handle_intr()

fix some compiler warnings

cosmetics:
- remove CPU number from pic_get_irq()
- add type parameter to enable/reenable
- add IRQ parameter to pic_ack_irq()
... and make intr.c compile again

first try on a generic interrupt handler.
Features:
- PIC details are hidden by struct pic_ops
- PICs can easily be cascaded
- support for soft interrupts
tested so far only on macppc with a PowerBook 3400c

file intr.c was initially added on branch ppcoea-renovation.