Annotation of src/sys/arch/powerpc/include/cpu.h, Revision 1.21
1.21 ! matt 1: /* $NetBSD: cpu.h,v 1.20 2002/08/14 15:41:57 matt Exp $ */
1.1 ws 2:
3: /*
1.5 ws 4: * Copyright (C) 1999 Wolfgang Solfrank.
5: * Copyright (C) 1999 TooLs GmbH.
1.9 matt 6: * Copyright (C) 1995-1997 Wolfgang Solfrank.
7: * Copyright (C) 1995-1997 TooLs GmbH.
1.1 ws 8: * All rights reserved.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. All advertising materials mentioning features or use of this software
19: * must display the following acknowledgement:
20: * This product includes software developed by TooLs GmbH.
21: * 4. The name of TooLs GmbH may not be used to endorse or promote products
22: * derived from this software without specific prior written permission.
23: *
24: * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
25: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27: * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28: * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
29: * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
30: * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31: * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32: * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33: * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34: */
1.5 ws 35: #ifndef _POWERPC_CPU_H_
36: #define _POWERPC_CPU_H_
1.1 ws 37:
1.9 matt 38: #if defined(_KERNEL_OPT)
39: #include "opt_lockdebug.h"
40: #include "opt_multiprocessor.h"
1.16 matt 41: #include "opt_ppcarch.h"
1.9 matt 42: #endif
43:
44: #include <machine/frame.h>
45: #include <machine/psl.h>
46: #include <machine/intr.h>
1.20 matt 47: #include <sys/device.h>
1.9 matt 48:
1.14 eeh 49:
50: struct cache_info {
51: int dcache_size;
52: int dcache_line_size;
53: int icache_size;
54: int icache_line_size;
55: };
56:
57:
1.9 matt 58: #ifdef _KERNEL
59: #include <sys/sched.h>
1.13 nathanw 60: #include <dev/sysmon/sysmonvar.h>
1.14 eeh 61:
1.9 matt 62: struct cpu_info {
63: struct schedstate_percpu ci_schedstate; /* scheduler state */
64: #if defined(DIAGNOSTIC) || defined(LOCKDEBUG)
65: u_long ci_spin_locks; /* # of spin locks held */
66: u_long ci_simple_locks; /* # of simple locks held */
67: #endif
68: struct device *ci_dev; /* device of corresponding cpu */
69: struct proc *ci_curproc; /* current owner of the processor */
70:
71: struct pcb *ci_curpcb;
72: struct pmap *ci_curpm;
73: struct proc *ci_fpuproc;
1.16 matt 74: struct proc *ci_vecproc;
1.9 matt 75: struct pcb *ci_idle_pcb; /* PA of our idle pcb */
76: int ci_cpuid;
77:
78: int ci_astpending;
79: int ci_want_resched;
80: u_long ci_lasttb;
81: int ci_tickspending;
82: int ci_cpl;
83: int ci_ipending;
84: int ci_intrdepth;
85: char *ci_intstk;
86: char *ci_spillstk;
87: int ci_tempsave[8];
88: int ci_ddbsave[8];
89: int ci_ipkdbsave[8];
90: int ci_disisave[4];
1.14 eeh 91: struct cache_info ci_ci;
1.12 nathanw 92: struct sysmon_envsys ci_sysmon;
93: struct envsys_tre_data ci_tau_info;
1.9 matt 94: struct evcnt ci_ev_traps; /* calls to trap() */
95: struct evcnt ci_ev_kdsi; /* kernel DSI traps */
96: struct evcnt ci_ev_udsi; /* user DSI traps */
97: struct evcnt ci_ev_udsi_fatal; /* user DSI trap failures */
98: struct evcnt ci_ev_isi; /* user ISI traps */
99: struct evcnt ci_ev_isi_fatal; /* user ISI trap failures */
100: struct evcnt ci_ev_pgm; /* user PGM traps */
101: struct evcnt ci_ev_fpu; /* FPU traps */
102: struct evcnt ci_ev_fpusw; /* FPU context switch */
103: struct evcnt ci_ev_ali; /* Alignment traps */
104: struct evcnt ci_ev_ali_fatal; /* Alignment fatal trap */
105: struct evcnt ci_ev_scalls; /* system call traps */
106: struct evcnt ci_ev_vec; /* Altivec traps */
107: struct evcnt ci_ev_vecsw; /* Altivec context switches */
1.16 matt 108: struct evcnt ci_ev_umchk; /* user MCHK events */
1.9 matt 109: };
110:
111: #ifdef MULTIPROCESSOR
112: static __inline int
1.11 chs 113: cpu_number(void)
1.9 matt 114: {
115: int pir;
116:
117: asm ("mfspr %0,1023" : "=r"(pir));
118: return pir;
119: }
120:
121: static __inline struct cpu_info *
1.11 chs 122: curcpu(void)
1.9 matt 123: {
124: struct cpu_info *ci;
125:
126: asm volatile ("mfsprg %0,0" : "=r"(ci));
127: return ci;
128: }
1.11 chs 129:
130: void cpu_boot_secondary_processors(void);
1.9 matt 131:
132: extern struct cpu_info cpu_info[];
133:
134: #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0)
135: #define curproc curcpu()->ci_curproc
136: #define curpcb curcpu()->ci_curpcb
137: #define curpm curcpu()->ci_curpm
138: #define want_resched curcpu()->ci_want_resched
139: #define astpending curcpu()->ci_astpending
140: #define intr_depth curcpu()->ci_intrdepth
141:
1.18 chs 142: #define CPU_INFO_ITERATOR int
143: #define CPU_INFO_FOREACH(cii, ci) \
144: cii = 0, ci = &cpu_info[0]; cii < CPU_MAXNUM; cii++, ci++
145:
1.9 matt 146: #else
147: extern struct cpu_info cpu_info_store;
148: extern volatile int want_resched;
149: extern volatile int astpending;
150: extern volatile int intr_depth;
151:
152: #define curcpu() (&cpu_info_store)
153: #define cpu_number() 0
154:
1.18 chs 155: #define CPU_INFO_ITERATOR int
156: #define CPU_INFO_FOREACH(cii, ci) \
157: cii = 0, ci = curcpu(); ci != NULL; ci = NULL
158:
1.9 matt 159: #endif /* MULTIPROCESSOR */
160:
1.20 matt 161: static __inline register_t
1.18 chs 162: mfmsr(void)
163: {
1.20 matt 164: register_t msr;
1.18 chs 165:
166: asm volatile ("mfmsr %0" : "=r"(msr));
167: return msr;
168: }
169:
170: static __inline void
1.20 matt 171: mtmsr(register_t msr)
1.18 chs 172: {
173:
174: asm volatile ("mtmsr %0" : : "r"(msr));
1.19 chs 175: }
176:
177: static __inline uint32_t
178: mftbl(void)
179: {
180: uint32_t tbl;
181:
182: asm volatile ("mftbl %0" : "=r"(tbl));
183: return tbl;
184: }
185:
186: static __inline uint64_t
187: mftb(void)
188: {
189: uint64_t tb;
190: int tmp;
191:
192: asm volatile ("
193: 1: mftbu %0 \n\
194: mftb %0+1 \n\
195: mftbu %1 \n\
196: cmplw %0,%1 \n\
197: bne- 1b"
1.21 ! matt 198: : "=r"(tb), "=r"(tmp) :: "cr0");
1.19 chs 199: return tb;
200: }
201:
202: static __inline uint32_t
203: mfpvr(void)
204: {
205: uint32_t pvr;
206:
207: asm volatile ("mfpvr %0" : "=r"(pvr));
208: return (pvr);
1.18 chs 209: }
210:
1.9 matt 211: #define CLKF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0)
212: #define CLKF_BASEPRI(frame) ((frame)->pri == 0)
213: #define CLKF_PC(frame) ((frame)->srr0)
214: #define CLKF_INTR(frame) ((frame)->depth > 0)
215:
216: #define PROC_PC(p) (trapframe(p)->srr0)
217:
218: #define cpu_swapout(p)
219: #define cpu_wait(p)
220:
221: extern int powersave;
222: extern int cpu_timebase;
223: extern int cpu_printfataltraps;
1.16 matt 224: extern char cpu_model[];
225:
226: struct cpu_info *cpu_attach_common(struct device *, int);
1.18 chs 227: void cpu_setup(struct device *, struct cpu_info *);
1.16 matt 228: void cpu_identify(char *, size_t);
229: void delay (unsigned int);
230: void cpu_probe_cache(void);
231: void dcache_flush_page(vaddr_t);
232: void icache_flush_page(vaddr_t);
233: void dcache_flush(vaddr_t, vsize_t);
234: void icache_flush(vaddr_t, vsize_t);
1.9 matt 235:
236: #define DELAY(n) delay(n)
237:
238: #define need_resched(ci) (want_resched = 1, astpending = 1)
239: #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, astpending = 1)
240: #define signotify(p) (astpending = 1)
241:
1.16 matt 242: #ifdef PPC_MPC6XX
243: void mpc6xx_init(void (*)(void));
244: void mpc6xx_startup(const char *);
245: void mpc6xx_dumpsys(void);
246: void mpc6xx_install_extint(void (*)(void));
247: void *mapiodev(paddr_t, psize_t);
248: paddr_t kvtop(caddr_t);
249: void softnet(int);
250:
251: extern paddr_t msgbuf_paddr;
252: extern int cpu_altivec;
253: #endif
254:
1.9 matt 255: #endif /* _KERNEL */
256:
257: #if defined(_KERNEL) || defined(_STANDALONE)
258: #if !defined(CACHELINESIZE)
259: #define CACHELINESIZE 32
260: #endif
1.10 matt 261: #endif
262:
1.15 matt 263: void __syncicache(void *, size_t);
1.14 eeh 264:
1.5 ws 265: /*
266: * CTL_MACHDEP definitions.
267: */
1.9 matt 268: #define CPU_CACHELINE 1
269: #define CPU_TIMEBASE 2
270: #define CPU_CPUTEMP 3
271: #define CPU_PRINTFATALTRAPS 4
1.14 eeh 272: #define CPU_CACHEINFO 5
1.16 matt 273: #define CPU_ALTIVEC 6
274: #define CPU_MODEL 7
1.17 matt 275: #define CPU_POWERSAVE 8
276: #define CPU_MAXID 9
1.1 ws 277:
1.5 ws 278: #define CTL_MACHDEP_NAMES { \
279: { 0, 0 }, \
280: { "cachelinesize", CTLTYPE_INT }, \
1.7 matt 281: { "timebase", CTLTYPE_INT }, \
282: { "cputempature", CTLTYPE_INT }, \
1.9 matt 283: { "printfataltraps", CTLTYPE_INT }, \
1.14 eeh 284: { "cacheinfo", CTLTYPE_STRUCT }, \
1.16 matt 285: { "altivec", CTLTYPE_INT }, \
286: { "model", CTLTYPE_STRING }, \
1.17 matt 287: { "powersave", CTLTYPE_INT }, \
1.1 ws 288: }
289:
1.5 ws 290: #endif /* _POWERPC_CPU_H_ */
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