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Default branch: MAIN
Current tag: MAIN
Revision 1.5 / (download) - annotate - [select for diffs], Tue Jul 17 01:36:13 2012 UTC (10 months ago) by matt
Branch: MAIN
CVS Tags: yamt-pagecache-base8,
yamt-pagecache-base7,
yamt-pagecache-base6,
tls-maxphys-nbase,
tls-maxphys-base,
tls-maxphys,
khorben-n900,
agc-symver-base,
agc-symver,
HEAD
Changes since 1.4: +2 -1
lines
Diff to previous 1.4 (colored)
The ETSEC on the P1025 has been moved/split so the MDIO stayed in the same place but each ETSEC has been split into two virtual halves (G0 and G1) and each one has a new different base address. For some reason, tsec1 connects to phy 2 and tsec2 connects to phy 1. Adjust config file to match
Revision 1.4 / (download) - annotate - [select for diffs], Mon May 7 23:04:22 2012 UTC (12 months, 2 weeks ago) by matt
Branch: MAIN
CVS Tags: yamt-pagecache-base5,
jmcneill-usbmp-base10
Changes since 1.3: +2 -2
lines
Diff to previous 1.3 (colored)
Preserve some MACCFG2 bits
Revision 1.3 / (download) - annotate - [select for diffs], Thu Jun 9 19:11:06 2011 UTC (23 months, 1 week ago) by matt
Branch: MAIN
CVS Tags: yamt-pagecache-base4,
yamt-pagecache-base3,
yamt-pagecache-base2,
yamt-pagecache-base,
rmind-uvmplock-nbase,
rmind-uvmplock-base,
netbsd-6-base,
jmcneill-usbmp-pre-base2,
jmcneill-usbmp-base9,
jmcneill-usbmp-base8,
jmcneill-usbmp-base7,
jmcneill-usbmp-base6,
jmcneill-usbmp-base5,
jmcneill-usbmp-base4,
jmcneill-usbmp-base3,
jmcneill-usbmp-base2,
jmcneill-usbmp-base,
jmcneill-audiomp3-base,
jmcneill-audiomp3
Branch point for: yamt-pagecache,
netbsd-6,
jmcneill-usbmp
Changes since 1.2: +6 -6
lines
Diff to previous 1.2 (colored)
Fix ATTR register definitions
Revision 1.2 / (download) - annotate - [select for diffs], Tue Jan 18 01:02:54 2011 UTC (2 years, 4 months ago) by matt
Branch: MAIN
CVS Tags: uebayasi-xip-base7,
jym-xensuspend-nbase,
jym-xensuspend-base,
cherry-xenmp-base,
bouyer-quota2-nbase,
bouyer-quota2-base,
bouyer-quota2
Branch point for: rmind-uvmplock,
cherry-xenmp
Changes since 1.1: +581 -0
lines
Diff to previous 1.1 (colored)
Add support for BookE Freescale MPC85xx (e500 core) processors. Add fast softint support for PowerPC (though only booke uses it). Redo FPU/VEC support and add e500 SPE support. Rework trap/intrs to use a common trapframe format. Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.
Revision 1.1, Fri Jan 7 01:26:20 2011 UTC (2 years, 4 months ago) by matt
Branch: MAIN
CVS Tags: jruoho-x86intr-base
Branch point for: matt-nb5-pq3,
jruoho-x86intr
FILE REMOVED
file etsecreg.h was initially added on branch matt-nb5-pq3.