CVS log for src/sys/arch/powerpc/include/booke/cpuvar.h

Up to [cvs.NetBSD.org] / src / sys / arch / powerpc / include / booke

Request diff between arbitrary revisions

Keyword substitution: kv
Default branch: MAIN

Include missing opt_multiprocessor.h.

Sync with HEAD

Detangle some of the PowerPC CPU configuration spaghetti.

Sync with HEAD

s/static inline/static __inline/g for consistency.

update from HEAD

Sync with HEAD

This needs to define PRIxPTE too.

Resync to 2012-11-19 00:00:00 UTC

sync with head

move common tlb stuff to uvm

Add a machine splhist command to give (a incomplete) spl history.
(only the most recent are going to be accurate).

splraise(6) from 0 at 549214603
splraise(7) from 6 at 549214643 (+40)
splx(6) from 7 at 549214691 (+48)
splx(0) from 6 at 549214730 (+39)

Export dump_trapframe.

Add command line processing from uboot
bootm $loadaddr [opts] [device]
where opts is -[advqs] and device is the boot device.
cpu_rootconf will now wait a bit for devices to appear until the boot device
appears.

Fix -fno-common fallout.

Sync with current pulling P2020 and other newer processor support.

Pull in changes from -current to get ehci at cpunode working.

Modify mapiodev to take a third argument indicating whether the space
should be prefetchable (true) or not (false).

Declare cpu_hatch_data

Catchup with rmind-uvmplock merge.

Switch to using the common <common/pmap/tlb/tlb.h>

Explicitly include <powerpc/psl.h>

Move booke_fixup_stubs() to fixup.c and rename it to cpu_fixup_stubs().
This makes it easier for other PPC variants to use it.

Take the fast softint support in e500_intr.c and make generic so that it can
be used to provide fast softint for other interrupt implementations.

sync with head

Sync with HEAD.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

sync with head

Sync with HEAD

file cpuvar.h was added on branch rmind-uvmplock on 2011-03-05 20:51:37 +0000

add begging of single step support.  Since BookE doesn't support PSL_SE, if
userret find PSL_SE set in SRR1, it will call booke_sstep to setup the
debug registers.

Sync with HEAD

Add little endian bus_space_tags.
Note highest memory in cpu_softc.

Sync with HEAD

Allow code to allow inclusive/exclusive locators for subdevices.
(uses on mpc85xx to match on SVRs or not match on SVRs).

Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

Add SPE (signal processing engine) support for mpc85xx/booke.  Think of it
as AltiVec-lite (really lite).  Genercize AltiVec support so that it could
the same interface could support SPE as well.  Rework the FPU support along
the same lines.  Move the __asm() to their own XXX_subr.S (altivec, fpu, spe).

Add mpc85xx support for netbsd-5 (with some incompatible kernel changes).

file cpuvar.h was initially added on branch matt-nb5-pq3.