CVS log for src/sys/arch/powerpc/include/asm.h

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PR 58960: fix misunderstanding in semantic and provide both the original
id string as well as _NETBSD_REVISIONID.
Do not rely on string concatenation in the inline assembler, use .ascii
and .asciz for individual string parts instead.

PR 58960: powerpc/asm.h: Respect NETBSD_REVISIONID.

s/psuedo/pseudo/ in comments.

s/udpate/update/

Consistently use _LP64 instead of __LP64__, although both are defined for
powerpc64.

No binary changes intended.

Sync with HEAD

Sync with HEAD

It's __RCSID for an extra level of indirection on PPC

Mark the .ident section as mergable string section to avoid redundant
entries.

Merge changes from current as of 20200406

Pull up following revision(s) (requested by rin in ticket #755):

	sys/arch/evbppc/conf/std.virtex: revision 1.4
	sys/arch/powerpc/powerpc/trap_subr.S: revision 1.81
	sys/arch/powerpc/ibm4xx/4xx_trap_subr.S: revision 1.8
	sys/arch/evbppc/conf/std.walnut: revision 1.9
	common/lib/libc/arch/powerpc/atomic/atomic_op_asm.h: revision 1.7
	sys/arch/powerpc/include/asm.h: revision 1.49
	common/lib/libc/arch/powerpc/atomic/atomic_cas.S: revision 1.9
	sys/arch/powerpc/ibm4xx/trap_subr.S: revision 1.28
	sys/arch/powerpc/include/lock.h: revision 1.15
	sys/arch/evbppc/conf/std.obs266: revision 1.3
	common/lib/libc/arch/powerpc/atomic/atomic_swap.S: revision 1.8
	sys/arch/powerpc/powerpc/locore_subr.S: revision 1.61
	sys/arch/powerpc/powerpc/lock_stubs.S: revision 1.12
	sys/arch/evbppc/conf/std.obs200: revision 1.5

Implement workaround for IBM405 Errata 77 (aka CPU_210), where
interrupted stwcx. may errantly write data to memory:

     https://elinux.org/images/1/1d/Ppc405gp-errata.pdf

This is because stwcx. is split into two pieces in the pipeline.

We need to
(1) insert dcbt before every stwcx. instruction, as well as
(2) insert sync before every rfi/rfci instruction.

It is unclear which processors are affected, but according to Linux,
all 405-based cores up until 405GPR and 405EP are affected:

     https://github.com/torvalds/linux/blob/master/arch/powerpc/platforms/40x/Kconfig#L140

For kernel, this workaround can be restricted to affected processors.

However, for kernel modules and userland, we have to enable it for all
32bit powerpc archs in order to share common binaries as before.
Proposed on port-powerpc:

     http://mail-index.netbsd.org/port-powerpc/2020/02/21/msg003583.html

Implement workaround for IBM405 Errata 77 (aka CPU_210), where
interrupted stwcx. may errantly write data to memory:

    https://elinux.org/images/1/1d/Ppc405gp-errata.pdf

This is because stwcx. is split into two pieces in the pipeline.

We need to
(1) insert dcbt before every stwcx. instruction, as well as
(2) insert sync before every rfi/rfci instruction.

It is unclear which processors are affected, but according to Linux,
all 405-based cores up until 405GPR and 405EP are affected:

    https://github.com/torvalds/linux/blob/master/arch/powerpc/platforms/40x/Kconfig#L140

For kernel, this workaround can be restricted to affected processors.
However, for kernel modules and userland, we have to enable it for all
32bit powerpc archs in order to share common binaries as before.

Proposed on port-powerpc:

    http://mail-index.netbsd.org/port-powerpc/2020/02/21/msg003583.html

update from HEAD

Sync with HEAD

Pull up following revision(s) (requested by chs in ticket #492):
	lib/libc/arch/powerpc64/sys/__vfork14.S: revision 1.2
	lib/libc/arch/powerpc64/sys/__syscall.S: revision 1.2
	lib/libc/arch/powerpc/sys/__syscall.S: revision 1.3
	lib/libc/arch/powerpc64/sys/syscall.S: revision 1.2
	lib/libc/arch/powerpc/sys/__clone.S: revision 1.6
	lib/libc/arch/powerpc64/gen/__setjmp14.S: revision 1.3
	sys/arch/powerpc/include/asm.h: revision 1.47
	lib/libc/arch/powerpc64/sys/cerror.S: revision 1.6
	lib/libc/arch/powerpc64/sys/getcontext.S: revision 1.5
	lib/libc/arch/powerpc64/sys/brk.S: revision 1.5
	lib/libc/arch/powerpc64/sys/ptrace.S: revision 1.3
	lib/libc/arch/powerpc64/genassym.cf: revision 1.1
	lib/libc/arch/powerpc64/gen/__sigsetjmp14.S: revision 1.3
	lib/libc/arch/powerpc/sys/getcontext.S: revision 1.6
	compat/powerpc64/powerpc/bsd.powerpc.mk: revision 1.3
	lib/libc/arch/powerpc64/sys/pipe.S: revision 1.2
	lib/libc/arch/powerpc/sys/brk.S: revision 1.14
	lib/libc/arch/powerpc64/SYS.h: revision 1.3
	lib/libc/arch/powerpc64/sys/fork.S: revision 1.2
	lib/libc/arch/powerpc64/sys/__sigtramp2.S: revision 1.4
	lib/libc/arch/powerpc64/Makefile.inc: revision 1.3
	lib/libc/arch/powerpc/sys/pipe.S: revision 1.9
	lib/libc/compiler_rt/Makefile.inc: revision 1.25
	lib/libc/arch/powerpc64/sys/sbrk.S: revision 1.4, 1.5
	lib/libc/arch/powerpc64/sys/__clone.S: revision 1.2
	lib/libc/arch/powerpc/sys/sbrk.S: revision 1.13
	lib/libc/arch/powerpc/SYS.h: revision 1.13
powerpc64 uses the same sources as powerpc and needs the long double as
double-double sources.
-
Spell LdAddr consistently
-
Add LDFLAGS+=-Wl,-m,elf32ppc_nbsd
-
Fix cmpptr/cmpreq/etc to use right mnemonics
-
Minimize differences between powerpc and powerpc64
-
Fix powerpc64 assembly to use right instructions for 64bit CPUs.
-
Use hidden for __curbrk and __minbrk to avoid GOT/TOC relocations.

Name the offsets to the remaining fields in the ppc64
stack frame header.  Add a stack frame alignment macro
to avoid hard-coding that.

Fix cmpptr/cmpreq/etc to use right mnemonics

Rebase to HEAD as of a few days ago.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Add _XENTRY which doesn't set the section to .text

Add cmp{ptr,long,reg}{,l}{,i}

Use ## for concatenation

Add P2SZREG to be usign with .p2align

Pass PICFLAGS down to cc-as-as and use __PIC__ to decide if it is small
vs big PIC mode. Retire -DPIC and -DBIGPIC.

resync with head

Support 16bits over stack size.

sync with (a bit old) head

provide _ENTRY(x) because some code needs it.

- Indent ifdefs, comment endif and else cpp tags
- Add missing END macro for LP64
- Make whitespace consistent

Catchup with rmind-uvmplock merge.

sync with head

In INIT_CPUINFO, make L_CPU to set the cpu_info (just to be safe).

Sync with HEAD.

Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.

sync with head

Sync with HEAD

binutils is automagically doing securecrt so make sure plt calls are emitted
with the secureplt magic as well.

Init CI_CURPCB too.

Some ports use %r0 as tmp2 to INIT_CPUINFO which has adverse effects so
never use tmp2 to hold an address.

Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.

Kill _NOREGNAMES.  Everything should be using %rX now.  If it doesn't it
soon will.

Add PIC_GOTSETUP and PIC_TOCSETUP which replace the old methods to get the
GOT (via a bl) to the new REL16 based relocs.  This is another step to
supporting secure plt.

Add END(sym)
Add __RCSID (to match cdefs.h)

Add a END(y) for function sizes.

Allow implementation to not have an interrupt stack (booke).
Use .ident for RCSID

Consistently use .gnu.warning with .pushsectio and .popsection on all
architectures instead of obsolete STABS frames for linker warnings.

Sync with HEAD.

sync with head

Put ASM RCSIDs into .ident

Rename L_ADDR to L_PCB and amend some comments accordingly.

Kill proc0paddr.  Use lwp0.l_addr instead.

Sync with HEAD.

sync with head.

sync with HEAD

sync with head.

Add clrr{ptr,long,reg}i, l{ptr,long,reg}arx, st{ptr,long,reg}cx macros

sync with HEAD

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

sync with head.

sync with HEAD

Sync with head.

Sync with head.

Update to HEAD.

merge yamt-idlelwp branch.  asked by core@.  some ports still needs work.

from doc/BRANCHES:

	idle lwp, and some changes depending on it.

	1. separate context switching and thread scheduling.
	   (cf. gmcgarry_ctxsw)
	2. implement idle lwp.
	3. clean up related MD/MI interfaces.
	4. make scheduler(s) modular.

Adapt powerpc to yamt-idlelwp.  Nuke cpu_setfunc.
Don't define _HAVE_BITENDIAN_BITOPS.  Misc cleanups.

sync with head.

sync with head

sync with head

Merge from HEAD.

wrap as(1)-only elements in #ifdef _LOCORE

Add stmd and lmd macros.

more refinements for ppc64 PIC/PLT/TOC issues

Add ppc64 ENTRY() macro that defines the descriptor and the dot symbol.

sync with head.

sync with head.

Add a STRONG_ALIAS macro

merge ktrace-lwp.

sync with -current

Sync with HEAD.

Use lis@h/ori@l instead of lis@ha/addi@l since we may use r0 and addi
is one of those funny instructions that treats r0 == 0 when used as the
first arg.

Fixes problems on ibm4xx.  Ok'd by matt@.

Split the hw-dependent powermanglement into its own function and make
Idle call that.  Add a ci_idlespin function pointer to cpu_info.
Update INIT_CPUINFO to initialize it to a naked 'blr' instruction.
In oea/cpu_subr.c, add cpu_idlespin and make ci_idlespin point to it.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

Pull up revision 1.10 (requested by skrll in ticket #1725):
Don't define register references if not KERNEL or STANDALONE.

Nuke ci_spillstk/CI_SPILLSTK.  No longer needed.

Nuke stmreg/ldmreg.  PPC64 doesn't have a lmd/stmd so make sure lmw/stmw
don't invoke valid instructions on PPC64.

Define SZREG {4,8} appropriately.  Add pseudo-instructions (via #define)
to load/store int, long, pointer, register, multiple registers.  This is so
assembly files can be support IPL32 and LP64 PowerPC implementations.

Perform a rototill of the powerpc code.  Mandate use of SPRG0 to store
a pointer to current cpu's cpu_info structure.  Use cpu_info for
intstk,intr_depth,still_stk,idle_pcb,curpcb,curlwp,etal even on
non-MULTIPROCESSOR machines.  Add common macros GET_CPUINFO and
INIT_CPUINFO to get and initialize the cpu_info struct on startup.  Make
ibm4xx use the standard <powerpc/frame.h>.  Use IFRAME_xx in ibm4xx
trap_subr.S instead of explicit magic offsets.  Move INTSTK and SPILLSTK
to std.<platform>.  Change faultbuf to a struct instead of an array.

On MPC6XX cpus, stop using the vector page for temporary space and use
reserved space in cpu_info.

Add a temporary bridge to use %foo regnames in kernel / standalone code.

sync kqueue branch with HEAD

catch up with -current.

Catch up to -current.

Don't define register references if not KERNEL or STANDALONE.

catch up with -current.

Add ENTRY_NOPROFILE().

Catch up to -current.

file asm.h was added on branch nathanw_sa on 2002-08-01 02:43:02 +0000

Add a port to IBM's PPC405GP Reference Board (the "walnut")
by Eduardo Horvath and Simon Burge of Wasabi Systems.

IBM 4xx series CPU features:
 - New pmap and revised trap handler.
 - Support on-chip timers, PCI controller, UARTs
 - Framework for on-chip ethernet and watchdog timer.
General PowerPC features:
 - Add in-kernel PPC floating point emulation
 - New in{,4}_cksum that is between 1.5 and 5 times faster than the
   old version depending on CPU type.
General changes:
 - Kernel support for generic dbsym-style symbols.

Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.

Pull up rev. 1.7 (approved by thorpej):
For ELF, add a WEAK_ALIAS() macro.

Add a WEAK_ALIAS() macro.

First-cut of profiling support.
XXX userland only, for now.

Implement WARN_REFERENCES().

Add PIC definitions.

Update for Elf.

PROF -> GPROF

PowerPC port