Annotation of src/sys/arch/pmax/tc/asc_pmaz.c, Revision 1.6
1.6 ! nisimura 1: /* $NetBSD: asc_pmaz.c,v 1.5 2000/03/06 03:09:43 mhitch Exp $ */
1.2 nisimura 2:
1.4 nisimura 3: /*-
4: * Copyright (c) 2000 The NetBSD Foundation, Inc.
5: * All rights reserved.
6: *
7: * This code is derived from software contributed to The NetBSD Foundation
8: * by Tohru Nishimura.
1.2 nisimura 9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. All advertising materials mentioning features or use of this software
19: * must display the following acknowledgement:
1.4 nisimura 20: * This product includes software developed by the NetBSD
21: * Foundation, Inc. and its contributors.
22: * 4. Neither the name of The NetBSD Foundation nor the names of its
23: * contributors may be used to endorse or promote products derived
24: * from this software without specific prior written permission.
1.2 nisimura 25: *
1.4 nisimura 26: * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27: * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36: * POSSIBILITY OF SUCH DAMAGE.
1.2 nisimura 37: */
38:
39: #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
1.6 ! nisimura 40: __KERNEL_RCSID(0, "$NetBSD: asc_pmaz.c,v 1.5 2000/03/06 03:09:43 mhitch Exp $");
1.2 nisimura 41:
42: #include <sys/types.h>
43: #include <sys/param.h>
44: #include <sys/systm.h>
45: #include <sys/device.h>
46: #include <sys/buf.h>
47:
48: #include <dev/scsipi/scsi_all.h>
49: #include <dev/scsipi/scsipi_all.h>
50: #include <dev/scsipi/scsiconf.h>
51: #include <dev/scsipi/scsi_message.h>
52:
53: #include <machine/bus.h>
54:
55: #include <dev/ic/ncr53c9xreg.h>
56: #include <dev/ic/ncr53c9xvar.h>
57:
58: #include <dev/tc/tcvar.h>
59:
60: struct asc_softc {
61: struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
62: bus_space_tag_t sc_bst;
63: bus_space_handle_t sc_bsh;
64: bus_dma_tag_t sc_dmat;
65: bus_dmamap_t sc_dmamap;
1.4 nisimura 66: caddr_t *sc_dmaaddr;
67: size_t *sc_dmalen;
68: size_t sc_dmasize;
1.2 nisimura 69: int sc_active; /* DMA active ? */
70: int sc_ispullup; /* DMA into main memory? */
71:
72: /* XXX XXX XXX */
73: caddr_t sc_base, sc_bounce, sc_target;
74: };
75:
1.4 nisimura 76: static int asc_pmaz_match __P((struct device *, struct cfdata *, void *));
77: static void asc_pmaz_attach __P((struct device *, struct device *, void *));
1.2 nisimura 78:
79: struct cfattach xasc_pmaz_ca = {
80: sizeof(struct asc_softc), asc_pmaz_match, asc_pmaz_attach
81: };
82:
83: static u_char asc_read_reg __P((struct ncr53c9x_softc *, int));
84: static void asc_write_reg __P((struct ncr53c9x_softc *, int, u_char));
85: static int asc_dma_isintr __P((struct ncr53c9x_softc *));
1.4 nisimura 86: static void asc_pmaz_reset __P((struct ncr53c9x_softc *));
87: static int asc_pmaz_intr __P((struct ncr53c9x_softc *));
88: static int asc_pmaz_setup __P((struct ncr53c9x_softc *, caddr_t *,
89: size_t *, int, size_t *));
90: static void asc_pmaz_go __P((struct ncr53c9x_softc *));
91: static void asc_pmaz_stop __P((struct ncr53c9x_softc *));
1.2 nisimura 92: static int asc_dma_isactive __P((struct ncr53c9x_softc *));
93: static void asc_clear_latched_intr __P((struct ncr53c9x_softc *));
94:
1.4 nisimura 95: static struct ncr53c9x_glue asc_pmaz_glue = {
1.2 nisimura 96: asc_read_reg,
97: asc_write_reg,
98: asc_dma_isintr,
99: asc_pmaz_reset,
100: asc_pmaz_intr,
101: asc_pmaz_setup,
102: asc_pmaz_go,
103: asc_pmaz_stop,
104: asc_dma_isactive,
105: asc_clear_latched_intr,
106: };
107:
108: /*
109: * Parameters specific to PMAZ-A TC option card.
110: */
111: #define PMAZ_OFFSET_53C94 0x0 /* from module base */
112: #define PMAZ_OFFSET_DMAR 0x40000 /* DMA Address Register */
113: #define PMAZ_OFFSET_RAM 0x80000 /* 128KB SRAM buffer */
114: #define PMAZ_OFFSET_ROM 0xc0000 /* diagnostic ROM */
115:
116: #define PMAZ_RAM_SIZE 0x20000 /* 128k (32k*32) */
117: #define PER_TGT_DMA_SIZE ((PMAZ_RAM_SIZE/7) & ~(sizeof(int)-1))
118:
119: #define PMAZ_DMAR_WRITE 0x80000000 /* DMA direction bit */
120: #define PMAZ_DMAR_MASK 0x1ffff /* 17 bits, 128k */
121: #define PMAZ_DMA_ADDR(x) ((unsigned)(x) & PMAZ_DMAR_MASK)
122:
1.4 nisimura 123: static int
1.2 nisimura 124: asc_pmaz_match(parent, cfdata, aux)
125: struct device *parent;
126: struct cfdata *cfdata;
127: void *aux;
128: {
129: struct tc_attach_args *d = aux;
130:
131: if (strncmp("PMAZ-AA ", d->ta_modname, TC_ROM_LLEN))
132: return (0);
133:
134: return (1);
135: }
136:
1.4 nisimura 137: static void
1.2 nisimura 138: asc_pmaz_attach(parent, self, aux)
139: struct device *parent, *self;
140: void *aux;
141: {
142: struct tc_attach_args *ta = aux;
143: struct asc_softc *asc = (struct asc_softc *)self;
144: struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x;
145:
146: /*
147: * Set up glue for MI code early; we use some of it here.
148: */
149: sc->sc_glue = &asc_pmaz_glue;
150: asc->sc_bst = ta->ta_memt;
151: asc->sc_dmat = ta->ta_dmat;
152: if (bus_space_map(asc->sc_bst, ta->ta_addr,
153: PMAZ_OFFSET_RAM + PMAZ_RAM_SIZE, 0, &asc->sc_bsh)) {
154: printf("%s: unable to map device\n", sc->sc_dev.dv_xname);
155: return;
156: }
157: asc->sc_base = (caddr_t)ta->ta_addr; /* XXX XXX XXX */
158:
1.6 ! nisimura 159: tc_intr_establish(parent, ta->ta_cookie, IPL_BIO, ncr53c9x_intr, sc);
1.2 nisimura 160:
161: sc->sc_id = 7;
162: sc->sc_freq = (ta->ta_busspeed) ? 25000000 : 12500000;
163:
164: /* gimme Mhz */
165: sc->sc_freq /= 1000000;
166:
167: /*
168: * XXX More of this should be in ncr53c9x_attach(), but
169: * XXX should we really poke around the chip that much in
170: * XXX the MI code? Think about this more...
171: */
172:
173: /*
174: * Set up static configuration info.
175: */
176: sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
177: sc->sc_cfg2 = NCRCFG2_SCSI2;
178: sc->sc_cfg3 = 0;
179: sc->sc_rev = NCR_VARIANT_NCR53C94;
180:
181: /*
182: * XXX minsync and maxxfer _should_ be set up in MI code,
183: * XXX but it appears to have some dependency on what sort
184: * XXX of DMA we're hooked up to, etc.
185: */
186:
187: /*
188: * This is the value used to start sync negotiations
189: * Note that the NCR register "SYNCTP" is programmed
190: * in "clocks per byte", and has a minimum value of 4.
191: * The SCSI period used in negotiation is one-fourth
192: * of the time (in nanoseconds) needed to transfer one byte.
193: * Since the chip's clock is given in MHz, we have the following
194: * formula: 4 * period = (1000 / freq) * 4
195: */
196: sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4;
197:
198: sc->sc_maxxfer = 64 * 1024;
199:
200: /* Do the common parts of attachment. */
1.6 ! nisimura 201: ncr53c9x_attach(sc, NULL, NULL);
1.2 nisimura 202: }
203:
1.4 nisimura 204: static void
1.2 nisimura 205: asc_pmaz_reset(sc)
206: struct ncr53c9x_softc *sc;
207: {
208: struct asc_softc *asc = (struct asc_softc *)sc;
209:
210: asc->sc_active = 0;
211: }
212:
1.4 nisimura 213: static int
1.2 nisimura 214: asc_pmaz_intr(sc)
215: struct ncr53c9x_softc *sc;
216: {
217: struct asc_softc *asc = (struct asc_softc *)sc;
218: int trans, resid;
219:
220: resid = 0;
221: if (!asc->sc_ispullup &&
222: (resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
223: NCR_DMA(("pmaz_intr: empty FIFO of %d ", resid));
224: DELAY(1);
225: }
226:
227: resid += NCR_READ_REG(sc, NCR_TCL);
228: resid += NCR_READ_REG(sc, NCR_TCM) << 8;
229:
230: trans = asc->sc_dmasize - resid;
231:
232: if (asc->sc_ispullup)
233: memcpy(asc->sc_target, asc->sc_bounce, trans);
234: *asc->sc_dmalen -= trans;
235: *asc->sc_dmaaddr += trans;
236: asc->sc_active = 0;
237:
238: return (0);
239: }
240:
1.4 nisimura 241: static int
1.2 nisimura 242: asc_pmaz_setup(sc, addr, len, datain, dmasize)
243: struct ncr53c9x_softc *sc;
244: caddr_t *addr;
245: size_t *len;
246: int datain;
247: size_t *dmasize;
248: {
249: struct asc_softc *asc = (struct asc_softc *)sc;
250: u_int32_t tc_dmar;
251: size_t size;
252:
253: asc->sc_dmaaddr = addr;
254: asc->sc_dmalen = len;
255: asc->sc_ispullup = datain;
256:
257: NCR_DMA(("pmaz_setup: start %d@%p, %s\n",
258: *asc->sc_dmalen, *asc->sc_dmaaddr, datain ? "IN" : "OUT"));
259:
260: size = *dmasize;
261: if (size > PER_TGT_DMA_SIZE)
262: size = PER_TGT_DMA_SIZE;
263: *dmasize = asc->sc_dmasize = size;
264:
265: NCR_DMA(("pmaz_setup: dmasize = %d\n", asc->sc_dmasize));
266:
267: asc->sc_bounce = asc->sc_base + PMAZ_OFFSET_RAM;
268: asc->sc_bounce += PER_TGT_DMA_SIZE *
269: sc->sc_nexus->xs->sc_link->scsipi_scsi.target;
270: asc->sc_target = *addr;
271:
272: if (!asc->sc_ispullup)
273: memcpy(asc->sc_bounce, asc->sc_target, size);
274:
275: #if 1
276: if (asc->sc_ispullup)
277: tc_dmar = PMAZ_DMA_ADDR(asc->sc_bounce);
278: else
279: tc_dmar = PMAZ_DMAR_WRITE | PMAZ_DMA_ADDR(asc->sc_bounce);
280: bus_space_write_4(asc->sc_bst, asc->sc_bsh, PMAZ_OFFSET_DMAR, tc_dmar);
281: asc->sc_active = 1;
282: #endif
283: return (0);
284: }
285:
1.4 nisimura 286: static void
1.2 nisimura 287: asc_pmaz_go(sc)
288: struct ncr53c9x_softc *sc;
289: {
290: #if 0
291: struct asc_softc *asc = (struct asc_softc *)sc;
292: u_int32_t tc_dmar;
293:
294: if (asc->sc_ispullup)
295: tc_dmar = PMAZ_DMA_ADDR(asc->sc_bounce);
296: else
297: tc_dmar = PMAZ_DMAR_WRITE | PMAZ_DMA_ADDR(asc->sc_bounce);
298: bus_space_write_4(asc->sc_bst, asc->sc_bsh, PMAZ_OFFSET_DMAR, tc_dmar);
299: asc->sc_active = 1;
300: #endif
301: }
302:
303: /* NEVER CALLED BY MI 53C9x ENGINE INDEED */
1.4 nisimura 304: static void
1.2 nisimura 305: asc_pmaz_stop(sc)
306: struct ncr53c9x_softc *sc;
307: {
308: #if 0
309: struct asc_softc *asc = (struct asc_softc *)sc;
310:
311: if (asc->sc_ispullup)
312: memcpy(asc->sc_target, asc->sc_bounce, asc->sc_dmasize);
313: asc->sc_active = 0;
314: #endif
315: }
316:
317: /*
318: * Glue functions.
319: */
320: static u_char
321: asc_read_reg(sc, reg)
322: struct ncr53c9x_softc *sc;
323: int reg;
324: {
325: struct asc_softc *asc = (struct asc_softc *)sc;
326: u_char v;
327:
328: v = bus_space_read_4(asc->sc_bst, asc->sc_bsh,
329: reg * sizeof(u_int32_t)) & 0xff;
330:
331: return (v);
332: }
333:
334: static void
335: asc_write_reg(sc, reg, val)
336: struct ncr53c9x_softc *sc;
337: int reg;
338: u_char val;
339: {
340: struct asc_softc *asc = (struct asc_softc *)sc;
341:
342: bus_space_write_4(asc->sc_bst, asc->sc_bsh,
343: reg * sizeof(u_int32_t), val);
344: }
345:
346: static int
347: asc_dma_isintr(sc)
348: struct ncr53c9x_softc *sc;
349: {
350: return !!(NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT);
351: }
352:
353: static int
354: asc_dma_isactive(sc)
355: struct ncr53c9x_softc *sc;
356: {
357: struct asc_softc *asc = (struct asc_softc *)sc;
358:
359: return (asc->sc_active);
360: }
361:
362: static void
363: asc_clear_latched_intr(sc)
364: struct ncr53c9x_softc *sc;
365: {
366: }
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