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File: [cvs.NetBSD.org] / src / sys / arch / news68k / dev / dmac_0266.h (download)

Revision 1.1, Thu Dec 9 14:53:04 1999 UTC (21 years, 1 month ago) by tsutsui
Branch: MAIN
CVS Tags: wrstuden-devbsize-base, wrstuden-devbsize-19991221, thorpej_scsipi_nbase, thorpej_scsipi_beforemerge, thorpej_scsipi_base, thorpej-mips-cache-base, thorpej-mips-cache, thorpej-devvp-base3, thorpej-devvp-base2, thorpej-devvp-base, thorpej-devvp, pre-chs-ubcperf, post-chs-ubcperf, newlock-base, newlock, netbsd-2-base, netbsd-2-1-RELEASE, netbsd-2-1-RC6, netbsd-2-1-RC5, netbsd-2-1-RC4, netbsd-2-1-RC3, netbsd-2-1-RC2, netbsd-2-1-RC1, netbsd-2-1, netbsd-2-0-base, netbsd-2-0-RELEASE, netbsd-2-0-RC5, netbsd-2-0-RC4, netbsd-2-0-RC3, netbsd-2-0-RC2, netbsd-2-0-RC1, netbsd-2-0-3-RELEASE, netbsd-2-0-2-RELEASE, netbsd-2-0-1-RELEASE, netbsd-2-0, netbsd-2, netbsd-1-6-base, netbsd-1-6-RELEASE, netbsd-1-6-RC3, netbsd-1-6-RC2, netbsd-1-6-RC1, netbsd-1-6-PATCH002-RELEASE, netbsd-1-6-PATCH002-RC4, netbsd-1-6-PATCH002-RC3, netbsd-1-6-PATCH002-RC2, netbsd-1-6-PATCH002-RC1, netbsd-1-6-PATCH002, netbsd-1-6-PATCH001-RELEASE, netbsd-1-6-PATCH001-RC3, netbsd-1-6-PATCH001-RC2, netbsd-1-6-PATCH001-RC1, netbsd-1-6-PATCH001, netbsd-1-6, netbsd-1-5-base, netbsd-1-5-RELEASE, netbsd-1-5-PATCH003, netbsd-1-5-PATCH002, netbsd-1-5-PATCH001, netbsd-1-5-BETA2, netbsd-1-5-BETA, netbsd-1-5-ALPHA2, netbsd-1-5, nathanw_sa_end, nathanw_sa_before_merge, nathanw_sa_base, nathanw_sa, minoura-xpg4dl-base, minoura-xpg4dl, kqueue-beforemerge, kqueue-base, kqueue-aftermerge, kqueue, kent-audio1-base, kent-audio1, ifpoll-base, gmcgarry_ucred_base, gmcgarry_ucred, gmcgarry_ctxsw_base, gmcgarry_ctxsw, gehenna-devsw-base, gehenna-devsw, fvdl_fs64_base, eeh-devprop-base, eeh-devprop, chs-ubc2-newbase
Branch point for: wrstuden-devbsize, thorpej_scsipi, ktrace-lwp

Initial import of news68k port.

/*	$NetBSD: dmac_0266.h,v 1.1 1999/12/09 14:53:04 tsutsui Exp $	*/

/*-
 * Copyright (C) 1999 Izumi Tsutsui.  All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/* DMAC 266 register definition */

struct dma_regs {
	u_int32_t	ctl;			/* Control Register	*/
#define	 DC_CTL_RST	0x04			/* Soft Reset		*/
#define	 DC_CTL_MOD	0x02			/* set transfer dir	*/
#define	 DC_CTL_ENB	0x01			/* set Enable		*/

	u_int32_t	stat;			/* Status Register 	*/
#define	 DC_ST_TCZ	0x10			/* Transfer Count Zero 	*/
#define	 DC_ST_INT	0x08			/* Interrupt 		*/
#define	 DC_ST_MOD	0x02			/* monitor transfer dir	*/
#define	 DC_ST_ENB	0x01			/* monitor Enable	*/

	u_int32_t	tcnt;			/* transfer counter	*/
	u_int32_t	tag;			/* Tag Register 	*/
	u_int32_t	offset;			/* Offset Register 	*/
	u_int32_t	mapent;			/* Map entry Register 	*/
};

#define DMAC_WAIT	__asm __volatile ("nop; nop; nop; nop; nop; nop")

#define DMAC_SEG_SIZE	0x1000 /* 4kbyte per DMA segment */
#define DMAC_SEG_OFFSET	0x0fff
#define DMAC_SEG_SHIFT	12