CVS log for src/sys/arch/netwinder/netwinder/netwinder_machdep.c

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Keyword substitution: kv
Default branch: MAIN

Add 0x prefix before hex physmem in couple more places.
For netwinder move physmem arg to new line to keep line <80 symbols.

s/boundries/boundaries/, s/itterate/iterate/ and few more typos.

fix multiplei repetitive typos in comments, messages and documentation. mainly because copy paste code big amount of files are affected.

Sync with HEAD

Sync with HEAD

PMAP_DEBUG has been deleted on arm

Trailing whitespace

Mostly merge changes from HEAD upto 20200411

Consistently use vaddr_t as initarm and friends return type.

Makes no difference to binaries except for aarch64 where it's required

KNF

Sync with HEAD

Sync with HEAD, resolve a couple of conflicts

Fix a commit

update from HEAD

Sync with HEAD

Sync with HEAD.  (Note that most of these changes are simply $NetBSD$
tag issues.)

physmem should be of type psize_t

Also, use PRIxPSIZE when printf(9)ing physmem.

switch all ports to use uvm_init.c:uvm_md_init()

uvm_setpagesize() is now subsumed within this funciton.

Replace more vm_offset_t, vm_size_t with vaddr_t, vsize_t
Use paddr_t for msgbufphys

vm_offset_t -> vaddr_t, vm_size_t -> vsize_t

Rebase to HEAD as of a few days ago.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Fix more <arm/locore.h> lossage

Resync to 2012-11-19 00:00:00 UTC

sync with head

Adapt to the changed signature of pckbc_cnattach().

Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed.  Default cortex to pmap_needs_fixup = 1.  But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.

Move the standard definitions of the {UND,IRQ,FIQ,ABT}_STACK_SIZE to
<arm32/machdep.h>
Move the extern for cpu_reset_address to the same file.
Add cpu_reset_address_paddr.
Kill cpu_reset_v4_MMU_disable.
if cpu_reset_address is NULL, then the MMU will be disabled.

Remove uneeded declarations.

#include <sys/bus.h> instead of <machine/bus.h>.

dependant -> dependent

sync with head

More setttb() -> cpu_setttb() for readability & consistency.  Missing instances
pointed out by tsutsui@ & nonaka@, thanks.

- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places.  Reduce sys/user.h inclusions.

Kill proc0paddr.  Use lwp0.l_addr instead.

sync with head.

Remove all declarations of physmem from sys/arch.  Add an include of
<sys/systm.h> to the one file that did not already contain it.
This now means that physmem can be changed by updating systm.h and uvm_page.c
(excluding fixing printfs)

Sync with HEAD.

Commit is split, to avoid a "too many arguments" protocol error.

sync with head.

Sync with HEAD.

ANSIfy another 1261 function definitions.
The only ones left in sys are beyond by sed script!
(or in sys/dist or sys/external)
Mostly they have function pointer parameters.

Sync with HEAD.

Sync with HEAD.

Update haad-dm branch to haad-dm-base2.

As discussed on tech-kern: mutex_init is too heavyweight for early bootstrap
phases, so move the initialization of the ksyms mutex back into main via
a function called ksyms_init. Rename the existing (but quite different)
ksyms_init* variations into ksyms_addsyms_elf() and ksyms_addsyms_explicit()
and adapt machdep code accordingly.

Remove LKMs and switch to the module framework, pass 1.

Proposed on tech-kern@.

It is not appropriate to call pmf_system_shutdown(9) from
doshutdownhooks(9): shutdown hooks registered by shutdownhook_establish(9)
expect to be called with interrupts disabled, but shutdown hooks
registered with pmf_device_register1(9) expect to be called with
interrupts enabled.  So I have made two changes:

1 Do not call pmf_system_shutdown() from doshutdownhooks().  Instead,
change every call to doshutdownhooks() to a call to doshutdownhooks()
followed by a call to pmf_system_shutdown().  No functional change
is intended by this change.

2 Make i386 re-enable interrupts briefly while it calls
pmf_system_shutdown().  I leave it to others either to fix the
other ports, or to factor out some MI shutdown code, as joerg@
suggests, and fix that.  Note that a functional change *is* intended
by this change.

I hope that this patch will stop us from flip-flopping between
calling doshutdownhooks() and pmf_system_shutdown() sometimes with
and sometimes without interrupts enabled.

Sync with HEAD.

sync with head.

sync with head.

Merge kernel changes in matt-armv6 to HEAD.

sync with HEAD

Sync with HEAD.

Sync with HEAD.

Adapt to new pmap_bootstrap signature.

sync with head

Sync with HEAD

Remove arm support for IPKDB.

It hasn't worked since arm was broken out from arm32 in Jan 2001, and
no-one has noticed or cared to fix it.

sync with head.

Sync with HEAD.

Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

Sync with head.

sync with head.

sync with head.

s/independant/independent/, from Zafer.

sync with head

sync with head

Merge from HEAD.

Fix a build problem ('kernel_l1pt.pv_va may be used uninitialized').

sync with head.

Merge 2006-05-24 NetBSD-current into the "peter-altq" branch.

Sync with head.

sync with head - hopefully this will work

sync with head

kernelstack and proc0paddr are defined in arm32_machdep.c
Change local definions into declations.

merge ktrace-lwp.

Sync with HEAD. Here we go again...

Adapt to shadowing and qualifier-cast warnings.

Sync with HEAD.

Fix comments slighly

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

Uppercase CPU, plural is CPUs.

__KERNEL_RCSID()

wscons as console support.

XXX: the way we pre-map memory for igsfb(4) is kludgy.

Also pass a type argument to comcnattach() and com_kgdb_attach().
comspeed() (and thus cominit()) may need this information.

Drop __P().  Drop redundant prototypes that we either don't need or
get from <arm/arm32/machdep.h> anyway.  Consistently use ANSI style
function definitions (most functions already were in ANSI style).
Generated object file is not changed.

In initarm() turn the LED yellow at the beginning, green at the end.

Rewrite netwinder_restart to be self-contained, when it runs the MMU
is disabled.  Set cpu_reset_address to the physical address of
netwinder_restart, not virtual.

Move KERNEL_VM_SIZE into the C files where its used.

Move KERNEL_VM_BASE inside where it is used (it won't be there for long).

Reduce differences between ARM32_NEW_VM_LAYOUT and not; always pass
the start and end of the kernel managed virtual address space to
pmap_bootstrap() in the new pmap.

Remove old pmap support for platforms which have fully switched over.

Eliminate PTE_BASE and the PT-PT completely in the ARM32_PMAP_NEW case.
Also in the ARM32_PMAP_NEW case, reclaim the USPACE-bytes of wasted space
at the top of the user address that hasn't been needed for a very very
long time.

Call ksyms_init() instead of ddb_init() in case of
	NKSYMS || defined(DDB) || defined(LKM)

New pmap for netwinder.

Use PAGE_SIZE rather than NBPG.

Initialize the new members of consdev (cn_halt, cn_flush) to NULL so
that this compiles again.

Revert pull-up of revision 1.35 (requested by rearnsha in ticket #1170):
  Revert cached memory access to L1 tables, this causes instability
  on the release branch.

Merge the nathanw_sa branch.

Pull up revision 1.35 (requested by thorpej in ticket #712):
  Do cached memory access to L1 tables, making sure to
  write-back the cache after any L1 table modifications.
(Overlooked while processing pull-up earlier -- sorry!)

Catch up to -current

Checkin new interrupt handling code for the footbridge.
This is based upon Jason's work on xscale.

Most of the interrupt handling code is now written in C using an asm stub to
call into the C code.

spl* now only updates a software mask, and does not update the hardware,
this should be much faster.

The new code works well on cats, it's untested on netwinder, but should work.

The code implements generic soft interrupts.

More work is still required to bring the isa interrupt handling code upto
scratch currently all isa interrupts are handled at IPL_BIO on the footbridge.
This may cause isa interrupts to be handled later than they should be.
I plan to fix this in the near future.

sync with -current:
Merge isa_machdep.c from netwinder and cats into footbridge/isa

Catch up to -current.

Merge isa_machdep.c from netwinder and cats into footbridge/isa (where it
joins other machdep files)
Saves maintaining multiple copies of the same thing, the only differences
were:
IRQ line used on the footbridge (made that a define in include/isa_machdep.h)
name of a dma_ranges variable contained arch name, so just made it generic.

sync kqueue with -current; this includes merge of gehenna-devsw branch,
merge of i386 MP branch, and part of autoconf rototil work

Properly prototype the netwinder isa/pci init funcs.

Make this compile with strict prototypes.

remove trailing \n in panic().  approved perry.

sync kqueue branch with HEAD

catch up with -current.

Sync with -current.

Enable caching on kernel and user page tables.  This saves having
to do uncached memory access during VM operations (which can be
quite expensive on some CPUs).

We currently write-back PTEs as soon as they're modified; there is
some room for optimization (to write them back in larger chunks).
For PTEs in the APTE space (i.e. PTEs for pmaps that describe another
process's address space), PTEs must also be evicted from the cache
complete (PTEs in PTE space will be evicted durint a context switch).

Do cached memory access to L1 tables, making sure to write-back the
cache after any L1 table modifications.

Catch up to -current.

Overhaul how DMA ranges work in the ARM bus_dma implementation.

A new "arm32_dma_range" structure now describes a DMA window, with
a system address base, bus address base, and length.  In addition to
providing info about which memory regions are legal for DMA, the new
structure provides address translation support, as well.

As before, if a tag does not list any ranges, then all addresses are
considered valid, and no DMA address translation is performed.

This allows us to remove a large chunk of code which was duplicated and
tweaked slightly (to do the address translation) from the stock ARM
bus_dma in the XScale IOP and ARM Integrator ports.

Test compiled on all ARM platforms, test booted on Intel IQ80321 and Shark.

Move the calls to uvm_page_physload() out of pmap_bootstrap() and
into platform-specific initialization code, giving platform-specific
code control over which free list a given chunk of memory gets put
onto.

Changes are essentially mechanical.  Test compiled for all ARM
platforms, test booted on Intel IQ80321 and Shark.

Discussed some time ago on port-arm.

Move the uvm_setpagesize() call to platform-dependent code in preparation
for other changes to pmap_bootstrap().

Curproc->curlwp renaming.

Change uses of "curproc->l_proc" back to "curproc", which is more like the
original use. Bare uses of "curproc" are now "curlwp".

"curproc" is now #defined in proc.h as ((curlwp) ? (curlwp)->l_proc) : NULL)
so that it is always safe to reference curproc (*de*referencing curproc
is another story, but that's always been true).

catch up with -current on kqueue branch

Catch up to -current.

Use the bus_space_generic bus space ops.

* Rewrite the 32-bit ARM pte.h based on the ARM architecture manual.
  Significant cleanup, here, including better PTE bit names.
* Add XScale PTE extensions (ECC enable, write-allocate cache mode).
* Mechanical changes everywhere else to update for new pte.h.  While
  doing this, two bugs (as a result of typos) were fixed in

	arm/arm32/bus_dma.c
	evbarm/integrator/int_bus_dma.c

Clean up handling of the vector page on 32-bit ARM systems:
* Don't refer to VA 0, instead refer to a new variable: vector_page
* Delete the old zero_page_*() functions, replacing them with a new
  one: vector_page_setprot().
* When manipulating vector page mappings in user pmaps, only do so if
  the vector page is below KERNEL_BASE (if it's above KERNEL_BASE, the
  vector page is mapped by the kernel pmap).
* Add a new function, arm32_vector_init(), which takes the virtual
  address of the vector page (which MUST be valid when the function
  is called) and a bitmask of vectors the kernel is going to take
  over, and performs all vector page initialization, including setting
  the V bit in the CPU Control register ("relocate vectors to high
  address"), if necessary.

Fetch the memory size from the NeTTrom boot info.

Clean up Netwinder bootstrap:
* Put the code that runs with the MMU off in a separate section (.start).
* Use a linker script to set the VMA/LMA appropriately for each section.
* Fix kernel page table allocation and mapping of kernel text/data/bss.

...and now that kernel images > 2MB work:
* Add SYMTAB_SPACE to the GENERIC kernel so that we have DDB symbols.
* Use dbsym to load the kernel's DDB symbol area.

Catch up to -current.
(CVS: It's not just a program. It's an adventure!)

* Fix use of pmap_curmaxkvaddr.
* Use the PTP hint in the pmap.

* Rename PROCESS_PAGE_TBLS_BASE -> PTE_BASE
* Rename ALT_PAGE_TBLS_BASE -> APTE_BASE
* Garbage-collect PAGE_TABLE_SPACE_START

Catch up with -current.

Implement pmap_growkernel for arm32 based ports.
Note that this has been compiled on some systems, cats, IQ80310, IPAQ, netwinder and shark (note that shark's build is currently broken due to other reasons), but only actually run on cats.
Shark doesn't make use of the functionality as I believe there has to be a correlation between OFW and the kernel tables so that calls into OFW work.

Catch up to -current.

Fix the "va" argument to pmap_map_entry() when mapping kernel_ptpt.

Change pmap_map_entry() to work like pmap_map_chunk(): take a pointer
to the L1 table and a virtual address, and no pointer to the L2 table.
The L2 table will be looked up by pmap_map_entry(), which will panic
if the there is no L2 table for the requested VA.

NOTE: IT IS EXTREMELY IMPORTANT THAT THE CORRECT VIRTUAL ADDRESS
BE PROVIDED TO pmap_map_entry()!  Notably, the code that mapped
the kernel L2 tables into the kernel PT mapping L2 table were not
passing actual virtual addresses, but rather offsets into the range
mapped by the L2 table.  I have fixed up all of these call sites,
and tested the resulting kernel on both an IQ80310 and a Shark.
Other portmasters should examine their pmap_map_entry() calls if
their new kernels fail.

Keep track of which kernel PTs are available during bootstrap,
and let pmap_map_chunk() lookup the correct one to use for the
current VA.  Eliminate the "l2table" argument to pmap_map_chunk().

Add a second L2 table for mapping kernel text/data/bss on the
IQ80310 (fixes booting kernels with ramdisks).

Always pass the L1 table to pmap_map_chunk().  This allows pmap_map_chunk()
to perform some error checking.

map_chunk() -> pmap_map_chunk(), and move it to pmap.c

map_pagetable() -> pmap_link_l2pt(), and move it to pmap.c

Collapse map_entry{,ro,nc}() into a single pmap_map_entry() that
takes a prot and a "cacheable" indicator.

Rename map_section() to pmap_map_section(), move it to pmap.c, and give it
an extra argument (prot - specifies protection of the mapping).

Sync w/ -current.

Overhaul of the ARM cache code.  This is mostly a simplification
pass.  Rather than providing a whole slew of cache operations that
aren't ever used, distill them down to some useful primitives:

	icache_sync_all         Synchronize I-cache
	icache_sync_range       Synchronize I-cache range

	dcache_wbinv_all        Write-back and Invalidate D-cache
	dcache_wbinv_range      Write-back and Invalidate D-cache range
	dcache_inv_range        Invalidate D-cache range
	dcache_wb_range         Write-back D-cache range

	idcache_wbinv_all       Write-back and Invalidate D-cache,
				Invalidate I-cache
	idcache_wbinv_range     Write-back and Invalidate D-cache,
				Invalidate I-cache range

Note: This does not yet include an overhaul of the actual asm files
that implement the primitives.  Instead, we've provided a safe default
for each CPU type, and the individual CPU types can now be optimized
one at a time.

Sync kqueue branch with -current.

Catch up to -current.

Use <arm/undefined.h> instead of <machine/undefined.h>.

No need to pull in <machine/pte.h> directly.

Sync the thorpej-mips-cache branch with -current.

file netwinder_machdep.c was added on branch nathanw_sa on 2002-01-08 00:26:49 +0000

Add some rudimentary support for ELF symbols in DDB on the ARM ports.
On platforms which load the kernel sans symbols directly from firmware
(possibly in e.g. S-Record format), call ddb_init() with empty arguments,
so that it will search any compiled in SYMTAB_SPACE.  On all other platforms,
if __ELF__, also call ddb_init() with empty arguments until ELF bootloaders
which pass symbol information are ready.

Remove unneeded declarations of the db_machine_init() function.  The
ARM ports are the only ones that actually have one, and it is about
to change.

Remove unnecessary prototypes for zero_page_read{only,write}().

Update the kqueue branch to HEAD.

Change <machine/irqhandler.h> to <machine/intr.h> since the latter always
includes the former and is a standard include file.

Switch netwinder to use a common conf.c for the arm ports.

update to -current

Allow ELF to be executed.  Remove any depenence on a.out header.  Instead
use etext & end to establish text and kernel size.

`response', not `responce'

`accessible' only has one `a'.

Typo police:  28285 -> 21285
Also garbage collect the old kernel VM map defines for footbridge.

Move the footbridge dir out of arm32 into arm.

Sync with HEAD.

Sync with HEAD

file netwinder_machdep.c was added on branch thorpej_scsipi on 2001-04-21 17:54:20 +0000

More changes to get the netwinder to multiuser.  Hack the initarm code
to reserve the first 2MB for the kernel.  Use the netwinder specific
files.  Add pci_attach_hook for init the pci devices.  Add and alternate
id for the PCI ISA bridge.

Add these to CVS so other folks can look at them and let me what
I'm screwing up.