Annotation of src/sys/arch/mvme68k/dev/sbic.c, Revision 1.22
1.22 ! drochner 1: /* $NetBSD: sbic.c,v 1.21 2003/05/03 18:10:52 wiz Exp $ */
1.1 chuck 2:
3: /*
4: * Changes Copyright (c) 1996 Steve Woodford
5: * Original Copyright (c) 1994 Christian E. Hopps
6: * Copyright (c) 1990 The Regents of the University of California.
7: * All rights reserved.
8: *
9: * This code is derived from software contributed to Berkeley by
10: * Van Jacobson of Lawrence Berkeley Laboratory.
11: *
12: * Redistribution and use in source and binary forms, with or without
13: * modification, are permitted provided that the following conditions
14: * are met:
15: * 1. Redistributions of source code must retain the above copyright
16: * notice, this list of conditions and the following disclaimer.
17: * 2. Redistributions in binary form must reproduce the above copyright
18: * notice, this list of conditions and the following disclaimer in the
19: * documentation and/or other materials provided with the distribution.
20: * 3. All advertising materials mentioning features or use of this software
21: * must display the following acknowledgement:
22: * This product includes software developed by the University of
23: * California, Berkeley and its contributors.
24: * 4. Neither the name of the University nor the names of its contributors
25: * may be used to endorse or promote products derived from this software
26: * without specific prior written permission.
27: *
28: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38: * SUCH DAMAGE.
39: *
40: * @(#)scsi.c 7.5 (Berkeley) 5/4/91
41: */
42:
43: /*
44: * Steve Woodford (SCW), Apr, 1996
45: * MVME147S WD33C93 Scsi Bus Interface Controller driver,
46: *
47: * Basically a de-loused and tidied up version of the Amiga AMD 33C93 driver.
48: *
49: * The original driver used features which required at least a WD33C93A
50: * chip. The '147 has the original WD33C93 chip (no 'A' suffix).
51: *
52: * This version of the driver is pretty well generic, so should work with
53: * any flavour of WD33C93 chip.
54: */
1.7 jonathan 55: #include "opt_ddb.h"
1.1 chuck 56:
57: #include <sys/param.h>
58: #include <sys/systm.h>
59: #include <sys/device.h>
60: #include <sys/kernel.h> /* For hz */
61: #include <sys/disklabel.h>
62: #include <sys/buf.h>
1.12 scw 63:
1.6 bouyer 64: #include <dev/scsipi/scsi_all.h>
65: #include <dev/scsipi/scsipi_all.h>
66: #include <dev/scsipi/scsiconf.h>
1.12 scw 67:
1.15 mrg 68: #include <uvm/uvm_extern.h>
1.12 scw 69:
1.1 chuck 70: #include <mvme68k/mvme68k/isr.h>
71: #include <mvme68k/dev/dmavar.h>
72: #include <mvme68k/dev/sbicreg.h>
73: #include <mvme68k/dev/sbicvar.h>
74:
75:
76: /*
77: * Since I can't find this in any other header files
78: */
79: #define SCSI_PHASE(reg) (reg&0x07)
80:
81: /*
82: * SCSI delays
83: * In u-seconds, primarily for state changes on the SPC.
84: */
85: #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */
86: #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */
87: #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */
88:
89: /*
90: * Convenience macro for waiting for a particular sbic event
91: */
92: #define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__)
93:
94: int sbicicmd __P((struct sbic_softc *, void *, int, void *, int));
1.6 bouyer 95: int sbicgo __P((struct sbic_softc *, struct scsipi_xfer *));
96: int sbicdmaok __P((struct sbic_softc *, struct scsipi_xfer *));
1.1 chuck 97: int sbicwait __P((sbic_regmap_p, u_char, int , int));
98: int sbiccheckdmap __P((void *, u_long, u_long));
99: u_char sbicselectbus __P((struct sbic_softc *));
100: int sbicxfout __P((sbic_regmap_p, int, void *));
101: int sbicxfin __P((sbic_regmap_p, int, void *));
102: int sbicfromscsiperiod __P((struct sbic_softc *, int));
103: int sbictoscsiperiod __P((struct sbic_softc *, int));
104: int sbicpoll __P((struct sbic_softc *));
105: int sbicnextstate __P((struct sbic_softc *, u_char, u_char));
106: int sbicmsgin __P((struct sbic_softc *));
107: int sbicabort __P((struct sbic_softc *, char *));
108: void sbicxfdone __P((struct sbic_softc *));
109: void sbicerror __P((struct sbic_softc *,u_char));
110: void sbicreset __P((struct sbic_softc *));
111: void sbic_scsidone __P((struct sbic_acb *, int));
112: void sbic_sched __P((struct sbic_softc *));
113: void sbic_save_ptrs __P((struct sbic_softc *));
114: void sbic_load_ptrs __P((struct sbic_softc *));
115:
116: /*
117: * Synch xfer parameters, and timing conversions
118: */
119: int sbic_min_period = SBIC_SYN_MIN_PERIOD; /* in cycles = f(ICLK,FSn) */
120: int sbic_max_offset = SBIC_SYN_MAX_OFFSET; /* pure number */
121: int sbic_cmd_wait = SBIC_CMD_WAIT;
122: int sbic_data_wait = SBIC_DATA_WAIT;
123: int sbic_init_wait = SBIC_INIT_WAIT;
124:
125: /*
126: * was broken before.. now if you want this you get it for all drives
127: * on sbic controllers.
128: */
129: u_char sbic_inhibit_sync[8];
130: int sbic_enable_reselect = 1; /* Allow Disconnect / Reselect */
131: int sbic_no_dma = 0; /* Use PIO transfers instead of DMA */
132: int sbic_parallel_operations = 1; /* Allow command queues */
133:
134: /*
135: * Some useful stuff for debugging purposes
136: */
137: #ifdef DEBUG
138: int sbicdma_ops = 0; /* total DMA operations */
139: int sbicdma_hits = 0; /* number of DMA chains that were contiguous */
140: int sbicdma_misses = 0; /* number of DMA chains that were not contiguous */
141: int sbicdma_saves = 0;
142:
1.5 christos 143: #define QPRINTF(a) if (sbic_debug > 1) printf a
1.1 chuck 144:
145: int sbic_debug = 0; /* Debug all chip related things */
146: int sync_debug = 0; /* Debug all Synchronous Scsi related things */
147: int reselect_debug = 0; /* Debug all reselection related things */
148: int data_pointer_debug = 0; /* Debug Data Pointer related things */
149:
150: void sbictimeout __P((struct sbic_softc *dev));
151:
152: #else
153: #define QPRINTF(a) /* */
154: #endif
155:
156:
157: /*
158: * default minphys routine for sbic based controllers
159: */
160: void
161: sbic_minphys(bp)
162: struct buf *bp;
163: {
164: /*
165: * No max transfer at this level.
166: */
167: minphys(bp);
168: }
169:
170:
171: /*
172: * Save DMA pointers. Take into account partial transfer. Shut down DMA.
173: */
174: void
175: sbic_save_ptrs(dev)
176: struct sbic_softc *dev;
177: {
178: sbic_regmap_p regs;
179: struct sbic_acb* acb;
180: int count,
181: asr,
182: s;
183:
184: /*
185: * Only need to save pointers if DMA was active...
186: */
187: if ( dev->sc_cur == NULL || (dev->sc_flags & SBICF_INDMA) == 0 )
188: return;
189:
190: regs = dev->sc_sbicp;
191:
192: s = splbio();
193:
194: /*
195: * Wait until WD chip is idle
196: */
197: do {
198: GET_SBIC_asr(regs, asr);
199: if( asr & SBIC_ASR_DBR ) {
1.5 christos 200: printf("sbic_save_ptrs: asr %02x canceled!\n", asr);
1.1 chuck 201: splx(s);
202: return;
203: }
204: } while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) );
205:
206:
207: /*
208: * Save important state.
209: * must be done before dmastop
210: */
211: acb = dev->sc_nexus;
212: acb->sc_dmacmd = dev->sc_dmacmd;
213:
214: /*
215: * Fetch the residual count
216: */
217: SBIC_TC_GET(regs, count);
218:
219: /*
220: * Shut down DMA
221: */
222: dev->sc_dmastop(dev);
223:
224: /*
225: * No longer in DMA
226: */
227: dev->sc_flags &= ~SBICF_INDMA;
228:
229: /*
230: * Ensure the WD chip is back in polled I/O mode, with nothing to
231: * transfer.
232: */
233: SBIC_TC_PUT(regs, 0);
234: SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI);
235:
236: /*
237: * Update current count...
238: */
239: acb->sc_tcnt = count;
240:
241: /*
242: * Work out how many bytes were actually transferred
243: */
244: count = dev->sc_tcnt - count;
245: dev->sc_tcnt = acb->sc_tcnt;
246:
247: /*
248: * Fixup partial xfers
249: */
250: acb->sc_kv.dc_addr += count;
251: acb->sc_kv.dc_count -= count;
252: acb->sc_pa.dc_addr += count;
253: acb->sc_pa.dc_count -= count >> 1;
254:
255: #ifdef DEBUG
256: if ( data_pointer_debug )
1.12 scw 257: printf("save at (%p,%x):%x\n",
1.1 chuck 258: dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count);
259: sbicdma_saves++;
260: #endif
261:
262: splx(s);
263: }
264:
265:
266: /*
267: * DOES NOT RESTART DMA!!!
268: */
269: void
270: sbic_load_ptrs(dev)
271: struct sbic_softc *dev;
272: {
273: struct sbic_acb *acb = dev->sc_nexus;
274: int s;
275:
276: if ( acb->sc_kv.dc_count == 0 ) {
277: /*
278: * No data to xfer
279: */
280: return;
281: }
282:
283: s = splbio();
284:
285: /*
286: * Reset the Scatter-Gather chain
287: */
288: dev->sc_last = dev->sc_cur = &acb->sc_pa;
289:
290: /*
291: * Restore the Transfer Count and DMA specific data
292: */
293: dev->sc_tcnt = acb->sc_tcnt;
294: dev->sc_dmacmd = acb->sc_dmacmd;
295:
296: #ifdef DEBUG
297: sbicdma_ops++;
298: #endif
299:
300: /*
301: * Need to fixup new segment?
302: */
303: if ( dev->sc_tcnt == 0 ) {
304: /*
305: * sc_tcnt == 0 implies end of segment
306: */
307: char *vaddr, *paddr;
308: int count;
309:
310: /*
311: * do kvm to pa mappings
312: */
313: vaddr = acb->sc_kv.dc_addr;
1.12 scw 314: paddr = acb->sc_pa.dc_addr = (char *) kvtop((caddr_t)vaddr);
1.1 chuck 315:
1.20 thorpej 316: for (count = (PAGE_SIZE - ((int)vaddr & PGOFSET));
1.1 chuck 317: count < acb->sc_kv.dc_count &&
1.12 scw 318: (char*)kvtop((caddr_t)(vaddr + count + 4)) == paddr + count + 4;
1.20 thorpej 319: count += PAGE_SIZE)
1.1 chuck 320: ; /* Do nothing */
321:
322: /*
323: * If it's all contiguous...
324: */
325: if ( count > acb->sc_kv.dc_count ) {
326: count = acb->sc_kv.dc_count;
327: #ifdef DEBUG
328: sbicdma_hits++;
329: #endif
330: }
331: #ifdef DEBUG
332: else
333: sbicdma_misses++;
334: #endif
335:
336: acb->sc_tcnt = count;
337: acb->sc_pa.dc_count = count >> 1;
338:
339: #ifdef DEBUG
340: if ( data_pointer_debug )
1.12 scw 341: printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", acb->sc_kv.dc_addr,
1.1 chuck 342: acb->sc_kv.dc_count,
343: acb->sc_pa.dc_addr,
344: acb->sc_tcnt);
345: #endif
346:
347: }
348:
349: splx(s);
350: }
351:
352: /*
353: * used by specific sbic controller
354: *
355: * it appears that the higher level code does nothing with LUN's
356: * so I will too. I could plug it in, however so could they
1.6 bouyer 357: * in scsi_scsipi_cmd().
1.1 chuck 358: */
1.16 bouyer 359: void
360: sbic_scsi_request(chan, req, arg)
361: struct scsipi_channel *chan;
362: scsipi_adapter_req_t req;
363: void *arg;
364: {
1.6 bouyer 365: struct scsipi_xfer *xs;
1.16 bouyer 366: struct scsipi_periph *periph;
367: struct sbic_softc *dev = (void *)chan->chan_adapter->adapt_dev;
1.1 chuck 368: struct sbic_acb *acb;
1.16 bouyer 369: int flags, s;
1.1 chuck 370:
1.16 bouyer 371: switch (req) {
372: case ADAPTER_REQ_RUN_XFER:
373: xs = arg;
374: periph = xs->xs_periph;
375: flags = xs->xs_control;
1.1 chuck 376:
1.16 bouyer 377: if ( flags & XS_CTL_DATA_UIO )
378: panic("sbic: scsi data uio requested");
1.1 chuck 379:
1.16 bouyer 380: if ( dev->sc_nexus && (flags & XS_CTL_POLL) )
381: panic("sbic_scsicmd: busy");
1.1 chuck 382:
1.16 bouyer 383: s = splbio();
1.1 chuck 384:
1.16 bouyer 385: if ( (acb = dev->free_list.tqh_first) != NULL )
386: TAILQ_REMOVE(&dev->free_list, acb, chain);
1.1 chuck 387:
1.16 bouyer 388: splx(s);
1.1 chuck 389:
1.16 bouyer 390: if ( acb == NULL ) {
1.1 chuck 391: #ifdef DEBUG
1.16 bouyer 392: printf("sbic_scsicmd: unable to queue request for target %d\n",
393: periph->periph_target);
1.1 chuck 394: #ifdef DDB
1.16 bouyer 395: Debugger();
1.1 chuck 396: #endif
397: #endif
1.16 bouyer 398: xs->error = XS_RESOURCE_SHORTAGE;
399: scsipi_done(xs);
400: return;
401: }
402:
403: if ( flags & XS_CTL_DATA_IN )
404: acb->flags = ACB_ACTIVE | ACB_DATAIN;
405: else
406: acb->flags = ACB_ACTIVE;
1.1 chuck 407:
1.16 bouyer 408: acb->xs = xs;
409: acb->clen = xs->cmdlen;
410: acb->sc_kv.dc_addr = xs->data;
411: acb->sc_kv.dc_count = xs->datalen;
412: acb->pa_addr = xs->data ? (char *)kvtop((caddr_t)xs->data) : 0;
1.17 scw 413: memcpy(&acb->cmd, xs->cmd, xs->cmdlen);
1.1 chuck 414:
1.16 bouyer 415: if ( flags & XS_CTL_POLL ) {
416: /*
417: * This has major side effects -- it locks up the machine
418: */
419: int stat;
1.1 chuck 420:
1.16 bouyer 421: s = splbio();
1.1 chuck 422:
1.16 bouyer 423: dev->sc_flags |= SBICF_ICMD;
1.1 chuck 424:
1.16 bouyer 425: do {
426: /*
427: * If we already had a nexus, while away the time until idle...
428: * This is likely only to happen if a reselection occurs between
429: * here and our earlier check for ICMD && sc_nexus (which would
430: * have resulted in a panic() had it been true).
431: */
432: while ( dev->sc_nexus )
433: sbicpoll(dev);
1.1 chuck 434:
1.16 bouyer 435: /*
436: * Fix up the new nexus
437: */
438: dev->sc_nexus = acb;
439: dev->sc_xs = xs;
440: dev->target = periph->periph_target;
441: dev->lun = periph->periph_lun;
1.1 chuck 442:
1.16 bouyer 443: stat = sbicicmd(dev, &acb->cmd, acb->clen,
444: acb->sc_kv.dc_addr, acb->sc_kv.dc_count);
1.1 chuck 445:
1.16 bouyer 446: } while ( dev->sc_nexus != acb );
1.1 chuck 447:
1.16 bouyer 448: sbic_scsidone(acb, stat);
1.1 chuck 449:
1.16 bouyer 450: splx(s);
1.1 chuck 451:
1.16 bouyer 452: return;
453: }
1.1 chuck 454:
1.16 bouyer 455: s = splbio();
456: TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain);
1.1 chuck 457:
1.16 bouyer 458: /*
459: * If nothing is active, try to start it now.
460: */
461: if ( dev->sc_nexus == NULL )
462: sbic_sched(dev);
1.1 chuck 463:
1.16 bouyer 464: splx(s);
1.1 chuck 465:
1.16 bouyer 466: return;
1.1 chuck 467:
1.16 bouyer 468: case ADAPTER_REQ_GROW_RESOURCES:
469: /* XXX Not supported. */
470: return;
471:
472: case ADAPTER_REQ_SET_XFER_MODE:
473: /* XXX Not supported. */
474: return;
475: }
1.1 chuck 476:
477: }
478:
479: /*
480: * attempt to start the next available command
481: */
482: void
483: sbic_sched(dev)
484: struct sbic_softc *dev;
485: {
1.6 bouyer 486: struct scsipi_xfer *xs;
1.16 bouyer 487: struct scsipi_periph *periph = NULL; /* Gag the compiler */
1.1 chuck 488: struct sbic_acb *acb;
489: int flags,
490: stat;
491:
492: /*
493: * XXXSCW
494: * I'll keep this test here, even though I can't see any obvious way
495: * in which sbic_sched() could be called with sc_nexus non NULL
496: */
497: if ( dev->sc_nexus )
498: return; /* a command is current active */
499:
500: /*
501: * Loop through the ready list looking for work to do...
502: */
503: for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) {
504: int i, j;
505:
1.16 bouyer 506: periph = acb->xs->xs_periph;
507: i = periph->periph_target;
508: j = 1 << periph->periph_lun;
1.1 chuck 509:
510: /*
511: * We've found a potential command, but is the target/lun busy?
512: */
513: if ( (dev->sc_tinfo[i].lubusy & j) == 0 ) {
514: /*
515: * Nope, it's not busy, so we can use it.
516: */
517: dev->sc_tinfo[i].lubusy |= j;
518: TAILQ_REMOVE(&dev->ready_list, acb, chain);
519: dev->sc_nexus = acb;
520: acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */
521: break;
522: }
523: }
524:
525: if ( acb == NULL ) {
526: QPRINTF(("sbicsched: no work\n"));
527: return; /* did not find an available command */
528: }
529:
530: #ifdef DEBUG
531: if ( data_pointer_debug > 1 )
1.16 bouyer 532: printf("sbic_sched(%d,%d)\n", periph->periph_target,
533: periph->periph_lun);
1.1 chuck 534: #endif
535:
536: dev->sc_xs = xs = acb->xs;
1.10 thorpej 537: flags = xs->xs_control;
1.1 chuck 538:
1.10 thorpej 539: if ( flags & XS_CTL_RESET )
1.1 chuck 540: sbicreset(dev);
541:
542: dev->sc_stat[0] = -1;
1.16 bouyer 543: dev->target = periph->periph_target;
544: dev->lun = periph->periph_lun;
1.1 chuck 545:
1.10 thorpej 546: if ( flags & XS_CTL_POLL || (!sbic_parallel_operations &&
1.1 chuck 547: (sbicdmaok(dev, xs) == 0)) )
548: stat = sbicicmd(dev, &acb->cmd, acb->clen,
549: acb->sc_kv.dc_addr, acb->sc_kv.dc_count);
550: else
1.11 scw 551: if ( sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT )
1.1 chuck 552: return;
553: else
554: stat = dev->sc_stat[0];
555:
556: sbic_scsidone(acb, stat);
557: }
558:
559: void
560: sbic_scsidone(acb, stat)
561: struct sbic_acb *acb;
562: int stat;
563: {
1.6 bouyer 564: struct scsipi_xfer *xs = acb->xs;
1.16 bouyer 565: struct scsipi_periph *periph = xs->xs_periph;
566: struct sbic_softc *dev = (void *)periph->periph_channel->chan_adapter->adapt_dev;
1.1 chuck 567: int dosched = 0;
568:
569: #ifdef DIAGNOSTIC
570: if ( acb == NULL || xs == NULL ) {
1.6 bouyer 571: printf("sbic_scsidone -- (%d,%d) no scsipi_xfer\n", dev->target, dev->lun);
1.1 chuck 572: #ifdef DDB
573: Debugger();
574: #endif
575: return;
576: }
577: #endif
578:
579:
580: #ifdef DEBUG
581: if ( data_pointer_debug > 1 )
1.16 bouyer 582: printf("scsidone: (%d,%d)->(%d,%d)%02x\n", periph->periph_target,
583: periph->periph_lun,
1.1 chuck 584: dev->target, dev->lun, stat);
585:
1.16 bouyer 586: if ( xs->xs_periph->periph_target == dev->sc_channel.chan_id)
1.1 chuck 587: panic("target == hostid");
588: #endif
589:
1.16 bouyer 590: xs->status = stat;
591: xs->resid = 0; /* XXXX */
592: if ( xs->error == XS_NOERROR) {
593: if ( stat == SCSI_CHECK || stat == SCSI_BUSY)
594: xs->error = XS_BUSY;
1.1 chuck 595: }
596:
597:
598: /*
599: * Remove the ACB from whatever queue it's on. We have to do a bit of
600: * a hack to figure out which queue it's on. Note that it is *not*
601: * necessary to cdr down the ready queue, but we must cdr down the
602: * nexus queue and see if it's there, so we can mark the unit as no
603: * longer busy. This code is sickening, but it works.
604: */
605: if ( acb == dev->sc_nexus ) {
606:
607: dev->sc_nexus = NULL;
608: dev->sc_xs = NULL;
609:
1.16 bouyer 610: dev->sc_tinfo[periph->periph_target].lubusy &=
611: ~(1 << periph->periph_lun);
1.1 chuck 612:
613: if ( dev->ready_list.tqh_first )
614: dosched = 1; /* start next command */
615:
616: } else
617: if ( dev->ready_list.tqh_last == &acb->chain.tqe_next ) {
618:
619: TAILQ_REMOVE(&dev->ready_list, acb, chain);
620:
621: } else {
622:
1.8 scw 623: struct sbic_acb *a;
1.1 chuck 624:
625: for (a = dev->nexus_list.tqh_first; a; a = a->chain.tqe_next) {
626: if ( a == acb ) {
627: TAILQ_REMOVE(&dev->nexus_list, acb, chain);
1.16 bouyer 628: dev->sc_tinfo[periph->periph_target].lubusy &=
629: ~(1 << periph->periph_lun);
1.1 chuck 630: break;
631: }
632: }
633:
634: if ( a )
635: ;
636: else if ( acb->chain.tqe_next ) {
637: TAILQ_REMOVE(&dev->ready_list, acb, chain);
638: } else {
1.5 christos 639: printf("%s: can't find matching acb\n", dev->sc_dev.dv_xname);
1.1 chuck 640: #ifdef DDB
641: Debugger();
642: #endif
643: }
644: }
645:
646: /*
647: * Put it on the free list.
648: */
649: acb->flags = ACB_FREE;
650: TAILQ_INSERT_HEAD(&dev->free_list, acb, chain);
651:
1.16 bouyer 652: dev->sc_tinfo[periph->periph_target].cmds++;
1.1 chuck 653:
1.6 bouyer 654: scsipi_done(xs);
1.1 chuck 655:
656: if ( dosched )
657: sbic_sched(dev);
658: }
659:
660: int
661: sbicdmaok(dev, xs)
662: struct sbic_softc *dev;
1.6 bouyer 663: struct scsipi_xfer *xs;
1.1 chuck 664: {
1.11 scw 665: if ( sbic_no_dma || xs->datalen == 0 ||
666: xs->datalen & 0x03 || (int)xs->data & 0x03)
1.1 chuck 667: return(0);
668:
669: /*
1.21 wiz 670: * controller supports DMA to any addresses?
1.1 chuck 671: */
672: if ( (dev->sc_flags & SBICF_BADDMA) == 0 )
673: return(1);
674:
675: /*
1.21 wiz 676: * this address is ok for DMA?
1.1 chuck 677: */
678: if ( sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0 )
679: return(1);
680:
681: return(0);
682: }
683:
684: int
685: sbicwait(regs, until, timeo, line)
686: sbic_regmap_p regs;
687: u_char until;
688: int timeo;
689: int line;
690: {
691: u_char val;
692:
693: if ( timeo == 0 )
694: timeo = 1000000; /* some large value.. */
695:
696: GET_SBIC_asr(regs, val);
697:
698: while ( (val & until) == 0 ) {
699:
700: if ( timeo-- == 0 ) {
701: int csr;
702: GET_SBIC_csr(regs, csr);
1.5 christos 703: printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", line, val, csr);
1.1 chuck 704: #if defined(DDB) && defined(DEBUG)
705: Debugger();
706: #endif
707: return(val); /* Maybe I should abort */
708: break;
709: }
710:
711: DELAY(1);
712: GET_SBIC_asr(regs, val);
713: }
714:
715: return(val);
716: }
717:
718: int
719: sbicabort(dev, where)
720: struct sbic_softc *dev;
721: char *where;
722: {
723: sbic_regmap_p regs = dev->sc_sbicp;
724: u_char csr,
725: asr;
726:
727: GET_SBIC_asr(regs, asr);
728: GET_SBIC_csr(regs, csr);
729:
1.5 christos 730: printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n",
1.1 chuck 731: dev->sc_dev.dv_xname, where, csr, asr);
732:
733: /*
734: * Clean up chip itself
735: */
736: if ( dev->sc_flags & SBICF_SELECTED ) {
737:
738: while ( asr & SBIC_ASR_DBR ) {
739: /*
740: * sbic is jammed w/data. need to clear it
741: * But we don't know what direction it needs to go
742: */
743: GET_SBIC_data(regs, asr);
1.5 christos 744: printf("%s: abort %s: clearing data buffer 0x%02x\n",
1.1 chuck 745: dev->sc_dev.dv_xname, where, asr);
746: GET_SBIC_asr(regs, asr);
747: if ( asr & SBIC_ASR_DBR ) /* Not the read direction, then */
748: SET_SBIC_data(regs, asr);
749: GET_SBIC_asr(regs, asr);
750: }
751:
752: WAIT_CIP(regs);
753:
1.5 christos 754: printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname);
1.1 chuck 755: SET_SBIC_cmd(regs, SBIC_CMD_ABORT);
756: WAIT_CIP(regs);
757:
758: GET_SBIC_asr(regs, asr);
759:
760: if ( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI) ) {
761: /*
762: * ok, get more drastic..
763: */
1.5 christos 764: printf("%s: sbicabort - asr %x, trying to reset\n",
1.1 chuck 765: dev->sc_dev.dv_xname, asr);
766: sbicreset(dev);
767: dev->sc_flags &= ~SBICF_SELECTED;
1.2 chuck 768: return SBIC_STATE_ERROR;
1.1 chuck 769: }
770:
1.5 christos 771: printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname);
1.1 chuck 772: SET_SBIC_cmd(regs, SBIC_CMD_DISC);
773:
774: do {
775: SBIC_WAIT (regs, SBIC_ASR_INT, 0);
776: GET_SBIC_asr(regs, asr);
777: GET_SBIC_csr (regs, csr);
778: QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr));
779: } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) &&
780: (csr != SBIC_CSR_CMD_INVALID) );
781:
782: /*
783: * lets just hope it worked..
784: */
785: dev->sc_flags &= ~SBICF_SELECTED;
786: }
787:
1.2 chuck 788: return SBIC_STATE_ERROR;
1.1 chuck 789: }
790:
791:
792: /*
793: * Initialize driver-private structures
794: */
795: void
796: sbicinit(dev)
797: struct sbic_softc *dev;
798: {
799: u_int i;
800:
801: if ( (dev->sc_flags & SBICF_ALIVE) == 0 ) {
802:
803: struct sbic_acb *acb;
804:
805: TAILQ_INIT(&dev->ready_list);
806: TAILQ_INIT(&dev->nexus_list);
807: TAILQ_INIT(&dev->free_list);
1.13 thorpej 808: callout_init(&dev->sc_timo_ch);
1.1 chuck 809:
810: dev->sc_nexus = NULL;
811: dev->sc_xs = NULL;
812:
813: acb = dev->sc_acb;
1.17 scw 814: memset(acb, 0, sizeof(dev->sc_acb));
1.1 chuck 815:
816: for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) {
817: TAILQ_INSERT_TAIL(&dev->free_list, acb, chain);
818: acb++;
819: }
820:
1.17 scw 821: memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo));
1.1 chuck 822:
823: #ifdef DEBUG
824: /*
825: * make sure timeout is really not needed
826: */
1.13 thorpej 827: callout_reset(&dev->sc_timo_ch, 30 * hz, (void *)sbictimeout, dev);
1.1 chuck 828: #endif
829:
830: } else
831: panic("sbic: reinitializing driver!");
832:
833: dev->sc_flags |= SBICF_ALIVE;
834: dev->sc_flags &= ~SBICF_SELECTED;
835:
836: /*
837: * initialize inhibit array
1.9 scw 838: * Never enable Sync, since it just doesn't work on mvme147 :(
1.1 chuck 839: */
1.9 scw 840: for (i = 0; i < 8; ++i)
841: sbic_inhibit_sync[i] = 1;
1.1 chuck 842:
843: sbicreset(dev);
844: }
845:
846: void
847: sbicreset(dev)
848: struct sbic_softc *dev;
849: {
850: sbic_regmap_p regs = dev->sc_sbicp;
851: u_int my_id,
852: s;
853: u_char csr;
854:
855: s = splbio();
856:
1.16 bouyer 857: my_id = dev->sc_channel.chan_id & SBIC_ID_MASK;
1.1 chuck 858:
859: if (dev->sc_clkfreq < 110)
860: my_id |= SBIC_ID_FS_8_10;
861: else if (dev->sc_clkfreq < 160)
862: my_id |= SBIC_ID_FS_12_15;
863: else if (dev->sc_clkfreq < 210)
864: my_id |= SBIC_ID_FS_16_20;
865:
866: SET_SBIC_myid(regs, my_id);
867:
868: /*
869: * Reset the chip
870: */
871: SET_SBIC_cmd(regs, SBIC_CMD_RESET);
872: DELAY(25);
873:
874: SBIC_WAIT(regs, SBIC_ASR_INT, 0);
875: GET_SBIC_csr(regs, csr); /* clears interrupt also */
876:
877: /*
878: * Set up various chip parameters
879: */
880: SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI);
881:
882: /*
883: * don't allow Selection (SBIC_RID_ES)
884: * until we can handle target mode!!
885: */
886: SET_SBIC_rselid(regs, SBIC_RID_ER);
887:
888: /*
889: * Asynchronous for now
890: */
891: SET_SBIC_syn(regs, 0);
892:
893: /*
894: * Anything else was zeroed by reset
895: */
896: splx(s);
897:
898: dev->sc_flags &= ~SBICF_SELECTED;
899: }
900:
901: void
902: sbicerror(dev, csr)
903: struct sbic_softc *dev;
904: u_char csr;
905: {
1.6 bouyer 906: struct scsipi_xfer *xs = dev->sc_xs;
1.1 chuck 907:
908: #ifdef DIAGNOSTIC
909: if ( xs == NULL )
910: panic("sbicerror: dev->sc_xs == NULL");
911: #endif
912:
1.10 thorpej 913: if ( xs->xs_control & XS_CTL_SILENT )
1.1 chuck 914: return;
915:
1.5 christos 916: printf("%s: csr == 0x%02x\n", dev->sc_dev.dv_xname, csr);
1.1 chuck 917: }
918:
919: /*
920: * select the bus, return when selected or error.
921: *
922: * Returns the current CSR following selection and optionally MSG out phase.
923: * i.e. the returned CSR *should* indicate CMD phase...
924: * If the return value is 0, some error happened.
925: */
926: u_char
927: sbicselectbus(dev)
928: struct sbic_softc *dev;
929: {
930: sbic_regmap_p regs = dev->sc_sbicp;
931: u_char target = dev->target,
932: lun = dev->lun,
933: asr,
934: csr,
935: id;
936:
937: /*
938: * if we're already selected, return (XXXX panic maybe?)
939: */
940: if ( dev->sc_flags & SBICF_SELECTED )
941: return(0);
942:
943: QPRINTF(("sbicselectbus %d: ", target));
944:
945: /*
946: * issue select
947: */
948: SET_SBIC_selid(regs, target);
949: SET_SBIC_timeo(regs, SBIC_TIMEOUT(250, dev->sc_clkfreq));
950:
951: GET_SBIC_asr(regs, asr);
952:
953: if ( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) {
954: /*
955: * This means we got ourselves reselected upon
956: */
957: QPRINTF(("WD busy (reselect?)\n"));
958: return 0;
959: }
960:
961: SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN);
962:
963: /*
1.18 wiz 964: * wait for select (merged from separate function may need
1.1 chuck 965: * cleanup)
966: */
967: WAIT_CIP(regs);
968:
969: do {
970:
971: asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0);
972:
973: if ( asr & SBIC_ASR_LCI ) {
974: QPRINTF(("late LCI: asr %02x\n", asr));
975: return 0;
976: }
977:
978: /*
979: * Clear interrupt
980: */
981: GET_SBIC_csr (regs, csr);
982:
983: QPRINTF(("%02x ", csr));
984:
985: /*
986: * Reselected from under our feet?
987: */
988: if ( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY ) {
989: QPRINTF(("got reselected, asr %02x\n", asr));
990: /*
991: * We need to handle this now so we don't lock up later
992: */
993: sbicnextstate(dev, csr, asr);
994:
995: return 0;
996: }
997:
998: /*
999: * Whoops!
1000: */
1001: if ( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN ) {
1002: panic("sbicselectbus: target issued select!");
1003: return 0;
1004: }
1005:
1006: } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) &&
1007: csr != (SBIC_CSR_MIS_2 | CMD_PHASE) &&
1008: csr != SBIC_CSR_SEL_TIMEO);
1009:
1010: /*
1011: * Anyone at home?
1012: */
1013: if ( csr == SBIC_CSR_SEL_TIMEO ) {
1014: dev->sc_xs->error = XS_SELTIMEOUT;
1015: QPRINTF(("Selection Timeout\n"));
1016: return 0;
1017: }
1018:
1019: QPRINTF(("Selection Complete\n"));
1020:
1021: /*
1022: * Assume we're now selected
1023: */
1024: GET_SBIC_selid(regs, id);
1025: dev->target = id;
1026: dev->lun = lun;
1027: dev->sc_flags |= SBICF_SELECTED;
1028:
1029: /*
1030: * Enable (or not) reselection
1031: * XXXSCW This is probably not necessary since we don't use use the
1.2 chuck 1032: * Select-and-Xfer-with-ATN command to initiate a selection...
1.1 chuck 1033: */
1034: if ( !sbic_enable_reselect && dev->nexus_list.tqh_first == NULL)
1035: SET_SBIC_rselid (regs, 0);
1036: else
1037: SET_SBIC_rselid (regs, SBIC_RID_ER);
1038:
1039: /*
1040: * We only really need to do anything when the target goes to MSG out
1041: * If the device ignored ATN, it's probably old and brain-dead,
1042: * but we'll try to support it anyhow.
1043: * If it doesn't support message out, it definately doesn't
1044: * support synchronous transfers, so no point in even asking...
1045: */
1046: if ( csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) ) {
1047: /*
1048: * Send identify message (SCSI-2 requires an identify msg)
1049: */
1050: if ( sbic_inhibit_sync[id] && dev->sc_sync[id].state == SYNC_START ) {
1051: /*
1052: * Handle drives that don't want to be asked
1053: * whether to go sync at all.
1054: */
1055: dev->sc_sync[id].offset = 0;
1056: dev->sc_sync[id].period = sbic_min_period;
1057: dev->sc_sync[id].state = SYNC_DONE;
1058: }
1059:
1060: /*
1061: * Do we need to negotiate Synchronous Xfers for this target?
1062: */
1063: if ( dev->sc_sync[id].state != SYNC_START ) {
1064: /*
1065: * Nope, we've already negotiated.
1066: * Now see if we should allow the target to disconnect/reselect...
1067: */
1.10 thorpej 1068: if ( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD ||
1.1 chuck 1069: !sbic_enable_reselect )
1070: SEND_BYTE (regs, MSG_IDENTIFY | lun);
1071: else
1072: SEND_BYTE (regs, MSG_IDENTIFY_DR | lun);
1073:
1074: } else {
1075: /*
1076: * try to initiate a sync transfer.
1077: * So compose the sync message we're going
1078: * to send to the target
1079: */
1080: #ifdef DEBUG
1081: if ( sync_debug )
1.5 christos 1082: printf("\nSending sync request to target %d ... ", id);
1.1 chuck 1083: #endif
1084: /*
1085: * setup scsi message sync message request
1086: */
1087: dev->sc_msg[0] = MSG_IDENTIFY | lun;
1088: dev->sc_msg[1] = MSG_EXT_MESSAGE;
1089: dev->sc_msg[2] = 3;
1090: dev->sc_msg[3] = MSG_SYNC_REQ;
1091: dev->sc_msg[4] = sbictoscsiperiod(dev, sbic_min_period);
1092: dev->sc_msg[5] = sbic_max_offset;
1093:
1094: sbicxfout(regs, 6, dev->sc_msg);
1095:
1096: dev->sc_sync[id].state = SYNC_SENT;
1097: #ifdef DEBUG
1098: if ( sync_debug )
1.5 christos 1099: printf ("sent\n");
1.1 chuck 1100: #endif
1101: }
1102:
1103: /*
1104: * There's one interrupt still to come: the change to CMD phase...
1105: */
1106: SBIC_WAIT(regs, SBIC_ASR_INT , 0);
1107: GET_SBIC_csr(regs, csr);
1108: }
1109:
1.2 chuck 1110: /*
1111: * set sync or async
1112: */
1113: if ( dev->sc_sync[target].state == SYNC_DONE ) {
1114: #ifdef DEBUG
1115: if ( sync_debug )
1.5 christos 1116: printf("select(%d): sync reg = 0x%02x\n", target,
1.2 chuck 1117: SBIC_SYN(dev->sc_sync[target].offset,
1118: dev->sc_sync[target].period));
1119: #endif
1120: SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset,
1121: dev->sc_sync[target].period));
1122: } else {
1123: #ifdef DEBUG
1124: if ( sync_debug )
1.5 christos 1125: printf("select(%d): sync reg = 0x%02x\n", target,
1.2 chuck 1126: SBIC_SYN(0,sbic_min_period));
1127: #endif
1128: SET_SBIC_syn(regs, SBIC_SYN(0, sbic_min_period));
1129: }
1130:
1.1 chuck 1131: return csr;
1132: }
1133:
1134: /*
1.2 chuck 1135: * Information Transfer *to* a Scsi Target.
1136: *
1137: * Note: Don't expect there to be an interrupt immediately after all
1138: * the data is transferred out. The WD spec sheet says that the Transfer-
1139: * Info command for non-MSG_IN phases only completes when the target
1140: * next asserts 'REQ'. That is, when the SCSI bus changes to a new state.
1141: *
1142: * This can have a nasty effect on commands which take a relatively long
1143: * time to complete, for example a START/STOP unit command may remain in
1144: * CMD phase until the disk has spun up. Only then will the target change
1145: * to STATUS phase. This is really only a problem for immediate commands
1146: * since we don't allow disconnection for them (yet).
1.1 chuck 1147: */
1148: int
1149: sbicxfout(regs, len, bp)
1150: sbic_regmap_p regs;
1151: int len;
1152: void *bp;
1153: {
1154: int wait = sbic_data_wait;
1155: u_char asr,
1156: *buf = bp;
1157:
1158: QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x "
1159: "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2],
1160: buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9]));
1161:
1162: /*
1163: * sigh.. WD-PROTO strikes again.. sending the command in one go
1164: * causes the chip to lock up if talking to certain (misbehaving?)
1165: * targets. Anyway, this procedure should work for all targets, but
1166: * it's slightly slower due to the overhead
1167: */
1168: WAIT_CIP (regs);
1169:
1170: SBIC_TC_PUT (regs, 0);
1171: SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI);
1172: SBIC_TC_PUT (regs, (unsigned)len);
1173: SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO);
1174:
1175: /*
1176: * Loop for each byte transferred
1177: */
1178: do {
1179:
1180: GET_SBIC_asr (regs, asr);
1181:
1182: if ( asr & SBIC_ASR_DBR ) {
1183: if ( len ) {
1184: SET_SBIC_data (regs, *buf);
1185: buf++;
1186: len--;
1187: } else {
1188: SET_SBIC_data (regs, 0);
1189: }
1190: wait = sbic_data_wait;
1191: }
1192:
1.2 chuck 1193: } while ( len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0 );
1.1 chuck 1194:
1195: #ifdef DEBUG
1196: QPRINTF(("sbicxfout done: %d bytes remaining (wait:%d)\n", len, wait));
1197: #endif
1198:
1199: /*
1.2 chuck 1200: * Normally, an interrupt will be pending when this routing returns.
1.1 chuck 1201: */
1202: return(len);
1203: }
1204:
1205: /*
1206: * Information Transfer *from* a Scsi Target
1207: * returns # bytes left to read
1208: */
1209: int
1210: sbicxfin(regs, len, bp)
1211: sbic_regmap_p regs;
1212: int len;
1213: void *bp;
1214: {
1215: int wait = sbic_data_wait;
1216: u_char *buf = bp;
1217: u_char asr;
1218: #ifdef DEBUG
1219: u_char *obp = bp;
1220: #endif
1221:
1222: WAIT_CIP (regs);
1223:
1224: SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI);
1225: SBIC_TC_PUT (regs, (unsigned)len);
1226: SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO);
1227:
1228: /*
1229: * Loop for each byte transferred
1230: */
1231: do {
1232:
1233: GET_SBIC_asr (regs, asr);
1234:
1235: if ( asr & SBIC_ASR_DBR ) {
1236: if ( len ) {
1237: GET_SBIC_data (regs, *buf);
1238: buf++;
1239: len--;
1240: } else {
1241: u_char foo;
1242: GET_SBIC_data (regs, foo);
1243: }
1244: wait = sbic_data_wait;
1245: }
1246:
1247: } while ( (asr & SBIC_ASR_INT) == 0 && wait-- > 0 );
1248:
1249: QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x "
1250: "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2],
1251: obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9]));
1252:
1253: SBIC_TC_PUT (regs, 0);
1254:
1255: /*
1256: * this leaves with one csr to be read
1257: */
1258: return len;
1259: }
1260:
1261: /*
1262: * SCSI 'immediate' command: issue a command to some SCSI device
1263: * and get back an 'immediate' response (i.e., do programmed xfer
1264: * to get the response data). 'cbuf' is a buffer containing a scsi
1265: * command of length clen bytes. 'buf' is a buffer of length 'len'
1266: * bytes for data. The transfer direction is determined by the device
1267: * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the
1268: * command must supply no data.
1.2 chuck 1269: *
1270: * Note that although this routine looks like it can handle disconnect/
1271: * reselect, the fact is that it can't. There is still some work to be
1272: * done to clean this lot up.
1.1 chuck 1273: */
1274: int
1275: sbicicmd(dev, cbuf, clen, buf, len)
1276: struct sbic_softc *dev;
1277: void *cbuf,
1278: *buf;
1279: int clen,
1280: len;
1281: {
1282: sbic_regmap_p regs = dev->sc_sbicp;
1283: struct sbic_acb *acb = dev->sc_nexus;
1284: u_char csr,
1285: asr;
1.2 chuck 1286: int still_busy = SBIC_STATE_RUNNING;
1.1 chuck 1287:
1288: /*
1289: * Make sure pointers are OK
1290: */
1291: dev->sc_last = dev->sc_cur = &acb->sc_pa;
1292: dev->sc_tcnt = acb->sc_tcnt = 0;
1293:
1294: acb->sc_dmacmd = 0;
1295: acb->sc_pa.dc_count = 0; /* No DMA */
1296: acb->sc_kv.dc_addr = buf;
1297: acb->sc_kv.dc_count = len;
1298:
1299: #ifdef DEBUG
1300: if ( data_pointer_debug > 1 )
1.5 christos 1301: printf("sbicicmd(%d,%d):%d\n", dev->target, dev->lun, acb->sc_kv.dc_count);
1.1 chuck 1302: #endif
1303:
1304: /*
1305: * set the sbic into non-DMA mode
1306: */
1307: SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI);
1308:
1309: dev->sc_stat[0] = 0xff;
1310: dev->sc_msg[0] = 0xff;
1311:
1312: /*
1313: * We're stealing the SCSI bus
1314: */
1315: dev->sc_flags |= SBICF_ICMD;
1316:
1317: do {
1318: GET_SBIC_asr (regs, asr);
1319:
1320: /*
1321: * select the SCSI bus (it's an error if bus isn't free)
1322: */
1.2 chuck 1323: if ( (dev->sc_flags & SBICF_SELECTED) == 0 &&
1324: still_busy != SBIC_STATE_DISCONNECT ) {
1.1 chuck 1325: if ( (csr = sbicselectbus(dev)) == 0 ) {
1326: dev->sc_flags &= ~SBICF_ICMD;
1327: return(-1);
1328: }
1329: } else
1.2 chuck 1330: if ( (asr & (SBIC_ASR_BSY | SBIC_ASR_INT)) == SBIC_ASR_INT )
1.1 chuck 1331: GET_SBIC_csr(regs, csr);
1.2 chuck 1332: else
1333: csr = 0;
1334:
1335: if ( csr ) {
1336:
1337: QPRINTF((">ASR:0x%02x CSR:0x%02x< ", asr, csr));
1.1 chuck 1338:
1.2 chuck 1339: switch ( csr ) {
1.1 chuck 1340:
1.2 chuck 1341: case SBIC_CSR_S_XFERRED:
1342: case SBIC_CSR_DISC:
1343: case SBIC_CSR_DISC_1:
1344: {
1345: u_char phase;
1.1 chuck 1346:
1.2 chuck 1347: dev->sc_flags &= ~SBICF_SELECTED;
1348: GET_SBIC_cmd_phase (regs, phase);
1349:
1350: if ( phase == 0x60 ) {
1351: GET_SBIC_tlun (regs, dev->sc_stat[0]);
1352: still_busy = SBIC_STATE_DONE; /* done */
1353: } else {
1.1 chuck 1354: #ifdef DEBUG
1.2 chuck 1355: if ( reselect_debug > 1 )
1.5 christos 1356: printf("sbicicmd: handling disconnect\n");
1.1 chuck 1357: #endif
1.2 chuck 1358: still_busy = SBIC_STATE_DISCONNECT;
1359: }
1.1 chuck 1360: }
1.2 chuck 1361: break;
1.1 chuck 1362:
1.2 chuck 1363: case SBIC_CSR_XFERRED | CMD_PHASE:
1364: case SBIC_CSR_MIS | CMD_PHASE:
1365: case SBIC_CSR_MIS_1 | CMD_PHASE:
1366: case SBIC_CSR_MIS_2 | CMD_PHASE:
1367: {
1368: if ( sbicxfout(regs, clen, cbuf) )
1369: still_busy = sbicabort(dev, "icmd sending cmd");
1370: }
1371: break;
1.1 chuck 1372:
1.2 chuck 1373: case SBIC_CSR_XFERRED | STATUS_PHASE:
1374: case SBIC_CSR_MIS | STATUS_PHASE:
1375: case SBIC_CSR_MIS_1 | STATUS_PHASE:
1376: case SBIC_CSR_MIS_2 | STATUS_PHASE:
1377: {
1378: /*
1379: * The sbic does the status/cmd-complete reading ok,
1380: * so do this with its hi-level commands.
1381: */
1.1 chuck 1382: #ifdef DEBUG
1.2 chuck 1383: if ( sbic_debug )
1.5 christos 1384: printf("SBICICMD status phase (bsy=%d)\n", still_busy);
1.1 chuck 1385: #endif
1.2 chuck 1386: SET_SBIC_cmd_phase(regs, 0x46);
1387: SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER);
1388: }
1389: break;
1.1 chuck 1390:
1.2 chuck 1391: default:
1392: {
1393: still_busy = sbicnextstate(dev, csr, asr);
1394: }
1395: break;
1.1 chuck 1396: }
1397:
1.2 chuck 1398: /*
1399: * make sure the last command was taken,
1400: * ie. we're not hunting after an ignored command..
1401: */
1402: GET_SBIC_asr(regs, asr);
1.1 chuck 1403:
1.2 chuck 1404: /*
1405: * tapes may take a loooong time..
1406: */
1407: while (asr & SBIC_ASR_BSY ) {
1.1 chuck 1408:
1.2 chuck 1409: if ( asr & SBIC_ASR_DBR ) {
1410: int i;
1.1 chuck 1411:
1.5 christos 1412: printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr);
1.1 chuck 1413: #ifdef DDB
1.2 chuck 1414: Debugger();
1.1 chuck 1415: #endif
1.2 chuck 1416: /*
1417: * SBIC is jammed
1418: * DUNNO which direction
1419: * Try old direction
1420: */
1421: GET_SBIC_data(regs, i);
1422: GET_SBIC_asr(regs, asr);
1423:
1424: if ( asr & SBIC_ASR_DBR ) /* Wants us to write */
1425: SET_SBIC_data(regs, i);
1426: }
1427:
1.1 chuck 1428: GET_SBIC_asr(regs, asr);
1429: }
1430: }
1431:
1432: /*
1433: * wait for last command to complete
1434: */
1435: if ( asr & SBIC_ASR_LCI ) {
1.5 christos 1436: printf("sbicicmd: last command ignored\n");
1.1 chuck 1437: }
1438: else
1.2 chuck 1439: if ( still_busy >= SBIC_STATE_RUNNING ) /* Bsy */
1.1 chuck 1440: SBIC_WAIT (regs, SBIC_ASR_INT, sbic_cmd_wait);
1441:
1442: /*
1443: * do it again
1444: */
1.2 chuck 1445: } while ( still_busy >= SBIC_STATE_RUNNING && dev->sc_stat[0] == 0xff );
1.1 chuck 1446:
1447: /*
1448: * Sometimes we need to do an extra read of the CSR
1449: */
1450: GET_SBIC_csr(regs, csr);
1451:
1452: #ifdef DEBUG
1453: if ( data_pointer_debug > 1 )
1.5 christos 1454: printf("sbicicmd done(%d,%d):%d =%d=\n", dev->target, dev->lun,
1.1 chuck 1455: acb->sc_kv.dc_count,
1456: dev->sc_stat[0]);
1457: #endif
1458:
1459: dev->sc_flags &= ~SBICF_ICMD;
1460:
1461: return(dev->sc_stat[0]);
1462: }
1463:
1464: /*
1465: * Finish SCSI xfer command: After the completion interrupt from
1466: * a read/write operation, sequence through the final phases in
1467: * programmed i/o. This routine is a lot like sbicicmd except we
1468: * skip (and don't allow) the select, cmd out and data in/out phases.
1469: */
1470: void
1471: sbicxfdone(dev)
1472: struct sbic_softc *dev;
1473: {
1474: sbic_regmap_p regs = dev->sc_sbicp;
1475: u_char phase,
1476: csr;
1477: int s;
1478:
1479: QPRINTF(("{"));
1480: s = splbio();
1481:
1482: /*
1483: * have the sbic complete on its own
1484: */
1485: SBIC_TC_PUT(regs, 0);
1486: SET_SBIC_cmd_phase(regs, 0x46);
1487: SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER);
1488:
1489: do {
1490:
1491: SBIC_WAIT (regs, SBIC_ASR_INT, 0);
1492: GET_SBIC_csr (regs, csr);
1493: QPRINTF(("%02x:", csr));
1494:
1495: } while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) &&
1496: (csr != SBIC_CSR_S_XFERRED));
1497:
1498: dev->sc_flags &= ~SBICF_SELECTED;
1499:
1500: GET_SBIC_cmd_phase (regs, phase);
1501: QPRINTF(("}%02x", phase));
1502:
1503: if ( phase == 0x60 )
1504: GET_SBIC_tlun(regs, dev->sc_stat[0]);
1505: else
1506: sbicerror(dev, csr);
1507:
1508: QPRINTF(("=STS:%02x=\n", dev->sc_stat[0]));
1509:
1510: splx(s);
1511: }
1512:
1513: /*
1514: * No DMA chains
1515: */
1516: int
1517: sbicgo(dev, xs)
1518: struct sbic_softc *dev;
1.6 bouyer 1519: struct scsipi_xfer *xs;
1.1 chuck 1520: {
1521: struct sbic_acb *acb = dev->sc_nexus;
1522: sbic_regmap_p regs = dev->sc_sbicp;
1523: int i,
1524: dmaflags,
1525: count,
1526: usedma;
1527: u_char csr,
1528: asr,
1529: *addr;
1530:
1.16 bouyer 1531: dev->target = xs->xs_periph->periph_target;
1532: dev->lun = xs->xs_periph->periph_lun;
1.1 chuck 1533:
1534: usedma = sbicdmaok(dev, xs);
1535:
1536: #ifdef DEBUG
1537: if ( data_pointer_debug > 1 )
1.5 christos 1538: printf("sbicgo(%d,%d): usedma=%d\n", dev->target, dev->lun, usedma);
1.1 chuck 1539: #endif
1540:
1541: /*
1542: * select the SCSI bus (it's an error if bus isn't free)
1543: */
1544: if ( (csr = sbicselectbus(dev)) == 0 )
1545: return(0); /* Not done: needs to be rescheduled */
1546:
1547: dev->sc_stat[0] = 0xff;
1548:
1549: /*
1550: * Calculate DMA chains now
1551: */
1552: if ( acb->flags & ACB_DATAIN )
1553: dmaflags = DMAGO_READ;
1554: else
1555: dmaflags = 0;
1556:
1557: addr = acb->sc_kv.dc_addr;
1558: count = acb->sc_kv.dc_count;
1559:
1.12 scw 1560: if ( count && ((char *)kvtop((caddr_t)addr) != acb->sc_pa.dc_addr) ) {
1.19 chs 1561: printf("sbic: DMA buffer mapping changed %p->%x\n",
1.12 scw 1562: acb->sc_pa.dc_addr, kvtop((caddr_t)addr));
1.1 chuck 1563: #ifdef DDB
1564: Debugger();
1565: #endif
1566: }
1567:
1568: #ifdef DEBUG
1569: ++sbicdma_ops; /* count total DMA operations */
1570: #endif
1571:
1572: /*
1573: * Allocate the DMA chain
1574: * Mark end of segment...
1575: */
1576: acb->sc_tcnt = dev->sc_tcnt = 0;
1577: acb->sc_pa.dc_count = 0;
1578:
1579: sbic_load_ptrs(dev);
1580:
1581: /*
1582: * Enable interrupts but don't do any DMA
1583: * enintr() also enables interrupts for the sbic
1584: */
1585: dev->sc_enintr(dev);
1586:
1587: if ( usedma ) {
1588: dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr,
1589: acb->sc_pa.dc_count, dmaflags);
1590: #ifdef DEBUG
1591: dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0;
1592: #endif
1593: } else
1594: dev->sc_dmacmd = 0; /* Don't use DMA */
1595:
1596: acb->sc_dmacmd = dev->sc_dmacmd;
1597:
1598: #ifdef DEBUG
1599: if ( data_pointer_debug > 1 ) {
1.12 scw 1600: printf("sbicgo dmago:%d(%p:%lx) dmacmd=0x%02x\n", dev->target,
1.1 chuck 1601: dev->sc_cur->dc_addr,
1602: dev->sc_tcnt,
1603: dev->sc_dmacmd);
1604: }
1605: #endif
1606:
1607: /*
1608: * Lets cycle a while then let the interrupt handler take over.
1609: */
1610: GET_SBIC_asr(regs, asr);
1611:
1612: do {
1613:
1614: QPRINTF(("go "));
1615:
1616: /*
1617: * Handle the new phase
1618: */
1619: i = sbicnextstate(dev, csr, asr);
1620: #if 0
1621: WAIT_CIP(regs);
1622: #endif
1623: if ( i == SBIC_STATE_RUNNING ) {
1624: GET_SBIC_asr(regs, asr);
1625:
1626: if ( asr & SBIC_ASR_LCI )
1.5 christos 1627: printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr);
1.1 chuck 1628:
1629: if ( asr & SBIC_ASR_INT )
1630: GET_SBIC_csr(regs, csr);
1631: }
1632:
1633: } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) );
1634:
1635: if ( i == SBIC_STATE_DONE ) {
1636: if ( dev->sc_stat[0] == 0xff )
1637: #if 0
1.5 christos 1638: printf("sbicgo: done & stat = 0xff\n");
1.1 chuck 1639: #else
1640: ;
1641: #endif
1642: else
1643: return 1; /* Did we really finish that fast? */
1644: }
1645:
1646: return 0;
1647: }
1648:
1649:
1650: int
1651: sbicintr(dev)
1652: struct sbic_softc *dev;
1653: {
1654: sbic_regmap_p regs = dev->sc_sbicp;
1655: u_char asr,
1656: csr;
1657: int i;
1658:
1659: /*
1660: * pending interrupt?
1661: */
1662: GET_SBIC_asr (regs, asr);
1663: if ( (asr & SBIC_ASR_INT) == 0 )
1664: return(0);
1665:
1.2 chuck 1666: GET_SBIC_csr(regs, csr);
1667:
1.1 chuck 1668: do {
1669:
1670: QPRINTF(("intr[0x%x]", csr));
1671:
1672: i = sbicnextstate(dev, csr, asr);
1673: #if 0
1674: WAIT_CIP(regs);
1675: #endif
1.2 chuck 1676: if ( i == SBIC_STATE_RUNNING ) {
1677: GET_SBIC_asr(regs, asr);
1678:
1679: if ( asr & SBIC_ASR_LCI )
1.5 christos 1680: printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr);
1.2 chuck 1681:
1682: if ( asr & SBIC_ASR_INT )
1683: GET_SBIC_csr(regs, csr);
1684: }
1.1 chuck 1685:
1686: } while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) );
1687:
1688: QPRINTF(("intr done. state=%d, asr=0x%02x\n", i, asr));
1689:
1690: return(1);
1691: }
1692:
1693: /*
1694: * Run commands and wait for disconnect.
1695: * This is only ever called when a command is in progress, when we
1696: * want to busy wait for it to finish.
1697: */
1698: int
1699: sbicpoll(dev)
1700: struct sbic_softc *dev;
1701: {
1702: sbic_regmap_p regs = dev->sc_sbicp;
1703: u_char asr,
1704: csr;
1705: int i;
1706:
1707: /*
1708: * Wait for the next interrupt
1709: */
1710: SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait);
1711:
1712: do {
1713: GET_SBIC_asr (regs, asr);
1714:
1715: if ( asr & SBIC_ASR_INT )
1716: GET_SBIC_csr(regs, csr);
1717:
1718: QPRINTF(("poll[0x%x]", csr));
1719:
1720: /*
1721: * Handle it
1722: */
1723: i = sbicnextstate(dev, csr, asr);
1724:
1725: WAIT_CIP(regs);
1726: GET_SBIC_asr(regs, asr);
1727:
1728: /*
1729: * tapes may take a loooong time..
1730: */
1731: while ( asr & SBIC_ASR_BSY ) {
1.2 chuck 1732: u_char z = 0;
1.1 chuck 1733:
1734: if ( asr & SBIC_ASR_DBR ) {
1.5 christos 1735: printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr);
1.1 chuck 1736: #ifdef DDB
1737: Debugger();
1738: #endif
1739: /*
1740: * SBIC is jammed
1741: * DUNNO which direction
1742: * Try old direction
1743: */
1.2 chuck 1744: GET_SBIC_data(regs, z);
1.1 chuck 1745: GET_SBIC_asr(regs, asr);
1746:
1747: if ( asr & SBIC_ASR_DBR ) /* Wants us to write */
1.2 chuck 1748: SET_SBIC_data(regs, z);
1.1 chuck 1749: }
1750:
1751: GET_SBIC_asr(regs, asr);
1752: }
1753:
1754: if ( asr & SBIC_ASR_LCI )
1.5 christos 1755: printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr);
1.1 chuck 1756: else
1.2 chuck 1757: if ( i == SBIC_STATE_RUNNING ) /* BSY */
1.1 chuck 1758: SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait);
1759:
1760: } while ( i == SBIC_STATE_RUNNING );
1761:
1762: return(1);
1763: }
1764:
1765: /*
1766: * Handle a single msgin
1767: */
1768: int
1769: sbicmsgin(dev)
1770: struct sbic_softc *dev;
1771: {
1772: sbic_regmap_p regs = dev->sc_sbicp;
1773: int recvlen = 1;
1774: u_char asr,
1775: csr,
1776: *tmpaddr,
1777: *msgaddr;
1778:
1779: tmpaddr = msgaddr = dev->sc_msg;
1780:
1781: tmpaddr[0] = 0xff;
1782: tmpaddr[1] = 0xff;
1783:
1784: GET_SBIC_asr(regs, asr);
1785:
1786: #ifdef DEBUG
1787: if ( reselect_debug > 1 )
1.5 christos 1788: printf("sbicmsgin asr=%02x\n", asr);
1.1 chuck 1789: #endif
1790:
1791: GET_SBIC_selid (regs, csr);
1792: SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI);
1793:
1794: SBIC_TC_PUT(regs, 0);
1795: SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI);
1796:
1797: do {
1798: while( recvlen-- ) {
1799:
1800: /*
1801: * Fetch the next byte of the message
1802: */
1803: RECV_BYTE(regs, *tmpaddr);
1804:
1805: /*
1806: * get the command completion interrupt, or we
1807: * can't send a new command (LCI)
1808: */
1809: SBIC_WAIT(regs, SBIC_ASR_INT, 0);
1810: GET_SBIC_csr(regs, csr);
1811:
1812: #ifdef DEBUG
1813: if ( reselect_debug > 1 )
1.5 christos 1814: printf("sbicmsgin: got %02x csr %02x\n", *tmpaddr, csr);
1.1 chuck 1815: #endif
1816:
1817: tmpaddr++;
1818:
1819: if ( recvlen ) {
1820: /*
1821: * Clear ACK, and wait for the interrupt for the next byte
1822: */
1823: SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK);
1824: SBIC_WAIT(regs, SBIC_ASR_INT, 0);
1825: GET_SBIC_csr(regs, csr);
1826: }
1827: }
1828:
1829: if ( msgaddr[0] == 0xff ) {
1.5 christos 1830: printf("sbicmsgin: sbic swallowed our message\n");
1.1 chuck 1831: break;
1832: }
1833:
1834: #ifdef DEBUG
1835: if ( sync_debug ) {
1836: GET_SBIC_asr(regs, asr);
1.5 christos 1837: printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", csr, asr, msgaddr[0]);
1.1 chuck 1838: }
1839: #endif
1840: /*
1841: * test whether this is a reply to our sync
1842: * request
1843: */
1844: if ( MSG_ISIDENTIFY(msgaddr[0]) ) {
1845:
1846: /*
1847: * Got IFFY msg -- ack it
1848: */
1849: QPRINTF(("IFFY"));
1850:
1851: } else
1852: if ( msgaddr[0] == MSG_REJECT &&
1853: dev->sc_sync[dev->target].state == SYNC_SENT) {
1854:
1855: /*
1856: * Target probably rejected our Sync negotiation.
1857: */
1858: QPRINTF(("REJECT of SYN"));
1859:
1860: #ifdef DEBUG
1861: if ( sync_debug )
1.5 christos 1862: printf("target %d rejected sync, going async\n", dev->target);
1.1 chuck 1863: #endif
1864:
1865: dev->sc_sync[dev->target].period = sbic_min_period;
1866: dev->sc_sync[dev->target].offset = 0;
1867: dev->sc_sync[dev->target].state = SYNC_DONE;
1868: SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset,
1869: dev->sc_sync[dev->target].period));
1870:
1871: } else
1872: if ( msgaddr[0] == MSG_REJECT ) {
1873:
1874: /*
1875: * we'll never REJECt a REJECT message..
1876: */
1877: QPRINTF(("REJECT"));
1878:
1879: } else
1880: if ( msgaddr[0] == MSG_SAVE_DATA_PTR ) {
1881:
1882: /*
1883: * don't reject this either.
1884: */
1885: QPRINTF(("MSG_SAVE_DATA_PTR"));
1886:
1887: } else
1888: if ( msgaddr[0] == MSG_RESTORE_PTR ) {
1889:
1890: /*
1891: * don't reject this either.
1892: */
1893: QPRINTF(("MSG_RESTORE_PTR"));
1894:
1895: } else
1896: if ( msgaddr[0] == MSG_DISCONNECT ) {
1897:
1898: /*
1899: * Target is disconnecting...
1900: */
1901: QPRINTF(("DISCONNECT"));
1902:
1903: #ifdef DEBUG
1904: if ( reselect_debug > 1 && msgaddr[0] == MSG_DISCONNECT )
1.5 christos 1905: printf("sbicmsgin: got disconnect msg %s\n",
1.1 chuck 1906: (dev->sc_flags & SBICF_ICMD) ? "rejecting" : "");
1907: #endif
1908:
1909: if ( dev->sc_flags & SBICF_ICMD ) {
1910: /*
1911: * We're in immediate mode. Prevent disconnects.
1912: * prepare to reject the message, NACK
1913: */
1914: SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN);
1915: WAIT_CIP(regs);
1916: }
1917:
1918: } else
1919: if ( msgaddr[0] == MSG_CMD_COMPLETE ) {
1920:
1921: /*
1922: * !! KLUDGE ALERT !! quite a few drives don't seem to
1923: * really like the current way of sending the
1924: * sync-handshake together with the ident-message, and
1925: * they react by sending command-complete and
1926: * disconnecting right after returning the valid sync
1927: * handshake. So, all I can do is reselect the drive,
1928: * and hope it won't disconnect again. I don't think
1929: * this is valid behavior, but I can't help fixing a
1930: * problem that apparently exists.
1931: *
1932: * Note: we should not get here on `normal' command
1933: * completion, as that condition is handled by the
1934: * high-level sel&xfer resume command used to walk
1935: * thru status/cc-phase.
1936: */
1937: QPRINTF(("CMD_COMPLETE"));
1938:
1939: #ifdef DEBUG
1940: if ( sync_debug )
1.5 christos 1941: printf ("GOT MSG %d! target %d acting weird.."
1.1 chuck 1942: " waiting for disconnect...\n", msgaddr[0], dev->target);
1943: #endif
1944:
1945: /*
1946: * Check to see if sbic is handling this
1947: */
1948: GET_SBIC_asr(regs, asr);
1949:
1950: /*
1951: * XXXSCW: I'm not convinced of this, we haven't negated ACK yet...
1952: */
1953: if ( asr & SBIC_ASR_BSY )
1954: return SBIC_STATE_RUNNING;
1955:
1956: /*
1957: * Let's try this: Assume it works and set status to 00
1958: */
1959: dev->sc_stat[0] = 0;
1960:
1961: } else
1962: if ( msgaddr[0] == MSG_EXT_MESSAGE && tmpaddr == &(msgaddr[1]) ) {
1963:
1964: /*
1965: * Target is sending us an extended message. We'll assume it's
1966: * the response to our Sync. negotiation.
1967: */
1968: QPRINTF(("ExtMSG\n"));
1969:
1970: /*
1971: * Read in whole extended message. First, negate ACK to accept
1972: * the MSG_EXT_MESSAGE byte...
1973: */
1974: SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK);
1975:
1976: /*
1977: * Wait for the interrupt for the next byte (length)
1978: */
1979: SBIC_WAIT(regs, SBIC_ASR_INT, 0);
1980: GET_SBIC_csr(regs, csr);
1981:
1982: #ifdef DEBUG
1983: QPRINTF(("CLR ACK csr %02x\n", csr));
1984: #endif
1985:
1986: /*
1987: * Read the length byte
1988: */
1989: RECV_BYTE(regs, *tmpaddr);
1990:
1991: /*
1992: * Wait for command completion IRQ
1993: */
1994: SBIC_WAIT(regs, SBIC_ASR_INT, 0);
1995: GET_SBIC_csr(regs, csr);
1996:
1997: /*
1998: * Reload the loop counter
1999: */
2000: recvlen = *tmpaddr++;
2001:
2002: QPRINTF(("Recving ext msg, csr %02x len %02x\n", csr, recvlen));
2003:
2004: } else
2005: if ( msgaddr[0] == MSG_EXT_MESSAGE && msgaddr[1] == 3 &&
2006: msgaddr[2] == MSG_SYNC_REQ ) {
2007:
2008: /*
2009: * We've received the complete Extended Message Sync. Request...
2010: */
2011: QPRINTF(("SYN"));
2012:
2013: /*
2014: * Compute the required Transfer Period for the WD chip...
2015: */
2016: dev->sc_sync[dev->target].period = sbicfromscsiperiod(dev, msgaddr[3]);
2017: dev->sc_sync[dev->target].offset = msgaddr[4];
2018: dev->sc_sync[dev->target].state = SYNC_DONE;
2019:
2020: /*
2021: * Put the WD chip in synchronous mode
2022: */
2023: SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset,
2024: dev->sc_sync[dev->target].period));
1.2 chuck 2025: #ifdef DEBUG
2026: if ( sync_debug )
1.5 christos 2027: printf("msgin(%d): sync reg = 0x%02x\n", dev->target,
1.2 chuck 2028: SBIC_SYN(dev->sc_sync[dev->target].offset,
2029: dev->sc_sync[dev->target].period));
2030: #endif
1.1 chuck 2031:
1.5 christos 2032: printf("%s: target %d now synchronous, period=%dns, offset=%d.\n",
1.1 chuck 2033: dev->sc_dev.dv_xname, dev->target,
2034: msgaddr[3] * 4, msgaddr[4]);
2035:
2036: } else {
2037:
2038: /*
2039: * We don't support whatever this message is...
2040: */
2041: #ifdef DEBUG
2042: if ( sbic_debug || sync_debug )
1.5 christos 2043: printf ("sbicmsgin: Rejecting message 0x%02x\n", msgaddr[0]);
1.1 chuck 2044: #endif
2045:
2046: /*
2047: * prepare to reject the message, NACK
2048: */
2049: SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN);
2050: WAIT_CIP(regs);
2051: }
2052:
2053: /*
2054: * Negate ACK to complete the transfer
2055: */
2056: SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK);
2057:
2058: /*
2059: * Wait for the interrupt for the next byte, or phase change.
2060: * Only read the CSR if we have more data to transfer.
2061: * XXXSCW: We should really verify that we're still in MSG IN phase
2062: * before blindly going back around this loop, but that would mean
2063: * we read the CSR... <sigh>
2064: */
2065: SBIC_WAIT(regs, SBIC_ASR_INT, 0);
2066: if ( recvlen > 0 )
2067: GET_SBIC_csr(regs, csr);
2068:
2069: } while ( recvlen > 0 );
2070:
2071: /*
2072: * Should still have one CSR to read
2073: */
2074: return SBIC_STATE_RUNNING;
2075: }
2076:
2077:
2078: /*
2079: * sbicnextstate()
2080: * return:
1.2 chuck 2081: * SBIC_STATE_DONE == done
2082: * SBIC_STATE_RUNNING == working
2083: * SBIC_STATE_DISCONNECT == disconnected
2084: * SBIC_STATE_ERROR == error
1.1 chuck 2085: */
2086: int
2087: sbicnextstate(dev, csr, asr)
2088: struct sbic_softc *dev;
2089: u_char csr,
2090: asr;
2091: {
2092: sbic_regmap_p regs = dev->sc_sbicp;
2093: struct sbic_acb *acb = dev->sc_nexus;
2094:
2095: QPRINTF(("next[%02x,%02x]: ",asr,csr));
2096:
2097: switch (csr) {
2098:
2099: case SBIC_CSR_XFERRED | CMD_PHASE:
2100: case SBIC_CSR_MIS | CMD_PHASE:
2101: case SBIC_CSR_MIS_1 | CMD_PHASE:
2102: case SBIC_CSR_MIS_2 | CMD_PHASE:
2103: {
2104: if ( sbicxfout(regs, acb->clen, &acb->cmd) )
2105: goto abort;
2106: }
2107: break;
2108:
2109: case SBIC_CSR_XFERRED | STATUS_PHASE:
2110: case SBIC_CSR_MIS | STATUS_PHASE:
2111: case SBIC_CSR_MIS_1 | STATUS_PHASE:
2112: case SBIC_CSR_MIS_2 | STATUS_PHASE:
2113: {
2114: SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI);
2115:
2116: /*
2117: * this should be the normal i/o completion case.
2118: * get the status & cmd complete msg then let the
2119: * device driver look at what happened.
2120: */
2121: sbicxfdone(dev);
2122:
2123: #ifdef DEBUG
2124: dev->sc_dmatimo = 0;
2125: if ( data_pointer_debug > 1 )
1.12 scw 2126: printf("next dmastop: %d(%p:%lx)\n", dev->target,
1.1 chuck 2127: dev->sc_cur->dc_addr,
2128: dev->sc_tcnt);
2129: #endif
2130: /*
2131: * Stop the DMA chip
2132: */
2133: dev->sc_dmastop(dev);
2134:
2135: dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH);
2136:
2137: /*
2138: * Indicate to the upper layers that the command is done
2139: */
2140: sbic_scsidone(acb, dev->sc_stat[0]);
2141:
2142: return SBIC_STATE_DONE;
2143: }
2144:
2145: case SBIC_CSR_XFERRED | DATA_OUT_PHASE:
2146: case SBIC_CSR_XFERRED | DATA_IN_PHASE:
2147: case SBIC_CSR_MIS | DATA_OUT_PHASE:
2148: case SBIC_CSR_MIS | DATA_IN_PHASE:
2149: case SBIC_CSR_MIS_1 | DATA_OUT_PHASE:
2150: case SBIC_CSR_MIS_1 | DATA_IN_PHASE:
2151: case SBIC_CSR_MIS_2 | DATA_OUT_PHASE:
2152: case SBIC_CSR_MIS_2 | DATA_IN_PHASE:
2153: {
2154: /*
2155: * Verify that we expected to transfer data...
2156: */
2157: if ( acb->sc_kv.dc_count <= 0 ) {
1.5 christos 2158: printf("next: DATA phase with xfer count == %d, asr:0x%02x csr:0x%02x\n",
1.1 chuck 2159: acb->sc_kv.dc_count, asr, csr);
2160: goto abort;
2161: }
2162:
2163: /*
2164: * Should we transfer using PIO or DMA ?
2165: */
1.10 thorpej 2166: if ( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD ||
1.1 chuck 2167: acb->sc_dmacmd == 0 ) {
2168:
2169: /*
2170: * Do PIO transfer
2171: */
2172: int i;
2173:
2174: #ifdef DEBUG
2175: if ( data_pointer_debug > 1 )
1.12 scw 2176: printf("next PIO: %d(%p:%x)\n", dev->target,
1.1 chuck 2177: acb->sc_kv.dc_addr,
2178: acb->sc_kv.dc_count);
2179: #endif
2180:
2181: if ( SBIC_PHASE(csr) == DATA_IN_PHASE )
2182: /*
2183: * data in
2184: */
2185: i = sbicxfin(regs, acb->sc_kv.dc_count,
2186: acb->sc_kv.dc_addr);
2187: else
2188: /*
2189: * data out
2190: */
2191: i = sbicxfout(regs, acb->sc_kv.dc_count,
2192: acb->sc_kv.dc_addr);
2193:
2194: acb->sc_kv.dc_addr += (acb->sc_kv.dc_count - i);
2195: acb->sc_kv.dc_count = i;
2196:
2197: /*
2198: * Update current count...
2199: */
2200: acb->sc_tcnt = dev->sc_tcnt = i;
2201:
2202: dev->sc_flags &= ~SBICF_INDMA;
2203:
2204: } else {
2205:
2206: /*
2207: * Do DMA transfer
1.21 wiz 2208: * set next DMA addr and dec count
1.1 chuck 2209: */
2210: sbic_save_ptrs(dev);
2211: sbic_load_ptrs(dev);
2212:
2213: SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI |
2214: SBIC_MACHINE_DMA_MODE);
2215:
2216: #ifdef DEBUG
2217: dev->sc_dmatimo = 1;
2218: if ( data_pointer_debug > 1 )
1.12 scw 2219: printf("next DMA: %d(%p:%lx)\n", dev->target,
1.1 chuck 2220: dev->sc_cur->dc_addr,
2221: dev->sc_tcnt);
2222: #endif
2223: /*
2224: * Start the DMA chip going
2225: */
2226: dev->sc_tcnt = dev->sc_dmanext(dev);
2227:
2228: /*
2229: * Tell the WD chip how much to transfer this time around
2230: */
2231: SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt);
2232:
2233: /*
2234: * Start the transfer
2235: */
2236: SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO);
2237:
2238: /*
2239: * Indicate that we're in DMA mode
2240: */
2241: dev->sc_flags |= SBICF_INDMA;
2242: }
2243: }
2244: break;
2245:
2246: case SBIC_CSR_XFERRED | MESG_IN_PHASE:
2247: case SBIC_CSR_MIS | MESG_IN_PHASE:
2248: case SBIC_CSR_MIS_1 | MESG_IN_PHASE:
2249: case SBIC_CSR_MIS_2 | MESG_IN_PHASE:
2250: {
2251: sbic_save_ptrs(dev);
2252:
2253: /*
2254: * Handle a single message in...
2255: */
2256: return sbicmsgin(dev);
2257: }
2258:
2259: case SBIC_CSR_MSGIN_W_ACK:
2260: {
2261: /*
2262: * We should never see this since it's handled in 'sbicmsgin()'
2263: * but just for the sake of paranoia...
2264: */
2265: SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */
1.5 christos 2266: printf("Acking unknown msgin CSR:%02x",csr);
1.1 chuck 2267: }
2268: break;
2269:
2270: case SBIC_CSR_XFERRED | MESG_OUT_PHASE:
2271: case SBIC_CSR_MIS | MESG_OUT_PHASE:
2272: case SBIC_CSR_MIS_1 | MESG_OUT_PHASE:
2273: case SBIC_CSR_MIS_2 | MESG_OUT_PHASE:
2274: {
2275: /*
2276: * We only ever handle a message out phase here for sending a
2277: * REJECT message.
2278: */
2279: sbic_save_ptrs(dev);
2280:
2281: #ifdef DEBUG
2282: if (sync_debug)
1.5 christos 2283: printf ("sending REJECT msg to last msg.\n");
1.1 chuck 2284: #endif
2285:
2286: SEND_BYTE(regs, MSG_REJECT);
2287: WAIT_CIP(regs);
2288: }
2289: break;
2290:
2291: case SBIC_CSR_DISC:
2292: case SBIC_CSR_DISC_1:
2293: {
2294: /*
2295: * Try to schedule another target
2296: */
2297: sbic_save_ptrs(dev);
2298:
2299: dev->sc_flags &= ~SBICF_SELECTED;
2300:
2301: #ifdef DEBUG
2302: if ( reselect_debug > 1 )
1.5 christos 2303: printf("sbicnext target %d disconnected\n", dev->target);
1.1 chuck 2304: #endif
2305:
2306: TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain);
2307:
2308: ++dev->sc_tinfo[dev->target].dconns;
2309:
2310: dev->sc_nexus = NULL;
2311: dev->sc_xs = NULL;
2312:
1.10 thorpej 2313: if ( acb->xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD ||
1.1 chuck 2314: !sbic_parallel_operations )
2315: return SBIC_STATE_DISCONNECT;
2316:
2317: QPRINTF(("sbicnext: calling sbic_sched\n"));
2318:
2319: sbic_sched(dev);
2320:
2321: QPRINTF(("sbicnext: sbic_sched returned\n"));
2322:
2323: return SBIC_STATE_DISCONNECT;
2324: }
2325:
2326: case SBIC_CSR_RSLT_NI:
2327: case SBIC_CSR_RSLT_IFY:
2328: {
2329: /*
2330: * A reselection.
2331: * Note that since we don't enable Advanced Features (assuming
2332: * the WD chip is at least the 'A' revision), we're only ever
2333: * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the
2334: * hell of it, we'll handle it anyway, for all the extra code
2335: * it needs...
2336: */
2337: u_char newtarget,
2338: newlun;
2339:
2340: GET_SBIC_rselid(regs, newtarget);
2341:
2342: /*
2343: * check SBIC_RID_SIV?
2344: */
2345: newtarget &= SBIC_RID_MASK;
2346:
2347: if ( csr == SBIC_CSR_RSLT_IFY ) {
2348:
2349: /*
2350: * Read Identify msg to avoid lockup
2351: */
2352: GET_SBIC_data(regs, newlun);
2353: WAIT_CIP(regs);
2354: newlun &= SBIC_TLUN_MASK;
2355:
2356: } else {
2357:
2358: /*
2359: * Need to read Identify message the hard way, assuming
2360: * the target even sends us one...
2361: */
2362: for (newlun = 255; newlun; --newlun) {
2363: GET_SBIC_asr(regs, asr);
2364: if (asr & SBIC_ASR_INT)
2365: break;
1.2 chuck 2366: delay(10);
1.1 chuck 2367: }
2368:
2369: /*
2370: * If we didn't get an interrupt, somethink's up
2371: */
2372: if ( (asr & SBIC_ASR_INT) == 0 ) {
1.5 christos 2373: printf("%s: Reselect without identify? asr %x\n",
1.2 chuck 2374: dev->sc_dev.dv_xname, asr);
1.1 chuck 2375: newlun = 0; /* XXXX */
2376: } else {
2377: /*
2378: * We got an interrupt, verify that it's a change to
2379: * message in phase, and if so read the message.
2380: */
2381: GET_SBIC_csr(regs,csr);
2382:
1.12 scw 2383: if ( csr == (SBIC_CSR_MIS | MESG_IN_PHASE) ||
2384: csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) ||
2385: csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE) ) {
1.1 chuck 2386: /*
2387: * Yup, gone to message in. Fetch the target LUN
2388: */
2389: sbicmsgin(dev);
2390: newlun = dev->sc_msg[0] & 0x07;
2391:
2392: } else {
2393: /*
2394: * Whoops! Target didn't go to message in phase!!
2395: */
1.5 christos 2396: printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr);
1.1 chuck 2397: newlun = 0; /* XXXSCW */
2398: }
2399: }
2400: }
2401:
2402: /*
2403: * Ok, we have the identity of the reselecting target.
2404: */
2405: #ifdef DEBUG
2406: if ( reselect_debug > 1 ||
2407: (reselect_debug && csr == SBIC_CSR_RSLT_NI) ) {
1.5 christos 2408: printf("sbicnext: reselect %s from targ %d lun %d\n",
1.1 chuck 2409: csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, newlun);
2410: }
2411: #endif
2412:
2413: if ( dev->sc_nexus ) {
2414: /*
2415: * Whoops! We've been reselected with an command in progress!
2416: * The best we can do is to put the current command back on the
2417: * ready list and hope for the best.
2418: */
2419: #ifdef DEBUG
2420: if ( reselect_debug > 1 ) {
1.5 christos 2421: printf("%s: reselect %s with active command\n",
1.1 chuck 2422: dev->sc_dev.dv_xname,
2423: csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY");
2424: }
2425: #endif
2426:
2427: TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain);
2428:
2429: dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun);
2430:
2431: dev->sc_nexus = NULL;
2432: dev->sc_xs = NULL;
2433: }
2434:
2435: /*
2436: * Reload sync values for this target
2437: */
2438: if ( dev->sc_sync[newtarget].state == SYNC_DONE )
2439: SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset,
2440: dev->sc_sync[newtarget].period));
2441: else
2442: SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period));
2443:
2444: /*
2445: * Loop through the nexus list until we find the saved entry
2446: * for the reselecting target...
2447: */
2448: for (acb = dev->nexus_list.tqh_first; acb;
2449: acb = acb->chain.tqe_next) {
2450:
1.16 bouyer 2451: if ( acb->xs->xs_periph->periph_target == newtarget &&
2452: acb->xs->xs_periph->periph_lun == newlun) {
1.1 chuck 2453: /*
2454: * We've found the saved entry. Dequeue it, and
2455: * make it current again.
2456: */
2457: TAILQ_REMOVE(&dev->nexus_list, acb, chain);
2458:
2459: dev->sc_nexus = acb;
2460: dev->sc_xs = acb->xs;
2461: dev->sc_flags |= SBICF_SELECTED;
2462: dev->target = newtarget;
2463: dev->lun = newlun;
2464: break;
2465: }
2466: }
2467:
2468: if ( acb == NULL ) {
1.12 scw 2469: printf("%s: reselect %s targ %d not in nexus_list %p\n",
1.1 chuck 2470: dev->sc_dev.dv_xname,
2471: csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget,
2472: &dev->nexus_list.tqh_first);
2473: panic("bad reselect in sbic");
2474: }
2475:
2476: if ( csr == SBIC_CSR_RSLT_IFY )
2477: SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK);
2478: }
2479: break;
2480:
2481: default:
2482: abort:
2483: {
2484: /*
2485: * Something unexpected happened -- deal with it.
2486: */
1.5 christos 2487: printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr);
1.1 chuck 2488:
2489: #ifdef DDB
2490: Debugger();
2491: #endif
2492:
2493: #ifdef DEBUG
2494: dev->sc_dmatimo = 0;
2495: if ( data_pointer_debug > 1 )
1.12 scw 2496: printf("next dmastop: %d(%p:%lx)\n", dev->target,
1.1 chuck 2497: dev->sc_cur->dc_addr,
2498: dev->sc_tcnt);
2499: #endif
2500:
2501: dev->sc_dmastop(dev);
2502: SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI);
2503: if ( dev->sc_xs ) sbicerror(dev, csr);
2504: sbicabort(dev, "next");
2505:
2506: if ( dev->sc_flags & SBICF_INDMA ) {
2507: dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH);
2508:
2509: #ifdef DEBUG
2510: dev->sc_dmatimo = 0;
2511: if ( data_pointer_debug > 1 )
1.12 scw 2512: printf("next dmastop: %d(%p:%lx)\n", dev->target,
1.1 chuck 2513: dev->sc_cur->dc_addr,
2514: dev->sc_tcnt);
2515: #endif
2516: sbic_scsidone(acb, -1);
2517: }
2518:
2519: return SBIC_STATE_ERROR;
2520: }
2521: }
2522:
2523: return(SBIC_STATE_RUNNING);
2524: }
2525:
2526:
2527: /*
2528: * Check if DMA can not be used with specified buffer
2529: */
2530: int
2531: sbiccheckdmap(bp, len, mask)
2532: void *bp;
2533: u_long len,
2534: mask;
2535: {
2536: u_char *buffer;
2537: u_long phy_buf;
2538: u_long phy_len;
2539:
2540: buffer = bp;
2541:
2542: if ( len == 0 )
2543: return(1);
2544:
2545: while ( len ) {
2546:
1.12 scw 2547: phy_buf = kvtop((caddr_t)buffer);
1.20 thorpej 2548: phy_len = PAGE_SIZE - ((int) buffer & PGOFSET);
1.1 chuck 2549:
2550: if ( len < phy_len )
2551: phy_len = len;
2552:
2553: if ( phy_buf & mask )
2554: return(1);
2555:
2556: buffer += phy_len;
2557: len -= phy_len;
2558: }
2559:
2560: return(0);
2561: }
2562:
2563: int
2564: sbictoscsiperiod(dev, a)
2565: struct sbic_softc *dev;
2566: int a;
2567: {
2568: unsigned int fs;
2569:
2570: /*
2571: * cycle = DIV / (2 * CLK)
2572: * DIV = FS + 2
2573: * best we can do is 200ns at 20Mhz, 2 cycles
2574: */
2575:
2576: GET_SBIC_myid(dev->sc_sbicp, fs);
2577:
2578: fs = (fs >> 6) + 2; /* DIV */
2579:
2580: fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */
2581:
2582: if ( a < 2 )
2583: a = 8; /* map to Cycles */
2584:
2585: return ( (fs * a) >> 2 ); /* in 4 ns units */
2586: }
2587:
2588: int
2589: sbicfromscsiperiod(dev, p)
2590: struct sbic_softc *dev;
2591: int p;
2592: {
2593: unsigned fs,
2594: ret;
2595:
2596: /*
2597: * Just the inverse of the above
2598: */
2599: GET_SBIC_myid(dev->sc_sbicp, fs);
2600:
2601: fs = (fs >> 6) + 2; /* DIV */
2602:
2603: fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */
2604:
2605: ret = p << 2; /* in ns units */
2606: ret = ret / fs; /* in Cycles */
2607:
2608: if ( ret < sbic_min_period )
2609: return(sbic_min_period);
2610:
2611: /*
2612: * verify rounding
2613: */
2614: if ( sbictoscsiperiod(dev, ret) < p )
2615: ret++;
2616:
2617: return( (ret >= 8) ? 0 : ret );
2618: }
2619:
2620: #ifdef DEBUG
2621: void
2622: sbictimeout(dev)
2623: struct sbic_softc *dev;
2624: {
2625: int s,
2626: asr;
2627:
2628: s = splbio();
2629:
2630: if ( dev->sc_dmatimo ) {
2631:
2632: if ( dev->sc_dmatimo > 1 ) {
2633:
1.21 wiz 2634: printf("%s: DMA timeout #%d\n", dev->sc_dev.dv_xname,
1.1 chuck 2635: dev->sc_dmatimo - 1);
2636:
2637: GET_SBIC_asr(dev->sc_sbicp, asr);
2638:
2639: if ( asr & SBIC_ASR_INT ) {
2640: /*
2641: * We need to service a missed IRQ
2642: */
2643: sbicintr(dev);
1.2 chuck 2644: } else {
2645: (void) sbicabort(dev, "timeout");
2646: splx(s);
2647: return;
1.1 chuck 2648: }
2649: }
2650:
2651: dev->sc_dmatimo++;
2652: }
2653:
2654: splx(s);
2655:
1.13 thorpej 2656: callout_reset(&dev->sc_timo_ch, 30 * hz, (void *)sbictimeout, dev);
1.1 chuck 2657: }
2658: #endif
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