version 1.26.2.2, 2007/09/03 14:28:10 |
version 1.26.2.3, 2008/01/21 09:37:38 |
Line 127 __KERNEL_RCSID(0, "$NetBSD$"); |
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Line 127 __KERNEL_RCSID(0, "$NetBSD$"); |
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*/ |
*/ |
#define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) |
#define SBIC_WAIT(regs, until, timeo) sbicwait(regs, until, timeo, __LINE__) |
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int sbicicmd __P((struct sbic_softc *, void *, int, void *, int)); |
int sbicicmd (struct sbic_softc *, void *, int, void *, int); |
int sbicgo __P((struct sbic_softc *, struct scsipi_xfer *)); |
int sbicgo (struct sbic_softc *, struct scsipi_xfer *); |
int sbicdmaok __P((struct sbic_softc *, struct scsipi_xfer *)); |
int sbicdmaok (struct sbic_softc *, struct scsipi_xfer *); |
int sbicwait __P((sbic_regmap_p, u_char, int , int)); |
int sbicwait (sbic_regmap_p, u_char, int , int); |
int sbiccheckdmap __P((void *, u_long, u_long)); |
int sbiccheckdmap (void *, u_long, u_long); |
u_char sbicselectbus __P((struct sbic_softc *)); |
u_char sbicselectbus (struct sbic_softc *); |
int sbicxfout __P((sbic_regmap_p, int, void *)); |
int sbicxfout (sbic_regmap_p, int, void *); |
int sbicxfin __P((sbic_regmap_p, int, void *)); |
int sbicxfin (sbic_regmap_p, int, void *); |
int sbicfromscsiperiod __P((struct sbic_softc *, int)); |
int sbicfromscsiperiod (struct sbic_softc *, int); |
int sbictoscsiperiod __P((struct sbic_softc *, int)); |
int sbictoscsiperiod (struct sbic_softc *, int); |
int sbicpoll __P((struct sbic_softc *)); |
int sbicpoll (struct sbic_softc *); |
int sbicnextstate __P((struct sbic_softc *, u_char, u_char)); |
int sbicnextstate (struct sbic_softc *, u_char, u_char); |
int sbicmsgin __P((struct sbic_softc *)); |
int sbicmsgin (struct sbic_softc *); |
int sbicabort __P((struct sbic_softc *, const char *)); |
int sbicabort (struct sbic_softc *, const char *); |
void sbicxfdone __P((struct sbic_softc *)); |
void sbicxfdone (struct sbic_softc *); |
void sbicerror __P((struct sbic_softc *,u_char)); |
void sbicerror (struct sbic_softc *, u_char); |
void sbicreset __P((struct sbic_softc *)); |
void sbicreset (struct sbic_softc *); |
void sbic_scsidone __P((struct sbic_acb *, int)); |
void sbic_scsidone (struct sbic_acb *, int); |
void sbic_sched __P((struct sbic_softc *)); |
void sbic_sched (struct sbic_softc *); |
void sbic_save_ptrs __P((struct sbic_softc *)); |
void sbic_save_ptrs (struct sbic_softc *); |
void sbic_load_ptrs __P((struct sbic_softc *)); |
void sbic_load_ptrs (struct sbic_softc *); |
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/* |
/* |
* Synch xfer parameters, and timing conversions |
* Synch xfer parameters, and timing conversions |
Line 183 int sync_debug = 0; /* Debug |
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Line 183 int sync_debug = 0; /* Debug |
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int reselect_debug = 0; /* Debug all reselection related things */ |
int reselect_debug = 0; /* Debug all reselection related things */ |
int data_pointer_debug = 0; /* Debug Data Pointer related things */ |
int data_pointer_debug = 0; /* Debug Data Pointer related things */ |
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void sbictimeout __P((struct sbic_softc *dev)); |
void sbictimeout(struct sbic_softc *dev); |
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#else |
#else |
#define QPRINTF(a) /* */ |
#define QPRINTF(a) /* */ |
Line 194 void sbictimeout __P((struct sbic_sof |
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Line 194 void sbictimeout __P((struct sbic_sof |
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* default minphys routine for sbic based controllers |
* default minphys routine for sbic based controllers |
*/ |
*/ |
void |
void |
sbic_minphys(bp) |
sbic_minphys(struct buf *bp) |
struct buf *bp; |
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{ |
{ |
/* |
/* |
* No max transfer at this level. |
* No max transfer at this level. |
*/ |
*/ |
minphys(bp); |
minphys(bp); |
} |
} |
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Line 208 sbic_minphys(bp) |
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Line 207 sbic_minphys(bp) |
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* Save DMA pointers. Take into account partial transfer. Shut down DMA. |
* Save DMA pointers. Take into account partial transfer. Shut down DMA. |
*/ |
*/ |
void |
void |
sbic_save_ptrs(dev) |
sbic_save_ptrs(struct sbic_softc *dev) |
struct sbic_softc *dev; |
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{ |
{ |
sbic_regmap_p regs; |
sbic_regmap_p regs; |
struct sbic_acb* acb; |
struct sbic_acb *acb; |
int count, |
int count, asr, s; |
asr, |
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s; |
/* |
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* Only need to save pointers if DMA was active... |
/* |
*/ |
* Only need to save pointers if DMA was active... |
if (dev->sc_cur == NULL || (dev->sc_flags & SBICF_INDMA) == 0) |
*/ |
return; |
if ( dev->sc_cur == NULL || (dev->sc_flags & SBICF_INDMA) == 0 ) |
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return; |
regs = dev->sc_sbicp; |
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regs = dev->sc_sbicp; |
s = splbio(); |
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s = splbio(); |
/* |
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* Wait until WD chip is idle |
/* |
*/ |
* Wait until WD chip is idle |
do { |
*/ |
GET_SBIC_asr(regs, asr); |
do { |
if (asr & SBIC_ASR_DBR) { |
GET_SBIC_asr(regs, asr); |
printf("%s: asr %02x canceled!\n", __func__, asr); |
if( asr & SBIC_ASR_DBR ) { |
splx(s); |
printf("sbic_save_ptrs: asr %02x canceled!\n", asr); |
return; |
splx(s); |
} |
return; |
} while(asr & (SBIC_ASR_BSY|SBIC_ASR_CIP)); |
} |
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} while( asr & (SBIC_ASR_BSY|SBIC_ASR_CIP) ); |
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/* |
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* Save important state. |
/* |
* must be done before dmastop |
* Save important state. |
*/ |
* must be done before dmastop |
acb = dev->sc_nexus; |
*/ |
acb->sc_dmacmd = dev->sc_dmacmd; |
acb = dev->sc_nexus; |
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acb->sc_dmacmd = dev->sc_dmacmd; |
/* |
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* Fetch the residual count |
/* |
*/ |
* Fetch the residual count |
SBIC_TC_GET(regs, count); |
*/ |
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SBIC_TC_GET(regs, count); |
/* |
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* Shut down DMA |
/* |
*/ |
* Shut down DMA |
dev->sc_dmastop(dev); |
*/ |
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dev->sc_dmastop(dev); |
/* |
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* No longer in DMA |
/* |
*/ |
* No longer in DMA |
dev->sc_flags &= ~SBICF_INDMA; |
*/ |
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dev->sc_flags &= ~SBICF_INDMA; |
/* |
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* Ensure the WD chip is back in polled I/O mode, with nothing to |
/* |
* transfer. |
* Ensure the WD chip is back in polled I/O mode, with nothing to |
*/ |
* transfer. |
SBIC_TC_PUT(regs, 0); |
*/ |
SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); |
SBIC_TC_PUT(regs, 0); |
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SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); |
/* |
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* Update current count... |
/* |
*/ |
* Update current count... |
acb->sc_tcnt = count; |
*/ |
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acb->sc_tcnt = count; |
/* |
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* Work out how many bytes were actually transferred |
/* |
*/ |
* Work out how many bytes were actually transferred |
count = dev->sc_tcnt - count; |
*/ |
dev->sc_tcnt = acb->sc_tcnt; |
count = dev->sc_tcnt - count; |
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dev->sc_tcnt = acb->sc_tcnt; |
/* |
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* Fixup partial xfers |
/* |
*/ |
* Fixup partial xfers |
acb->sc_kv.dc_addr += count; |
*/ |
acb->sc_kv.dc_count -= count; |
acb->sc_kv.dc_addr += count; |
acb->sc_pa.dc_addr += count; |
acb->sc_kv.dc_count -= count; |
acb->sc_pa.dc_count -= count >> 1; |
acb->sc_pa.dc_addr += count; |
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acb->sc_pa.dc_count -= count >> 1; |
#ifdef DEBUG |
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if (data_pointer_debug) |
#ifdef DEBUG |
printf("save at (%p,%x):%x\n", |
if ( data_pointer_debug ) |
dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); |
printf("save at (%p,%x):%x\n", |
sbicdma_saves++; |
dev->sc_cur->dc_addr, dev->sc_cur->dc_count,count); |
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sbicdma_saves++; |
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#endif |
#endif |
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splx(s); |
splx(s); |
} |
} |
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Line 303 sbic_save_ptrs(dev) |
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Line 299 sbic_save_ptrs(dev) |
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* DOES NOT RESTART DMA!!! |
* DOES NOT RESTART DMA!!! |
*/ |
*/ |
void |
void |
sbic_load_ptrs(dev) |
sbic_load_ptrs(struct sbic_softc *dev) |
struct sbic_softc *dev; |
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{ |
{ |
struct sbic_acb *acb = dev->sc_nexus; |
struct sbic_acb *acb = dev->sc_nexus; |
int s; |
int s; |
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if ( acb->sc_kv.dc_count == 0 ) { |
if (acb->sc_kv.dc_count == 0) { |
/* |
/* |
* No data to xfer |
* No data to xfer |
*/ |
*/ |
return; |
return; |
} |
} |
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s = splbio(); |
s = splbio(); |
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/* |
/* |
* Reset the Scatter-Gather chain |
* Reset the Scatter-Gather chain |
*/ |
*/ |
dev->sc_last = dev->sc_cur = &acb->sc_pa; |
dev->sc_last = dev->sc_cur = &acb->sc_pa; |
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/* |
/* |
* Restore the Transfer Count and DMA specific data |
* Restore the Transfer Count and DMA specific data |
*/ |
*/ |
dev->sc_tcnt = acb->sc_tcnt; |
dev->sc_tcnt = acb->sc_tcnt; |
dev->sc_dmacmd = acb->sc_dmacmd; |
dev->sc_dmacmd = acb->sc_dmacmd; |
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#ifdef DEBUG |
#ifdef DEBUG |
sbicdma_ops++; |
sbicdma_ops++; |
#endif |
#endif |
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/* |
/* |
* Need to fixup new segment? |
* Need to fixup new segment? |
*/ |
*/ |
if ( dev->sc_tcnt == 0 ) { |
if (dev->sc_tcnt == 0) { |
/* |
/* |
* sc_tcnt == 0 implies end of segment |
* sc_tcnt == 0 implies end of segment |
*/ |
*/ |
char *vaddr, *paddr; |
char *vaddr, *paddr; |
int count; |
int count; |
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/* |
/* |
* do kvm to pa mappings |
* do kvm to pa mappings |
*/ |
*/ |
vaddr = acb->sc_kv.dc_addr; |
vaddr = acb->sc_kv.dc_addr; |
paddr = acb->sc_pa.dc_addr = (char *) kvtop((void *)vaddr); |
paddr = acb->sc_pa.dc_addr = (char *)kvtop((void *)vaddr); |
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for (count = (PAGE_SIZE - ((int)vaddr & PGOFSET)); |
for (count = (PAGE_SIZE - ((int)vaddr & PGOFSET)); |
count < acb->sc_kv.dc_count && |
count < acb->sc_kv.dc_count && |
(char*)kvtop((void *)(vaddr + count + 4)) == paddr + count + 4; |
(char *)kvtop((void *)(vaddr + count + 4)) == |
count += PAGE_SIZE) |
paddr + count + 4; |
; /* Do nothing */ |
count += PAGE_SIZE) |
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; /* Do nothing */ |
/* |
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* If it's all contiguous... |
/* |
*/ |
* If it's all contiguous... |
if ( count > acb->sc_kv.dc_count ) { |
*/ |
count = acb->sc_kv.dc_count; |
if (count > acb->sc_kv.dc_count) { |
#ifdef DEBUG |
count = acb->sc_kv.dc_count; |
sbicdma_hits++; |
#ifdef DEBUG |
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sbicdma_hits++; |
#endif |
#endif |
} |
} |
#ifdef DEBUG |
#ifdef DEBUG |
else |
else |
sbicdma_misses++; |
sbicdma_misses++; |
#endif |
#endif |
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acb->sc_tcnt = count; |
acb->sc_tcnt = count; |
acb->sc_pa.dc_count = count >> 1; |
acb->sc_pa.dc_count = count >> 1; |
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#ifdef DEBUG |
#ifdef DEBUG |
if ( data_pointer_debug ) |
if (data_pointer_debug) |
printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", acb->sc_kv.dc_addr, |
printf("DMA recalc:kv(%p,%x)pa(%p,%lx)\n", |
acb->sc_kv.dc_count, |
acb->sc_kv.dc_addr, |
acb->sc_pa.dc_addr, |
acb->sc_kv.dc_count, |
acb->sc_tcnt); |
acb->sc_pa.dc_addr, |
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acb->sc_tcnt); |
#endif |
#endif |
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} |
} |
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splx(s); |
splx(s); |
} |
} |
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/* |
/* |
Line 393 sbic_load_ptrs(dev) |
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Line 390 sbic_load_ptrs(dev) |
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* in scsi_scsipi_cmd(). |
* in scsi_scsipi_cmd(). |
*/ |
*/ |
void |
void |
sbic_scsi_request(chan, req, arg) |
sbic_scsi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, |
struct scsipi_channel *chan; |
void *arg) |
scsipi_adapter_req_t req; |
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void *arg; |
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{ |
{ |
struct scsipi_xfer *xs; |
struct scsipi_xfer *xs; |
struct scsipi_periph *periph; |
struct scsipi_periph *periph; |
struct sbic_softc *dev = (void *)chan->chan_adapter->adapt_dev; |
struct sbic_softc *dev = (void *)chan->chan_adapter->adapt_dev; |
struct sbic_acb *acb; |
struct sbic_acb *acb; |
int flags, s; |
int flags, s; |
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switch (req) { |
switch (req) { |
case ADAPTER_REQ_RUN_XFER: |
case ADAPTER_REQ_RUN_XFER: |
xs = arg; |
xs = arg; |
periph = xs->xs_periph; |
periph = xs->xs_periph; |
flags = xs->xs_control; |
flags = xs->xs_control; |
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if ( flags & XS_CTL_DATA_UIO ) |
if (flags & XS_CTL_DATA_UIO) |
panic("sbic: scsi data uio requested"); |
panic("sbic: scsi data uio requested"); |
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if ( dev->sc_nexus && (flags & XS_CTL_POLL) ) |
if (dev->sc_nexus && (flags & XS_CTL_POLL)) |
panic("sbic_scsicmd: busy"); |
panic("sbic_scsicmd: busy"); |
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s = splbio(); |
s = splbio(); |
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if ( (acb = dev->free_list.tqh_first) != NULL ) |
if ((acb = dev->free_list.tqh_first) != NULL) |
TAILQ_REMOVE(&dev->free_list, acb, chain); |
TAILQ_REMOVE(&dev->free_list, acb, chain); |
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splx(s); |
splx(s); |
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if ( acb == NULL ) { |
if (acb == NULL) { |
#ifdef DEBUG |
#ifdef DEBUG |
printf("sbic_scsicmd: unable to queue request for target %d\n", |
printf("%s: unable to queue request for target %d\n", |
periph->periph_target); |
__func__, periph->periph_target); |
#ifdef DDB |
#ifdef DDB |
Debugger(); |
Debugger(); |
#endif |
#endif |
#endif |
#endif |
xs->error = XS_RESOURCE_SHORTAGE; |
xs->error = XS_RESOURCE_SHORTAGE; |
scsipi_done(xs); |
scsipi_done(xs); |
return; |
return; |
} |
} |
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if ( flags & XS_CTL_DATA_IN ) |
if (flags & XS_CTL_DATA_IN) |
acb->flags = ACB_ACTIVE | ACB_DATAIN; |
acb->flags = ACB_ACTIVE | ACB_DATAIN; |
else |
else |
acb->flags = ACB_ACTIVE; |
acb->flags = ACB_ACTIVE; |
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acb->xs = xs; |
acb->xs = xs; |
acb->clen = xs->cmdlen; |
acb->clen = xs->cmdlen; |
acb->sc_kv.dc_addr = xs->data; |
acb->sc_kv.dc_addr = xs->data; |
acb->sc_kv.dc_count = xs->datalen; |
acb->sc_kv.dc_count = xs->datalen; |
acb->pa_addr = xs->data ? (char *)kvtop((void *)xs->data) : 0; |
acb->pa_addr = xs->data ? |
memcpy(&acb->cmd, xs->cmd, xs->cmdlen); |
(char *)kvtop((void *)xs->data) : 0; |
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memcpy(&acb->cmd, xs->cmd, xs->cmdlen); |
if ( flags & XS_CTL_POLL ) { |
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/* |
if (flags & XS_CTL_POLL) { |
* This has major side effects -- it locks up the machine |
/* |
*/ |
* This has major side effects |
int stat; |
* -- it locks up the machine |
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*/ |
s = splbio(); |
int stat; |
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dev->sc_flags |= SBICF_ICMD; |
s = splbio(); |
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do { |
dev->sc_flags |= SBICF_ICMD; |
/* |
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* If we already had a nexus, while away the time until idle... |
do { |
* This is likely only to happen if a reselection occurs between |
/* |
* here and our earlier check for ICMD && sc_nexus (which would |
* If we already had a nexus, while away |
* have resulted in a panic() had it been true). |
* the time until idle... |
*/ |
* This is likely only to happen if |
while ( dev->sc_nexus ) |
* a reselection occurs between |
sbicpoll(dev); |
* here and our earlier check for |
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* ICMD && sc_nexus(which would |
/* |
* have resulted in a panic() had it been true). |
* Fix up the new nexus |
*/ |
*/ |
while (dev->sc_nexus) |
dev->sc_nexus = acb; |
sbicpoll(dev); |
dev->sc_xs = xs; |
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dev->target = periph->periph_target; |
/* |
dev->lun = periph->periph_lun; |
* Fix up the new nexus |
|
*/ |
stat = sbicicmd(dev, &acb->cmd, acb->clen, |
dev->sc_nexus = acb; |
acb->sc_kv.dc_addr, acb->sc_kv.dc_count); |
dev->sc_xs = xs; |
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dev->target = periph->periph_target; |
} while ( dev->sc_nexus != acb ); |
dev->lun = periph->periph_lun; |
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sbic_scsidone(acb, stat); |
stat = sbicicmd(dev, &acb->cmd, acb->clen, |
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acb->sc_kv.dc_addr, acb->sc_kv.dc_count); |
splx(s); |
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} while (dev->sc_nexus != acb); |
return; |
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} |
sbic_scsidone(acb, stat); |
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s = splbio(); |
splx(s); |
TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); |
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return; |
/* |
} |
* If nothing is active, try to start it now. |
|
*/ |
s = splbio(); |
if ( dev->sc_nexus == NULL ) |
TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); |
sbic_sched(dev); |
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/* |
splx(s); |
* If nothing is active, try to start it now. |
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*/ |
return; |
if (dev->sc_nexus == NULL) |
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sbic_sched(dev); |
case ADAPTER_REQ_GROW_RESOURCES: |
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/* XXX Not supported. */ |
splx(s); |
return; |
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return; |
case ADAPTER_REQ_SET_XFER_MODE: |
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/* XXX Not supported. */ |
case ADAPTER_REQ_GROW_RESOURCES: |
return; |
/* XXX Not supported. */ |
} |
return; |
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case ADAPTER_REQ_SET_XFER_MODE: |
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/* XXX Not supported. */ |
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return; |
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} |
} |
} |
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/* |
/* |
* attempt to start the next available command |
* attempt to start the next available command |
*/ |
*/ |
void |
void |
sbic_sched(dev) |
sbic_sched(struct sbic_softc *dev) |
struct sbic_softc *dev; |
|
{ |
{ |
struct scsipi_xfer *xs; |
struct scsipi_xfer *xs; |
struct scsipi_periph *periph = NULL; /* Gag the compiler */ |
struct scsipi_periph *periph = NULL; /* Gag the compiler */ |
struct sbic_acb *acb; |
struct sbic_acb *acb; |
int flags, |
int flags, stat; |
stat; |
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/* |
/* |
* XXXSCW |
* XXXSCW |
* I'll keep this test here, even though I can't see any obvious way |
* I'll keep this test here, even though I can't see any obvious way |
* in which sbic_sched() could be called with sc_nexus non NULL |
* in which sbic_sched() could be called with sc_nexus non NULL |
*/ |
*/ |
if (dev->sc_nexus) |
if ( dev->sc_nexus ) |
return; /* a command is current active */ |
return; /* a command is current active */ |
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/* |
/* |
* Loop through the ready list looking for work to do... |
* Loop through the ready list looking for work to do... |
*/ |
*/ |
for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { |
for (acb = dev->ready_list.tqh_first; acb; acb = acb->chain.tqe_next) { |
int i, j; |
int i, j; |
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periph = acb->xs->xs_periph; |
periph = acb->xs->xs_periph; |
i = periph->periph_target; |
i = periph->periph_target; |
j = 1 << periph->periph_lun; |
j = 1 << periph->periph_lun; |
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/* |
/* |
* We've found a potential command, but is the target/lun busy? |
* We've found a potential command, but is the target/lun busy? |
*/ |
*/ |
if ((dev->sc_tinfo[i].lubusy & j) == 0) { |
if ( (dev->sc_tinfo[i].lubusy & j) == 0 ) { |
/* |
/* |
* Nope, it's not busy, so we can use it. |
* Nope, it's not busy, so we can use it. |
*/ |
*/ |
dev->sc_tinfo[i].lubusy |= j; |
dev->sc_tinfo[i].lubusy |= j; |
TAILQ_REMOVE(&dev->ready_list, acb, chain); |
TAILQ_REMOVE(&dev->ready_list, acb, chain); |
dev->sc_nexus = acb; |
dev->sc_nexus = acb; |
acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ |
acb->sc_pa.dc_addr = acb->pa_addr; /* XXXX check */ |
break; |
break; |
} |
} |
} |
} |
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|
if (acb == NULL) { |
if ( acb == NULL ) { |
QPRINTF(("sbicsched: no work\n")); |
QPRINTF(("sbicsched: no work\n")); |
return; /* did not find an available command */ |
return; /* did not find an available command */ |
} |
} |
|
|
#ifdef DEBUG |
#ifdef DEBUG |
if (data_pointer_debug > 1) |
if ( data_pointer_debug > 1 ) |
printf("sbic_sched(%d,%d)\n", periph->periph_target, |
printf("sbic_sched(%d,%d)\n", periph->periph_target, |
periph->periph_lun); |
periph->periph_lun); |
#endif |
#endif |
|
|
dev->sc_xs = xs = acb->xs; |
dev->sc_xs = xs = acb->xs; |
flags = xs->xs_control; |
flags = xs->xs_control; |
|
|
if (flags & XS_CTL_RESET) |
if ( flags & XS_CTL_RESET ) |
sbicreset(dev); |
sbicreset(dev); |
|
|
dev->sc_stat[0] = -1; |
dev->sc_stat[0] = -1; |
dev->target = periph->periph_target; |
dev->target = periph->periph_target; |
dev->lun = periph->periph_lun; |
dev->lun = periph->periph_lun; |
|
|
if (flags & XS_CTL_POLL || (!sbic_parallel_operations && |
if ( flags & XS_CTL_POLL || (!sbic_parallel_operations && |
(sbicdmaok(dev, xs) == 0)) ) |
(sbicdmaok(dev, xs) == 0)) ) |
stat = sbicicmd(dev, &acb->cmd, acb->clen, |
stat = sbicicmd(dev, &acb->cmd, acb->clen, |
acb->sc_kv.dc_addr, acb->sc_kv.dc_count); |
acb->sc_kv.dc_addr, acb->sc_kv.dc_count); |
else if (sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT) |
else |
return; |
if ( sbicgo(dev, xs) == 0 && xs->error != XS_SELTIMEOUT ) |
else |
return; |
stat = dev->sc_stat[0]; |
else |
|
stat = dev->sc_stat[0]; |
|
|
|
sbic_scsidone(acb, stat); |
sbic_scsidone(acb, stat); |
} |
} |
|
|
void |
void |
sbic_scsidone(acb, stat) |
sbic_scsidone(struct sbic_acb *acb, int stat) |
struct sbic_acb *acb; |
{ |
int stat; |
struct scsipi_xfer *xs = acb->xs; |
{ |
struct scsipi_periph *periph = xs->xs_periph; |
struct scsipi_xfer *xs = acb->xs; |
struct sbic_softc *dev = |
struct scsipi_periph *periph = xs->xs_periph; |
(void *)periph->periph_channel->chan_adapter->adapt_dev; |
struct sbic_softc *dev = (void *)periph->periph_channel->chan_adapter->adapt_dev; |
int dosched = 0; |
int dosched = 0; |
|
|
|
#ifdef DIAGNOSTIC |
#ifdef DIAGNOSTIC |
if ( acb == NULL || xs == NULL ) { |
if (acb == NULL || xs == NULL) { |
printf("sbic_scsidone -- (%d,%d) no scsipi_xfer\n", dev->target, dev->lun); |
printf("sbic_scsidone -- (%d,%d) no scsipi_xfer\n", |
|
dev->target, dev->lun); |
#ifdef DDB |
#ifdef DDB |
Debugger(); |
Debugger(); |
#endif |
#endif |
return; |
return; |
} |
} |
#endif |
#endif |
|
|
|
|
#ifdef DEBUG |
#ifdef DEBUG |
if ( data_pointer_debug > 1 ) |
if (data_pointer_debug > 1) |
printf("scsidone: (%d,%d)->(%d,%d)%02x\n", periph->periph_target, |
printf("scsidone: (%d,%d)->(%d,%d)%02x\n", |
periph->periph_lun, |
periph->periph_target, periph->periph_lun, |
dev->target, dev->lun, stat); |
dev->target, dev->lun, stat); |
|
|
if ( xs->xs_periph->periph_target == dev->sc_channel.chan_id) |
if (xs->xs_periph->periph_target == dev->sc_channel.chan_id) |
panic("target == hostid"); |
panic("target == hostid"); |
#endif |
#endif |
|
|
xs->status = stat; |
xs->status = stat; |
xs->resid = 0; /* XXXX */ |
xs->resid = 0; /* XXXX */ |
if ( xs->error == XS_NOERROR) { |
if (xs->error == XS_NOERROR) { |
if ( stat == SCSI_CHECK || stat == SCSI_BUSY) |
if (stat == SCSI_CHECK || stat == SCSI_BUSY) |
xs->error = XS_BUSY; |
xs->error = XS_BUSY; |
} |
} |
|
|
|
|
/* |
/* |
* Remove the ACB from whatever queue it's on. We have to do a bit of |
* Remove the ACB from whatever queue it's on. We have to do a bit of |
* a hack to figure out which queue it's on. Note that it is *not* |
* a hack to figure out which queue it's on. Note that it is *not* |
* necessary to cdr down the ready queue, but we must cdr down the |
* necessary to cdr down the ready queue, but we must cdr down the |
* nexus queue and see if it's there, so we can mark the unit as no |
* nexus queue and see if it's there, so we can mark the unit as no |
* longer busy. This code is sickening, but it works. |
* longer busy. This code is sickening, but it works. |
*/ |
*/ |
if ( acb == dev->sc_nexus ) { |
if (acb == dev->sc_nexus ) { |
|
|
dev->sc_nexus = NULL; |
dev->sc_nexus = NULL; |
dev->sc_xs = NULL; |
dev->sc_xs = NULL; |
|
|
dev->sc_tinfo[periph->periph_target].lubusy &= |
dev->sc_tinfo[periph->periph_target].lubusy &= |
~(1 << periph->periph_lun); |
~(1 << periph->periph_lun); |
|
|
if ( dev->ready_list.tqh_first ) |
if (dev->ready_list.tqh_first) |
dosched = 1; /* start next command */ |
dosched = 1; /* start next command */ |
|
|
} else |
} else if (dev->ready_list.tqh_last == &acb->chain.tqe_next) { |
if ( dev->ready_list.tqh_last == &acb->chain.tqe_next ) { |
|
|
|
TAILQ_REMOVE(&dev->ready_list, acb, chain); |
TAILQ_REMOVE(&dev->ready_list, acb, chain); |
|
|
} else { |
} else { |
|
|
struct sbic_acb *a; |
struct sbic_acb *a; |
|
|
for (a = dev->nexus_list.tqh_first; a; a = a->chain.tqe_next) { |
for (a = dev->nexus_list.tqh_first; a != NULL; |
if ( a == acb ) { |
a = a->chain.tqe_next) { |
TAILQ_REMOVE(&dev->nexus_list, acb, chain); |
if (a == acb) { |
dev->sc_tinfo[periph->periph_target].lubusy &= |
TAILQ_REMOVE(&dev->nexus_list, acb, chain); |
~(1 << periph->periph_lun); |
dev->sc_tinfo[periph->periph_target].lubusy &= |
break; |
~(1 << periph->periph_lun); |
} |
break; |
} |
} |
|
} |
|
|
if ( a ) |
if (a != NULL) |
; |
; |
else if ( acb->chain.tqe_next ) { |
else if ( acb->chain.tqe_next ) { |
TAILQ_REMOVE(&dev->ready_list, acb, chain); |
TAILQ_REMOVE(&dev->ready_list, acb, chain); |
} else { |
} else { |
printf("%s: can't find matching acb\n", dev->sc_dev.dv_xname); |
printf("%s: can't find matching acb\n", |
|
dev->sc_dev.dv_xname); |
#ifdef DDB |
#ifdef DDB |
Debugger(); |
Debugger(); |
#endif |
#endif |
} |
} |
} |
} |
|
|
/* |
/* |
* Put it on the free list. |
* Put it on the free list. |
*/ |
*/ |
acb->flags = ACB_FREE; |
acb->flags = ACB_FREE; |
TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); |
TAILQ_INSERT_HEAD(&dev->free_list, acb, chain); |
|
|
dev->sc_tinfo[periph->periph_target].cmds++; |
dev->sc_tinfo[periph->periph_target].cmds++; |
|
|
scsipi_done(xs); |
scsipi_done(xs); |
|
|
if ( dosched ) |
if (dosched) |
sbic_sched(dev); |
sbic_sched(dev); |
} |
} |
|
|
int |
int |
sbicdmaok(dev, xs) |
sbicdmaok(struct sbic_softc *dev, struct scsipi_xfer *xs) |
struct sbic_softc *dev; |
{ |
struct scsipi_xfer *xs; |
|
{ |
|
if ( sbic_no_dma || xs->datalen == 0 || |
|
xs->datalen & 0x03 || (int)xs->data & 0x03) |
|
return(0); |
|
|
|
/* |
|
* controller supports DMA to any addresses? |
|
*/ |
|
if ( (dev->sc_flags & SBICF_BADDMA) == 0 ) |
|
return(1); |
|
|
|
/* |
|
* this address is ok for DMA? |
|
*/ |
|
if ( sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0 ) |
|
return(1); |
|
|
|
return(0); |
if (sbic_no_dma || xs->datalen == 0 || |
|
xs->datalen & 0x03 || (int)xs->data & 0x03) |
|
return 0; |
|
|
|
/* |
|
* controller supports DMA to any addresses? |
|
*/ |
|
if ((dev->sc_flags & SBICF_BADDMA) == 0) |
|
return 1; |
|
|
|
/* |
|
* this address is ok for DMA? |
|
*/ |
|
if (sbiccheckdmap(xs->data, xs->datalen, dev->sc_dmamask) == 0) |
|
return 1; |
|
|
|
return 0; |
} |
} |
|
|
int |
int |
sbicwait(regs, until, timeo, line) |
sbicwait(sbic_regmap_p regs, u_char until, int timeo, int line) |
sbic_regmap_p regs; |
|
u_char until; |
|
int timeo; |
|
int line; |
|
{ |
{ |
u_char val; |
u_char val; |
|
|
if ( timeo == 0 ) |
if (timeo == 0) |
timeo = 1000000; /* some large value.. */ |
timeo = 1000000; /* some large value.. */ |
|
|
GET_SBIC_asr(regs, val); |
GET_SBIC_asr(regs, val); |
|
|
while ( (val & until) == 0 ) { |
while ((val & until) == 0) { |
|
|
if ( timeo-- == 0 ) { |
if (timeo-- == 0) { |
int csr; |
int csr; |
GET_SBIC_csr(regs, csr); |
GET_SBIC_csr(regs, csr); |
printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", line, val, csr); |
printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n", |
|
line, val, csr); |
#if defined(DDB) && defined(DEBUG) |
#if defined(DDB) && defined(DEBUG) |
Debugger(); |
Debugger(); |
#endif |
#endif |
return(val); /* Maybe I should abort */ |
return val; /* Maybe I should abort */ |
break; |
break; |
} |
} |
|
|
DELAY(1); |
DELAY(1); |
GET_SBIC_asr(regs, val); |
GET_SBIC_asr(regs, val); |
} |
} |
|
|
return(val); |
return val; |
} |
} |
|
|
int |
int |
sbicabort(dev, where) |
sbicabort(struct sbic_softc *dev, const char *where) |
struct sbic_softc *dev; |
{ |
const char *where; |
sbic_regmap_p regs = dev->sc_sbicp; |
{ |
u_char csr, asr; |
sbic_regmap_p regs = dev->sc_sbicp; |
|
u_char csr, |
GET_SBIC_asr(regs, asr); |
asr; |
GET_SBIC_csr(regs, csr); |
|
|
GET_SBIC_asr(regs, asr); |
|
GET_SBIC_csr(regs, csr); |
|
|
|
printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", |
|
dev->sc_dev.dv_xname, where, csr, asr); |
|
|
|
/* |
|
* Clean up chip itself |
|
*/ |
|
if ( dev->sc_flags & SBICF_SELECTED ) { |
|
|
|
while ( asr & SBIC_ASR_DBR ) { |
|
/* |
|
* sbic is jammed w/data. need to clear it |
|
* But we don't know what direction it needs to go |
|
*/ |
|
GET_SBIC_data(regs, asr); |
|
printf("%s: abort %s: clearing data buffer 0x%02x\n", |
|
dev->sc_dev.dv_xname, where, asr); |
|
GET_SBIC_asr(regs, asr); |
|
if ( asr & SBIC_ASR_DBR ) /* Not the read direction, then */ |
|
SET_SBIC_data(regs, asr); |
|
GET_SBIC_asr(regs, asr); |
|
} |
|
|
|
WAIT_CIP(regs); |
|
|
|
printf("%s: sbicabort - sending ABORT command\n", dev->sc_dev.dv_xname); |
|
SET_SBIC_cmd(regs, SBIC_CMD_ABORT); |
|
WAIT_CIP(regs); |
|
|
|
GET_SBIC_asr(regs, asr); |
|
|
|
if ( asr & (SBIC_ASR_BSY|SBIC_ASR_LCI) ) { |
|
/* |
|
* ok, get more drastic.. |
|
*/ |
|
printf("%s: sbicabort - asr %x, trying to reset\n", |
|
dev->sc_dev.dv_xname, asr); |
|
sbicreset(dev); |
|
dev->sc_flags &= ~SBICF_SELECTED; |
|
return SBIC_STATE_ERROR; |
|
} |
|
|
|
printf("%s: sbicabort - sending DISC command\n", dev->sc_dev.dv_xname); |
|
SET_SBIC_cmd(regs, SBIC_CMD_DISC); |
|
|
|
do { |
|
SBIC_WAIT (regs, SBIC_ASR_INT, 0); |
|
GET_SBIC_asr(regs, asr); |
|
GET_SBIC_csr (regs, csr); |
|
QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr)); |
|
} while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && |
|
(csr != SBIC_CSR_CMD_INVALID) ); |
|
|
|
/* |
|
* lets just hope it worked.. |
|
*/ |
|
dev->sc_flags &= ~SBICF_SELECTED; |
|
} |
|
|
|
return SBIC_STATE_ERROR; |
printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n", |
|
dev->sc_dev.dv_xname, where, csr, asr); |
|
|
|
/* |
|
* Clean up chip itself |
|
*/ |
|
if (dev->sc_flags & SBICF_SELECTED) { |
|
|
|
while (asr & SBIC_ASR_DBR) { |
|
/* |
|
* sbic is jammed w/data. need to clear it |
|
* But we don't know what direction it needs to go |
|
*/ |
|
GET_SBIC_data(regs, asr); |
|
printf("%s: abort %s: clearing data buffer 0x%02x\n", |
|
dev->sc_dev.dv_xname, where, asr); |
|
GET_SBIC_asr(regs, asr); |
|
if (asr & SBIC_ASR_DBR) |
|
/* Not the read direction, then */ |
|
SET_SBIC_data(regs, asr); |
|
GET_SBIC_asr(regs, asr); |
|
} |
|
|
|
WAIT_CIP(regs); |
|
|
|
printf("%s: sbicabort - sending ABORT command\n", |
|
dev->sc_dev.dv_xname); |
|
SET_SBIC_cmd(regs, SBIC_CMD_ABORT); |
|
WAIT_CIP(regs); |
|
|
|
GET_SBIC_asr(regs, asr); |
|
|
|
if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { |
|
/* |
|
* ok, get more drastic.. |
|
*/ |
|
printf("%s: sbicabort - asr %x, trying to reset\n", |
|
dev->sc_dev.dv_xname, asr); |
|
sbicreset(dev); |
|
dev->sc_flags &= ~SBICF_SELECTED; |
|
return SBIC_STATE_ERROR; |
|
} |
|
|
|
printf("%s: sbicabort - sending DISC command\n", |
|
dev->sc_dev.dv_xname); |
|
SET_SBIC_cmd(regs, SBIC_CMD_DISC); |
|
|
|
do { |
|
SBIC_WAIT (regs, SBIC_ASR_INT, 0); |
|
GET_SBIC_asr(regs, asr); |
|
GET_SBIC_csr (regs, csr); |
|
QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr)); |
|
} while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && |
|
(csr != SBIC_CSR_CMD_INVALID)); |
|
|
|
/* |
|
* lets just hope it worked.. |
|
*/ |
|
dev->sc_flags &= ~SBICF_SELECTED; |
|
} |
|
|
|
return SBIC_STATE_ERROR; |
} |
} |
|
|
|
|
Line 829 sbicabort(dev, where) |
|
Line 822 sbicabort(dev, where) |
|
* Initialize driver-private structures |
* Initialize driver-private structures |
*/ |
*/ |
void |
void |
sbicinit(dev) |
sbicinit(struct sbic_softc *dev) |
struct sbic_softc *dev; |
|
{ |
{ |
u_int i; |
u_int i; |
|
|
if ( (dev->sc_flags & SBICF_ALIVE) == 0 ) { |
if ((dev->sc_flags & SBICF_ALIVE) == 0) { |
|
|
struct sbic_acb *acb; |
struct sbic_acb *acb; |
|
|
TAILQ_INIT(&dev->ready_list); |
TAILQ_INIT(&dev->ready_list); |
TAILQ_INIT(&dev->nexus_list); |
TAILQ_INIT(&dev->nexus_list); |
TAILQ_INIT(&dev->free_list); |
TAILQ_INIT(&dev->free_list); |
callout_init(&dev->sc_timo_ch, 0); |
callout_init(&dev->sc_timo_ch, 0); |
|
|
dev->sc_nexus = NULL; |
dev->sc_nexus = NULL; |
dev->sc_xs = NULL; |
dev->sc_xs = NULL; |
|
|
acb = dev->sc_acb; |
acb = dev->sc_acb; |
memset(acb, 0, sizeof(dev->sc_acb)); |
memset(acb, 0, sizeof(dev->sc_acb)); |
|
|
for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { |
for (i = 0; i < sizeof(dev->sc_acb) / sizeof(*acb); i++) { |
TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); |
TAILQ_INSERT_TAIL(&dev->free_list, acb, chain); |
acb++; |
acb++; |
} |
} |
|
|
memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); |
memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); |
|
|
#ifdef DEBUG |
#ifdef DEBUG |
/* |
/* |
* make sure timeout is really not needed |
* make sure timeout is really not needed |
*/ |
*/ |
callout_reset(&dev->sc_timo_ch, 30 * hz, (void *)sbictimeout, dev); |
callout_reset(&dev->sc_timo_ch, 30 * hz, |
|
(void *)sbictimeout, dev); |
#endif |
#endif |
|
|
} else |
} else |
panic("sbic: reinitializing driver!"); |
panic("sbic: reinitializing driver!"); |
|
|
dev->sc_flags |= SBICF_ALIVE; |
dev->sc_flags |= SBICF_ALIVE; |
dev->sc_flags &= ~SBICF_SELECTED; |
dev->sc_flags &= ~SBICF_SELECTED; |
|
|
/* |
/* |
* initialize inhibit array |
* initialize inhibit array |
* Never enable Sync, since it just doesn't work on mvme147 :( |
* Never enable Sync, since it just doesn't work on mvme147 :( |
*/ |
*/ |
for (i = 0; i < 8; ++i) |
for (i = 0; i < 8; ++i) |
sbic_inhibit_sync[i] = 1; |
sbic_inhibit_sync[i] = 1; |
|
|
sbicreset(dev); |
sbicreset(dev); |
} |
} |
|
|
void |
void |
sbicreset(dev) |
sbicreset(struct sbic_softc *dev) |
struct sbic_softc *dev; |
|
{ |
{ |
sbic_regmap_p regs = dev->sc_sbicp; |
sbic_regmap_p regs = dev->sc_sbicp; |
u_int my_id, |
u_int my_id, s; |
s; |
u_char csr; |
u_char csr; |
|
|
s = splbio(); |
s = splbio(); |
|
|
my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; |
my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; |
|
|
if (dev->sc_clkfreq < 110) |
if (dev->sc_clkfreq < 110) |
my_id |= SBIC_ID_FS_8_10; |
my_id |= SBIC_ID_FS_8_10; |
else if (dev->sc_clkfreq < 160) |
else if (dev->sc_clkfreq < 160) |
my_id |= SBIC_ID_FS_12_15; |
my_id |= SBIC_ID_FS_12_15; |
else if (dev->sc_clkfreq < 210) |
else if (dev->sc_clkfreq < 210) |
my_id |= SBIC_ID_FS_16_20; |
my_id |= SBIC_ID_FS_16_20; |
|
|
SET_SBIC_myid(regs, my_id); |
SET_SBIC_myid(regs, my_id); |
|
|
/* |
/* |
* Reset the chip |
* Reset the chip |
*/ |
*/ |
SET_SBIC_cmd(regs, SBIC_CMD_RESET); |
SET_SBIC_cmd(regs, SBIC_CMD_RESET); |
DELAY(25); |
DELAY(25); |
|
|
SBIC_WAIT(regs, SBIC_ASR_INT, 0); |
SBIC_WAIT(regs, SBIC_ASR_INT, 0); |
GET_SBIC_csr(regs, csr); /* clears interrupt also */ |
GET_SBIC_csr(regs, csr); /* clears interrupt also */ |
|
|
/* |
/* |
* Set up various chip parameters |
* Set up various chip parameters |
*/ |
*/ |
SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); |
SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); |
|
|
/* |
/* |
* don't allow Selection (SBIC_RID_ES) |
* don't allow Selection (SBIC_RID_ES) |
* until we can handle target mode!! |
* until we can handle target mode!! |
*/ |
*/ |
SET_SBIC_rselid(regs, SBIC_RID_ER); |
SET_SBIC_rselid(regs, SBIC_RID_ER); |
|
|
/* |
/* |
* Asynchronous for now |
* Asynchronous for now |
*/ |
*/ |
SET_SBIC_syn(regs, 0); |
SET_SBIC_syn(regs, 0); |
|
|
/* |
/* |
* Anything else was zeroed by reset |
* Anything else was zeroed by reset |
*/ |
*/ |
splx(s); |
splx(s); |
|
|
|
dev->sc_flags &= ~SBICF_SELECTED; |
dev->sc_flags &= ~SBICF_SELECTED; |
} |
} |
|
|
void |
void |
sbicerror(dev, csr) |
sbicerror(struct sbic_softc *dev, u_char csr) |
struct sbic_softc *dev; |
|
u_char csr; |
|
{ |
{ |
struct scsipi_xfer *xs = dev->sc_xs; |
struct scsipi_xfer *xs = dev->sc_xs; |
|
|
#ifdef DIAGNOSTIC |
#ifdef DIAGNOSTIC |
if ( xs == NULL ) |
if (xs == NULL) |
panic("sbicerror: dev->sc_xs == NULL"); |
panic("sbicerror: dev->sc_xs == NULL"); |
#endif |
#endif |
|
|
if ( xs->xs_control & XS_CTL_SILENT ) |
if ( xs->xs_control & XS_CTL_SILENT ) |
return; |
return; |
|
|
printf("%s: csr == 0x%02x\n", dev->sc_dev.dv_xname, csr); |
printf("%s: csr == 0x%02x\n", dev->sc_dev.dv_xname, csr); |
} |
} |
|
|
/* |
/* |
Line 960 sbicerror(dev, csr) |
|
Line 949 sbicerror(dev, csr) |
|
* If the return value is 0, some error happened. |
* If the return value is 0, some error happened. |
*/ |
*/ |
u_char |
u_char |
sbicselectbus(dev) |
sbicselectbus(struct sbic_softc *dev) |
struct sbic_softc *dev; |
|
{ |
{ |
sbic_regmap_p regs = dev->sc_sbicp; |
sbic_regmap_p regs = dev->sc_sbicp; |
u_char target = dev->target, |
u_char target = dev->target, lun = dev->lun, asr, csr, id; |
lun = dev->lun, |
|
asr, |
/* |
csr, |
* if we're already selected, return (XXXX panic maybe?) |
id; |
*/ |
|
if (dev->sc_flags & SBICF_SELECTED) |
/* |
return 0; |
* if we're already selected, return (XXXX panic maybe?) |
|
*/ |
QPRINTF(("sbicselectbus %d: ", target)); |
if ( dev->sc_flags & SBICF_SELECTED ) |
|
return(0); |
/* |
|
* issue select |
QPRINTF(("sbicselectbus %d: ", target)); |
*/ |
|
SET_SBIC_selid(regs, target); |
/* |
SET_SBIC_timeo(regs, SBIC_TIMEOUT(250, dev->sc_clkfreq)); |
* issue select |
|
*/ |
GET_SBIC_asr(regs, asr); |
SET_SBIC_selid(regs, target); |
|
SET_SBIC_timeo(regs, SBIC_TIMEOUT(250, dev->sc_clkfreq)); |
if (asr & (SBIC_ASR_INT|SBIC_ASR_BSY)) { |
|
/* |
GET_SBIC_asr(regs, asr); |
* This means we got ourselves reselected upon |
|
*/ |
if ( asr & (SBIC_ASR_INT|SBIC_ASR_BSY) ) { |
QPRINTF(("WD busy (reselect?)\n")); |
/* |
return 0; |
* This means we got ourselves reselected upon |
} |
*/ |
|
QPRINTF(("WD busy (reselect?)\n")); |
SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); |
return 0; |
|
} |
/* |
|
* wait for select (merged from separate function may need |
SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN); |
* cleanup) |
|
*/ |
/* |
WAIT_CIP(regs); |
* wait for select (merged from separate function may need |
|
* cleanup) |
do { |
*/ |
|
WAIT_CIP(regs); |
asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); |
|
|
do { |
if (asr & SBIC_ASR_LCI) { |
|
QPRINTF(("late LCI: asr %02x\n", asr)); |
asr = SBIC_WAIT(regs, SBIC_ASR_INT | SBIC_ASR_LCI, 0); |
return 0; |
|
} |
if ( asr & SBIC_ASR_LCI ) { |
|
QPRINTF(("late LCI: asr %02x\n", asr)); |
/* |
return 0; |
* Clear interrupt |
} |
*/ |
|
GET_SBIC_csr (regs, csr); |
/* |
|
* Clear interrupt |
QPRINTF(("%02x ", csr)); |
*/ |
|
GET_SBIC_csr (regs, csr); |
/* |
|
* Reselected from under our feet? |
QPRINTF(("%02x ", csr)); |
*/ |
|
if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { |
/* |
QPRINTF(("got reselected, asr %02x\n", asr)); |
* Reselected from under our feet? |
/* |
*/ |
* We need to handle this now so we don't lock up later |
if ( csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY ) { |
*/ |
QPRINTF(("got reselected, asr %02x\n", asr)); |
sbicnextstate(dev, csr, asr); |
/* |
|
* We need to handle this now so we don't lock up later |
return 0; |
*/ |
} |
sbicnextstate(dev, csr, asr); |
|
|
/* |
return 0; |
* Whoops! |
} |
*/ |
|
if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { |
/* |
panic("sbicselectbus: target issued select!"); |
* Whoops! |
return 0; |
*/ |
} |
if ( csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN ) { |
|
panic("sbicselectbus: target issued select!"); |
} while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && |
return 0; |
csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && |
} |
csr != SBIC_CSR_SEL_TIMEO); |
|
|
} while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && |
/* |
csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && |
* Anyone at home? |
csr != SBIC_CSR_SEL_TIMEO); |
*/ |
|
if (csr == SBIC_CSR_SEL_TIMEO) { |
/* |
dev->sc_xs->error = XS_SELTIMEOUT; |
* Anyone at home? |
QPRINTF(("Selection Timeout\n")); |
*/ |
return 0; |
if ( csr == SBIC_CSR_SEL_TIMEO ) { |
} |
dev->sc_xs->error = XS_SELTIMEOUT; |
|
QPRINTF(("Selection Timeout\n")); |
QPRINTF(("Selection Complete\n")); |
return 0; |
|
} |
/* |
|
* Assume we're now selected |
QPRINTF(("Selection Complete\n")); |
*/ |
|
GET_SBIC_selid(regs, id); |
/* |
dev->target = id; |
* Assume we're now selected |
dev->lun = lun; |
*/ |
dev->sc_flags |= SBICF_SELECTED; |
GET_SBIC_selid(regs, id); |
|
dev->target = id; |
/* |
dev->lun = lun; |
* Enable (or not) reselection |
dev->sc_flags |= SBICF_SELECTED; |
* XXXSCW This is probably not necessary since we don't use use the |
|
* Select-and-Xfer-with-ATN command to initiate a selection... |
/* |
*/ |
* Enable (or not) reselection |
if (!sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) |
* XXXSCW This is probably not necessary since we don't use use the |
SET_SBIC_rselid (regs, 0); |
* Select-and-Xfer-with-ATN command to initiate a selection... |
else |
*/ |
SET_SBIC_rselid (regs, SBIC_RID_ER); |
if ( !sbic_enable_reselect && dev->nexus_list.tqh_first == NULL) |
|
SET_SBIC_rselid (regs, 0); |
/* |
else |
* We only really need to do anything when the target goes to MSG out |
SET_SBIC_rselid (regs, SBIC_RID_ER); |
* If the device ignored ATN, it's probably old and brain-dead, |
|
* but we'll try to support it anyhow. |
/* |
* If it doesn't support message out, it definately doesn't |
* We only really need to do anything when the target goes to MSG out |
* support synchronous transfers, so no point in even asking... |
* If the device ignored ATN, it's probably old and brain-dead, |
*/ |
* but we'll try to support it anyhow. |
if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) { |
* If it doesn't support message out, it definately doesn't |
/* |
* support synchronous transfers, so no point in even asking... |
* Send identify message (SCSI-2 requires an identify msg) |
*/ |
*/ |
if ( csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) ) { |
if (sbic_inhibit_sync[id] && |
/* |
dev->sc_sync[id].state == SYNC_START) { |
* Send identify message (SCSI-2 requires an identify msg) |
/* |
*/ |
* Handle drives that don't want to be asked |
if ( sbic_inhibit_sync[id] && dev->sc_sync[id].state == SYNC_START ) { |
* whether to go sync at all. |
/* |
*/ |
* Handle drives that don't want to be asked |
dev->sc_sync[id].offset = 0; |
* whether to go sync at all. |
dev->sc_sync[id].period = sbic_min_period; |
*/ |
dev->sc_sync[id].state = SYNC_DONE; |
dev->sc_sync[id].offset = 0; |
} |
dev->sc_sync[id].period = sbic_min_period; |
|
dev->sc_sync[id].state = SYNC_DONE; |
/* |
} |
* Do we need to negotiate Synchronous Xfers for this target? |
|
*/ |
/* |
if (dev->sc_sync[id].state != SYNC_START) { |
* Do we need to negotiate Synchronous Xfers for this target? |
/* |
*/ |
* Nope, we've already negotiated. |
if ( dev->sc_sync[id].state != SYNC_START ) { |
* Now see if we should allow the target to |
/* |
* disconnect/reselect... |
* Nope, we've already negotiated. |
*/ |
* Now see if we should allow the target to disconnect/reselect... |
if (dev->sc_xs->xs_control & XS_CTL_POLL || |
*/ |
dev->sc_flags & SBICF_ICMD || |
if ( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || |
!sbic_enable_reselect) |
!sbic_enable_reselect ) |
SEND_BYTE (regs, MSG_IDENTIFY | lun); |
SEND_BYTE (regs, MSG_IDENTIFY | lun); |
else |
else |
SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); |
SEND_BYTE (regs, MSG_IDENTIFY_DR | lun); |
|
|
} else { |
} else { |
/* |
/* |
* try to initiate a sync transfer. |
* try to initiate a sync transfer. |
* So compose the sync message we're going |
* So compose the sync message we're going |
* to send to the target |
* to send to the target |
*/ |
*/ |
#ifdef DEBUG |
#ifdef DEBUG |
if (sync_debug) |
if ( sync_debug ) |
printf("\nSending sync request " |
printf("\nSending sync request to target %d ... ", id); |
"to target %d ... ", id); |
#endif |
#endif |
/* |
/* |
* setup scsi message sync message request |
* setup scsi message sync message request |
*/ |
*/ |
dev->sc_msg[0] = MSG_IDENTIFY | lun; |
dev->sc_msg[0] = MSG_IDENTIFY | lun; |
dev->sc_msg[1] = MSG_EXT_MESSAGE; |
dev->sc_msg[1] = MSG_EXT_MESSAGE; |
dev->sc_msg[2] = 3; |
dev->sc_msg[2] = 3; |
dev->sc_msg[3] = MSG_SYNC_REQ; |
dev->sc_msg[3] = MSG_SYNC_REQ; |
dev->sc_msg[4] = sbictoscsiperiod(dev, sbic_min_period); |
dev->sc_msg[4] = sbictoscsiperiod(dev, sbic_min_period); |
dev->sc_msg[5] = sbic_max_offset; |
dev->sc_msg[5] = sbic_max_offset; |
|
|
sbicxfout(regs, 6, dev->sc_msg); |
sbicxfout(regs, 6, dev->sc_msg); |
|
|
dev->sc_sync[id].state = SYNC_SENT; |
dev->sc_sync[id].state = SYNC_SENT; |
#ifdef DEBUG |
#ifdef DEBUG |
if ( sync_debug ) |
if (sync_debug) |
printf ("sent\n"); |
printf ("sent\n"); |
#endif |
#endif |
} |
} |
|
|
/* |
/* |
* There's one interrupt still to come: the change to CMD phase... |
* There's one interrupt still to come: the change to |
*/ |
* CMD phase... |
SBIC_WAIT(regs, SBIC_ASR_INT , 0); |
*/ |
GET_SBIC_csr(regs, csr); |
SBIC_WAIT(regs, SBIC_ASR_INT , 0); |
} |
GET_SBIC_csr(regs, csr); |
|
} |
/* |
|
* set sync or async |
/* |
*/ |
* set sync or async |
if ( dev->sc_sync[target].state == SYNC_DONE ) { |
*/ |
|
if (dev->sc_sync[target].state == SYNC_DONE) { |
#ifdef DEBUG |
#ifdef DEBUG |
if ( sync_debug ) |
if (sync_debug) |
printf("select(%d): sync reg = 0x%02x\n", target, |
printf("select(%d): sync reg = 0x%02x\n", target, |
SBIC_SYN(dev->sc_sync[target].offset, |
SBIC_SYN(dev->sc_sync[target].offset, |
dev->sc_sync[target].period)); |
dev->sc_sync[target].period)); |
#endif |
#endif |
SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, |
SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[target].offset, |
dev->sc_sync[target].period)); |
dev->sc_sync[target].period)); |
} else { |
} else { |
#ifdef DEBUG |
#ifdef DEBUG |
if ( sync_debug ) |
if (sync_debug) |
printf("select(%d): sync reg = 0x%02x\n", target, |
printf("select(%d): sync reg = 0x%02x\n", target, |
SBIC_SYN(0,sbic_min_period)); |
SBIC_SYN(0,sbic_min_period)); |
#endif |
#endif |
SET_SBIC_syn(regs, SBIC_SYN(0, sbic_min_period)); |
SET_SBIC_syn(regs, SBIC_SYN(0, sbic_min_period)); |
} |
} |
|
|
return csr; |
return csr; |
} |
} |
|
|
/* |
/* |
Line 1182 sbicselectbus(dev) |
|
Line 1171 sbicselectbus(dev) |
|
* since we don't allow disconnection for them (yet). |
* since we don't allow disconnection for them (yet). |
*/ |
*/ |
int |
int |
sbicxfout(regs, len, bp) |
sbicxfout(sbic_regmap_p regs, int len, void *bp) |
sbic_regmap_p regs; |
{ |
int len; |
int wait = sbic_data_wait; |
void *bp; |
u_char asr, *buf = bp; |
{ |
|
int wait = sbic_data_wait; |
QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " |
u_char asr, |
"%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], |
*buf = bp; |
buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); |
|
|
QPRINTF(("sbicxfout {%d} %02x %02x %02x %02x %02x " |
/* |
"%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], |
* sigh.. WD-PROTO strikes again.. sending the command in one go |
buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); |
* causes the chip to lock up if talking to certain (misbehaving?) |
|
* targets. Anyway, this procedure should work for all targets, but |
/* |
* it's slightly slower due to the overhead |
* sigh.. WD-PROTO strikes again.. sending the command in one go |
*/ |
* causes the chip to lock up if talking to certain (misbehaving?) |
WAIT_CIP (regs); |
* targets. Anyway, this procedure should work for all targets, but |
|
* it's slightly slower due to the overhead |
SBIC_TC_PUT (regs, 0); |
*/ |
SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); |
WAIT_CIP (regs); |
SBIC_TC_PUT (regs, (unsigned)len); |
|
SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); |
SBIC_TC_PUT (regs, 0); |
|
SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); |
/* |
SBIC_TC_PUT (regs, (unsigned)len); |
* Loop for each byte transferred |
SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); |
*/ |
|
do { |
/* |
|
* Loop for each byte transferred |
GET_SBIC_asr(regs, asr); |
*/ |
|
do { |
if (asr & SBIC_ASR_DBR) { |
|
if (len) { |
GET_SBIC_asr (regs, asr); |
SET_SBIC_data (regs, *buf); |
|
buf++; |
if ( asr & SBIC_ASR_DBR ) { |
len--; |
if ( len ) { |
} else { |
SET_SBIC_data (regs, *buf); |
SET_SBIC_data (regs, 0); |
buf++; |
} |
len--; |
wait = sbic_data_wait; |
} else { |
} |
SET_SBIC_data (regs, 0); |
|
} |
|
wait = sbic_data_wait; |
|
} |
|
|
|
} while ( len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); |
} while (len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0); |
|
|
#ifdef DEBUG |
#ifdef DEBUG |
QPRINTF(("sbicxfout done: %d bytes remaining (wait:%d)\n", len, wait)); |
QPRINTF(("sbicxfout done: %d bytes remaining (wait:%d)\n", len, wait)); |
#endif |
#endif |
|
|
/* |
/* |
* Normally, an interrupt will be pending when this routing returns. |
* Normally, an interrupt will be pending when this routing returns. |
*/ |
*/ |
return(len); |
return len; |
} |
} |
|
|
/* |
/* |
Line 1243 sbicxfout(regs, len, bp) |
|
Line 1228 sbicxfout(regs, len, bp) |
|
* returns # bytes left to read |
* returns # bytes left to read |
*/ |
*/ |
int |
int |
sbicxfin(regs, len, bp) |
sbicxfin(sbic_regmap_p regs, int len, void *bp) |
sbic_regmap_p regs; |
{ |
int len; |
int wait = sbic_data_wait; |
void *bp; |
u_char *buf = bp; |
{ |
u_char asr; |
int wait = sbic_data_wait; |
|
u_char *buf = bp; |
|
u_char asr; |
|
#ifdef DEBUG |
#ifdef DEBUG |
u_char *obp = bp; |
u_char *obp = bp; |
#endif |
#endif |
|
|
WAIT_CIP (regs); |
WAIT_CIP(regs); |
|
|
SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); |
SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); |
SBIC_TC_PUT (regs, (unsigned)len); |
SBIC_TC_PUT(regs, (unsigned int)len); |
SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); |
SET_SBIC_cmd (regs, SBIC_CMD_XFER_INFO); |
|
|
/* |
/* |
* Loop for each byte transferred |
* Loop for each byte transferred |
*/ |
*/ |
do { |
do { |
|
|
GET_SBIC_asr (regs, asr); |
GET_SBIC_asr(regs, asr); |
|
|
if ( asr & SBIC_ASR_DBR ) { |
if (asr & SBIC_ASR_DBR) { |
if ( len ) { |
if (len) { |
GET_SBIC_data (regs, *buf); |
GET_SBIC_data (regs, *buf); |
buf++; |
buf++; |
len--; |
len--; |
} else { |
} else { |
u_char foo; |
u_char foo; |
GET_SBIC_data (regs, foo); |
GET_SBIC_data (regs, foo); |
} |
} |
wait = sbic_data_wait; |
wait = sbic_data_wait; |
} |
} |
|
|
} while ( (asr & SBIC_ASR_INT) == 0 && wait-- > 0 ); |
} while ((asr & SBIC_ASR_INT) == 0 && wait-- > 0); |
|
|
QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " |
QPRINTF(("sbicxfin {%d} %02x %02x %02x %02x %02x %02x " |
"%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], |
"%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], |
obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); |
obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); |
|
|
SBIC_TC_PUT (regs, 0); |
SBIC_TC_PUT (regs, 0); |
|
|
/* |
/* |
* this leaves with one csr to be read |
* this leaves with one csr to be read |
*/ |
*/ |
return len; |
return len; |
} |
} |
|
|
/* |
/* |
Line 1308 sbicxfin(regs, len, bp) |
|
Line 1290 sbicxfin(regs, len, bp) |
|
* done to clean this lot up. |
* done to clean this lot up. |
*/ |
*/ |
int |
int |
sbicicmd(dev, cbuf, clen, buf, len) |
sbicicmd(struct sbic_softc *dev, void *cbuf, int clen, void *buf, int len) |
struct sbic_softc *dev; |
{ |
void *cbuf, |
sbic_regmap_p regs = dev->sc_sbicp; |
*buf; |
struct sbic_acb *acb = dev->sc_nexus; |
int clen, |
u_char csr, asr; |
len; |
int still_busy = SBIC_STATE_RUNNING; |
{ |
|
sbic_regmap_p regs = dev->sc_sbicp; |
/* |
struct sbic_acb *acb = dev->sc_nexus; |
* Make sure pointers are OK |
u_char csr, |
*/ |
asr; |
dev->sc_last = dev->sc_cur = &acb->sc_pa; |
int still_busy = SBIC_STATE_RUNNING; |
dev->sc_tcnt = acb->sc_tcnt = 0; |
|
|
/* |
acb->sc_dmacmd = 0; |
* Make sure pointers are OK |
acb->sc_pa.dc_count = 0; /* No DMA */ |
*/ |
acb->sc_kv.dc_addr = buf; |
dev->sc_last = dev->sc_cur = &acb->sc_pa; |
acb->sc_kv.dc_count = len; |
dev->sc_tcnt = acb->sc_tcnt = 0; |
|
|
|
acb->sc_dmacmd = 0; |
|
acb->sc_pa.dc_count = 0; /* No DMA */ |
|
acb->sc_kv.dc_addr = buf; |
|
acb->sc_kv.dc_count = len; |
|
|
|
#ifdef DEBUG |
#ifdef DEBUG |
if ( data_pointer_debug > 1 ) |
if (data_pointer_debug > 1) |
printf("sbicicmd(%d,%d):%d\n", dev->target, dev->lun, acb->sc_kv.dc_count); |
printf("sbicicmd(%d,%d):%d\n", |
#endif |
dev->target, dev->lun, acb->sc_kv.dc_count); |
|
#endif |
/* |
|
* set the sbic into non-DMA mode |
/* |
*/ |
* set the sbic into non-DMA mode |
SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); |
*/ |
|
SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); |
dev->sc_stat[0] = 0xff; |
|
dev->sc_msg[0] = 0xff; |
dev->sc_stat[0] = 0xff; |
|
dev->sc_msg[0] = 0xff; |
/* |
|
* We're stealing the SCSI bus |
/* |
*/ |
* We're stealing the SCSI bus |
dev->sc_flags |= SBICF_ICMD; |
*/ |
|
dev->sc_flags |= SBICF_ICMD; |
do { |
|
GET_SBIC_asr (regs, asr); |
do { |
|
GET_SBIC_asr(regs, asr); |
/* |
|
* select the SCSI bus (it's an error if bus isn't free) |
/* |
*/ |
* select the SCSI bus (it's an error if bus isn't free) |
if ( (dev->sc_flags & SBICF_SELECTED) == 0 && |
*/ |
still_busy != SBIC_STATE_DISCONNECT ) { |
if ((dev->sc_flags & SBICF_SELECTED) == 0 && |
if ( (csr = sbicselectbus(dev)) == 0 ) { |
still_busy != SBIC_STATE_DISCONNECT) { |
dev->sc_flags &= ~SBICF_ICMD; |
if ((csr = sbicselectbus(dev)) == 0) { |
return(-1); |
dev->sc_flags &= ~SBICF_ICMD; |
} |
return -1; |
} else |
} |
if ( (asr & (SBIC_ASR_BSY | SBIC_ASR_INT)) == SBIC_ASR_INT ) |
} else if ((asr & (SBIC_ASR_BSY | SBIC_ASR_INT)) == |
GET_SBIC_csr(regs, csr); |
SBIC_ASR_INT) |
else |
GET_SBIC_csr(regs, csr); |
csr = 0; |
else |
|
csr = 0; |
if ( csr ) { |
|
|
if (csr) { |
QPRINTF((">ASR:0x%02x CSR:0x%02x< ", asr, csr)); |
|
|
QPRINTF((">ASR:0x%02x CSR:0x%02x< ", asr, csr)); |
switch ( csr ) { |
|
|
switch (csr) { |
case SBIC_CSR_S_XFERRED: |
|
case SBIC_CSR_DISC: |
case SBIC_CSR_S_XFERRED: |
case SBIC_CSR_DISC_1: |
case SBIC_CSR_DISC: |
{ |
case SBIC_CSR_DISC_1: |
u_char phase; |
{ |
|
u_char phase; |
dev->sc_flags &= ~SBICF_SELECTED; |
|
GET_SBIC_cmd_phase (regs, phase); |
dev->sc_flags &= ~SBICF_SELECTED; |
|
GET_SBIC_cmd_phase(regs, phase); |
if ( phase == 0x60 ) { |
|
GET_SBIC_tlun (regs, dev->sc_stat[0]); |
if (phase == 0x60) { |
still_busy = SBIC_STATE_DONE; /* done */ |
GET_SBIC_tlun(regs, dev->sc_stat[0]); |
} else { |
still_busy = SBIC_STATE_DONE; /* done */ |
#ifdef DEBUG |
} else { |
if ( reselect_debug > 1 ) |
#ifdef DEBUG |
printf("sbicicmd: handling disconnect\n"); |
if (reselect_debug > 1) |
#endif |
printf("sbicicmd: " |
still_busy = SBIC_STATE_DISCONNECT; |
"handling disconnect\n"); |
} |
#endif |
} |
still_busy = SBIC_STATE_DISCONNECT; |
break; |
} |
|
break; |
case SBIC_CSR_XFERRED | CMD_PHASE: |
} |
case SBIC_CSR_MIS | CMD_PHASE: |
|
case SBIC_CSR_MIS_1 | CMD_PHASE: |
case SBIC_CSR_XFERRED | CMD_PHASE: |
case SBIC_CSR_MIS_2 | CMD_PHASE: |
case SBIC_CSR_MIS | CMD_PHASE: |
{ |
case SBIC_CSR_MIS_1 | CMD_PHASE: |
if ( sbicxfout(regs, clen, cbuf) ) |
case SBIC_CSR_MIS_2 | CMD_PHASE: |
still_busy = sbicabort(dev, "icmd sending cmd"); |
|
} |
if (sbicxfout(regs, clen, cbuf)) |
break; |
still_busy = sbicabort(dev, |
|
"icmd sending cmd"); |
case SBIC_CSR_XFERRED | STATUS_PHASE: |
break; |
case SBIC_CSR_MIS | STATUS_PHASE: |
|
case SBIC_CSR_MIS_1 | STATUS_PHASE: |
case SBIC_CSR_XFERRED | STATUS_PHASE: |
case SBIC_CSR_MIS_2 | STATUS_PHASE: |
case SBIC_CSR_MIS | STATUS_PHASE: |
{ |
case SBIC_CSR_MIS_1 | STATUS_PHASE: |
/* |
case SBIC_CSR_MIS_2 | STATUS_PHASE: |
* The sbic does the status/cmd-complete reading ok, |
|
* so do this with its hi-level commands. |
/* |
*/ |
* The sbic does the status/cmd-complete |
#ifdef DEBUG |
* reading ok, so do this with its |
if ( sbic_debug ) |
* hi-level commands. |
printf("SBICICMD status phase (bsy=%d)\n", still_busy); |
*/ |
#endif |
#ifdef DEBUG |
SET_SBIC_cmd_phase(regs, 0x46); |
if (sbic_debug) |
SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); |
printf("SBICICMD status phase " |
} |
"(bsy=%d)\n", still_busy); |
break; |
#endif |
|
SET_SBIC_cmd_phase(regs, 0x46); |
default: |
SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); |
{ |
break; |
still_busy = sbicnextstate(dev, csr, asr); |
|
} |
default: |
break; |
still_busy = sbicnextstate(dev, csr, asr); |
} |
break; |
|
} |
/* |
|
* make sure the last command was taken, |
/* |
* ie. we're not hunting after an ignored command.. |
* make sure the last command was taken, |
*/ |
* ie. we're not hunting after an ignored command.. |
GET_SBIC_asr(regs, asr); |
*/ |
|
GET_SBIC_asr(regs, asr); |
/* |
|
* tapes may take a loooong time.. |
/* |
*/ |
* tapes may take a loooong time.. |
while (asr & SBIC_ASR_BSY ) { |
*/ |
|
while (asr & SBIC_ASR_BSY) { |
if ( asr & SBIC_ASR_DBR ) { |
|
int i; |
if (asr & SBIC_ASR_DBR) { |
|
int i; |
printf("sbicicmd: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); |
|
|
printf("sbicicmd: " |
|
"Waiting while sbic is jammed, " |
|
"CSR:%02x,ASR:%02x\n", csr, asr); |
#ifdef DDB |
#ifdef DDB |
Debugger(); |
Debugger(); |
#endif |
#endif |
/* |
/* |
* SBIC is jammed |
* SBIC is jammed |
* DUNNO which direction |
* DUNNO which direction |
* Try old direction |
* Try old direction |
*/ |
*/ |
GET_SBIC_data(regs, i); |
GET_SBIC_data(regs, i); |
GET_SBIC_asr(regs, asr); |
GET_SBIC_asr(regs, asr); |
|
|
if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ |
if (asr & SBIC_ASR_DBR) |
SET_SBIC_data(regs, i); |
/* Wants us to write */ |
} |
SET_SBIC_data(regs, i); |
|
} |
GET_SBIC_asr(regs, asr); |
|
} |
GET_SBIC_asr(regs, asr); |
} |
} |
|
} |
/* |
|
* wait for last command to complete |
/* |
*/ |
* wait for last command to complete |
if ( asr & SBIC_ASR_LCI ) { |
*/ |
printf("sbicicmd: last command ignored\n"); |
if (asr & SBIC_ASR_LCI) { |
} |
printf("sbicicmd: last command ignored\n"); |
else |
} else if (still_busy >= SBIC_STATE_RUNNING) /* Bsy */ |
if ( still_busy >= SBIC_STATE_RUNNING ) /* Bsy */ |
SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); |
SBIC_WAIT (regs, SBIC_ASR_INT, sbic_cmd_wait); |
|
|
/* |
/* |
* do it again |
* do it again |
*/ |
*/ |
} while (still_busy >= SBIC_STATE_RUNNING && dev->sc_stat[0] == 0xff); |
} while ( still_busy >= SBIC_STATE_RUNNING && dev->sc_stat[0] == 0xff ); |
|
|
/* |
/* |
* Sometimes we need to do an extra read of the CSR |
* Sometimes we need to do an extra read of the CSR |
*/ |
*/ |
GET_SBIC_csr(regs, csr); |
GET_SBIC_csr(regs, csr); |
|
|
#ifdef DEBUG |
#ifdef DEBUG |
if (data_pointer_debug > 1) |
if ( data_pointer_debug > 1 ) |
printf("sbicicmd done(%d,%d):%d =%d=\n", dev->target, dev->lun, |
printf("sbicicmd done(%d,%d):%d =%d=\n", dev->target, dev->lun, |
acb->sc_kv.dc_count, dev->sc_stat[0]); |
acb->sc_kv.dc_count, |
|
dev->sc_stat[0]); |
|
#endif |
#endif |
|
|
dev->sc_flags &= ~SBICF_ICMD; |
dev->sc_flags &= ~SBICF_ICMD; |
|
|
return(dev->sc_stat[0]); |
return dev->sc_stat[0]; |
} |
} |
|
|
/* |
/* |
Line 1504 sbicicmd(dev, cbuf, clen, buf, len) |
|
Line 1481 sbicicmd(dev, cbuf, clen, buf, len) |
|
* skip (and don't allow) the select, cmd out and data in/out phases. |
* skip (and don't allow) the select, cmd out and data in/out phases. |
*/ |
*/ |
void |
void |
sbicxfdone(dev) |
sbicxfdone(struct sbic_softc *dev) |
struct sbic_softc *dev; |
|
{ |
{ |
sbic_regmap_p regs = dev->sc_sbicp; |
sbic_regmap_p regs = dev->sc_sbicp; |
u_char phase, |
u_char phase, csr; |
csr; |
int s; |
int s; |
|
|
|
QPRINTF(("{")); |
QPRINTF(("{")); |
s = splbio(); |
s = splbio(); |
|
|
/* |
/* |
* have the sbic complete on its own |
* have the sbic complete on its own |
*/ |
*/ |
SBIC_TC_PUT(regs, 0); |
SBIC_TC_PUT(regs, 0); |
SET_SBIC_cmd_phase(regs, 0x46); |
SET_SBIC_cmd_phase(regs, 0x46); |
SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); |
SET_SBIC_cmd(regs, SBIC_CMD_SEL_ATN_XFER); |
|
|
do { |
do { |
|
|
SBIC_WAIT (regs, SBIC_ASR_INT, 0); |
SBIC_WAIT(regs, SBIC_ASR_INT, 0); |
GET_SBIC_csr (regs, csr); |
GET_SBIC_csr(regs, csr); |
QPRINTF(("%02x:", csr)); |
QPRINTF(("%02x:", csr)); |
|
|
} while ( (csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && |
} while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) && |
(csr != SBIC_CSR_S_XFERRED)); |
(csr != SBIC_CSR_S_XFERRED)); |
|
|
dev->sc_flags &= ~SBICF_SELECTED; |
dev->sc_flags &= ~SBICF_SELECTED; |
|
|
GET_SBIC_cmd_phase (regs, phase); |
GET_SBIC_cmd_phase (regs, phase); |
QPRINTF(("}%02x", phase)); |
QPRINTF(("}%02x", phase)); |
|
|
if ( phase == 0x60 ) |
if (phase == 0x60) |
GET_SBIC_tlun(regs, dev->sc_stat[0]); |
GET_SBIC_tlun(regs, dev->sc_stat[0]); |
else |
else |
sbicerror(dev, csr); |
sbicerror(dev, csr); |
|
|
QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); |
QPRINTF(("=STS:%02x=\n", dev->sc_stat[0])); |
|
|
splx(s); |
splx(s); |
} |
} |
|
|
/* |
/* |
* No DMA chains |
* No DMA chains |
*/ |
*/ |
int |
int |
sbicgo(dev, xs) |
sbicgo(struct sbic_softc *dev, struct scsipi_xfer *xs) |
struct sbic_softc *dev; |
{ |
struct scsipi_xfer *xs; |
struct sbic_acb *acb = dev->sc_nexus; |
{ |
sbic_regmap_p regs = dev->sc_sbicp; |
struct sbic_acb *acb = dev->sc_nexus; |
int i, dmaflags, count, usedma; |
sbic_regmap_p regs = dev->sc_sbicp; |
u_char csr, asr, *addr; |
int i, |
|
dmaflags, |
dev->target = xs->xs_periph->periph_target; |
count, |
dev->lun = xs->xs_periph->periph_lun; |
usedma; |
|
u_char csr, |
usedma = sbicdmaok(dev, xs); |
asr, |
|
*addr; |
#ifdef DEBUG |
|
if (data_pointer_debug > 1) |
dev->target = xs->xs_periph->periph_target; |
printf("sbicgo(%d,%d): usedma=%d\n", |
dev->lun = xs->xs_periph->periph_lun; |
dev->target, dev->lun, usedma); |
|
#endif |
usedma = sbicdmaok(dev, xs); |
|
|
/* |
#ifdef DEBUG |
* select the SCSI bus (it's an error if bus isn't free) |
if ( data_pointer_debug > 1 ) |
*/ |
printf("sbicgo(%d,%d): usedma=%d\n", dev->target, dev->lun, usedma); |
if ((csr = sbicselectbus(dev)) == 0) |
#endif |
return 0; /* Not done: needs to be rescheduled */ |
|
|
/* |
dev->sc_stat[0] = 0xff; |
* select the SCSI bus (it's an error if bus isn't free) |
|
*/ |
/* |
if ( (csr = sbicselectbus(dev)) == 0 ) |
* Calculate DMA chains now |
return(0); /* Not done: needs to be rescheduled */ |
*/ |
|
if (acb->flags & ACB_DATAIN) |
dev->sc_stat[0] = 0xff; |
dmaflags = DMAGO_READ; |
|
else |
/* |
dmaflags = 0; |
* Calculate DMA chains now |
|
*/ |
addr = acb->sc_kv.dc_addr; |
if ( acb->flags & ACB_DATAIN ) |
count = acb->sc_kv.dc_count; |
dmaflags = DMAGO_READ; |
|
else |
if (count && ((char *)kvtop((void *)addr) != acb->sc_pa.dc_addr)) { |
dmaflags = 0; |
printf("sbic: DMA buffer mapping changed %p->%x\n", |
|
acb->sc_pa.dc_addr, kvtop((void *)addr)); |
addr = acb->sc_kv.dc_addr; |
|
count = acb->sc_kv.dc_count; |
|
|
|
if ( count && ((char *)kvtop((void *)addr) != acb->sc_pa.dc_addr) ) { |
|
printf("sbic: DMA buffer mapping changed %p->%x\n", |
|
acb->sc_pa.dc_addr, kvtop((void *)addr)); |
|
#ifdef DDB |
#ifdef DDB |
Debugger(); |
Debugger(); |
#endif |
#endif |
} |
} |
|
|
#ifdef DEBUG |
#ifdef DEBUG |
++sbicdma_ops; /* count total DMA operations */ |
++sbicdma_ops; /* count total DMA operations */ |
#endif |
#endif |
|
|
/* |
/* |
* Allocate the DMA chain |
* Allocate the DMA chain |
* Mark end of segment... |
* Mark end of segment... |
*/ |
*/ |
acb->sc_tcnt = dev->sc_tcnt = 0; |
acb->sc_tcnt = dev->sc_tcnt = 0; |
acb->sc_pa.dc_count = 0; |
acb->sc_pa.dc_count = 0; |
|
|
sbic_load_ptrs(dev); |
sbic_load_ptrs(dev); |
|
|
/* |
/* |
* Enable interrupts but don't do any DMA |
* Enable interrupts but don't do any DMA |
* enintr() also enables interrupts for the sbic |
* enintr() also enables interrupts for the sbic |
*/ |
*/ |
dev->sc_enintr(dev); |
dev->sc_enintr(dev); |
|
|
if ( usedma ) { |
if (usedma) { |
dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, |
dev->sc_tcnt = dev->sc_dmago(dev, acb->sc_pa.dc_addr, |
acb->sc_pa.dc_count, dmaflags); |
acb->sc_pa.dc_count, dmaflags); |
#ifdef DEBUG |
#ifdef DEBUG |
dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; |
dev->sc_dmatimo = dev->sc_tcnt ? 1 : 0; |
#endif |
#endif |
} else |
} else |
dev->sc_dmacmd = 0; /* Don't use DMA */ |
dev->sc_dmacmd = 0; /* Don't use DMA */ |
|
|
acb->sc_dmacmd = dev->sc_dmacmd; |
acb->sc_dmacmd = dev->sc_dmacmd; |
|
|
#ifdef DEBUG |
#ifdef DEBUG |
if ( data_pointer_debug > 1 ) { |
if (data_pointer_debug > 1) { |
printf("sbicgo dmago:%d(%p:%lx) dmacmd=0x%02x\n", dev->target, |
printf("sbicgo dmago:%d(%p:%lx) dmacmd=0x%02x\n", dev->target, |
dev->sc_cur->dc_addr, |
dev->sc_cur->dc_addr, |
dev->sc_tcnt, |
dev->sc_tcnt, |
dev->sc_dmacmd); |
dev->sc_dmacmd); |
} |
} |
#endif |
#endif |
|
|
/* |
/* |
* Lets cycle a while then let the interrupt handler take over. |
* Lets cycle a while then let the interrupt handler take over. |
*/ |
*/ |
GET_SBIC_asr(regs, asr); |
GET_SBIC_asr(regs, asr); |
|
|
do { |
do { |
|
|
QPRINTF(("go ")); |
QPRINTF(("go ")); |
|
|
/* |
/* |
* Handle the new phase |
* Handle the new phase |
*/ |
*/ |
i = sbicnextstate(dev, csr, asr); |
i = sbicnextstate(dev, csr, asr); |
#if 0 |
#if 0 |
WAIT_CIP(regs); |
WAIT_CIP(regs); |
#endif |
#endif |
if ( i == SBIC_STATE_RUNNING ) { |
if (i == SBIC_STATE_RUNNING) { |
GET_SBIC_asr(regs, asr); |
GET_SBIC_asr(regs, asr); |
|
|
if ( asr & SBIC_ASR_LCI ) |
if (asr & SBIC_ASR_LCI) |
printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); |
printf("sbicgo: LCI asr:%02x csr:%02x\n", |
|
asr, csr); |
|
|
if ( asr & SBIC_ASR_INT ) |
if (asr & SBIC_ASR_INT) |
GET_SBIC_csr(regs, csr); |
GET_SBIC_csr(regs, csr); |
} |
} |
|
|
} while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); |
} while (i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); |
|
|
if ( i == SBIC_STATE_DONE ) { |
if (i == SBIC_STATE_DONE) { |
if ( dev->sc_stat[0] == 0xff ) |
if (dev->sc_stat[0] == 0xff) |
#if 0 |
#if 0 |
printf("sbicgo: done & stat = 0xff\n"); |
printf("sbicgo: done & stat = 0xff\n"); |
#else |
#else |
; |
; |
#endif |
#endif |
else |
else |
return 1; /* Did we really finish that fast? */ |
return 1; /* Did we really finish that fast? */ |
} |
} |
|
|
return 0; |
return 0; |
} |
} |
|
|
|
|
int |
int |
sbicintr(dev) |
sbicintr(struct sbic_softc *dev) |
struct sbic_softc *dev; |
|
{ |
{ |
sbic_regmap_p regs = dev->sc_sbicp; |
sbic_regmap_p regs = dev->sc_sbicp; |
u_char asr, |
u_char asr, csr; |
csr; |
int i; |
int i; |
|
|
|
/* |
/* |
* pending interrupt? |
* pending interrupt? |
*/ |
*/ |
GET_SBIC_asr (regs, asr); |
GET_SBIC_asr (regs, asr); |
if ( (asr & SBIC_ASR_INT) == 0 ) |
if ((asr & SBIC_ASR_INT) == 0) |
return(0); |
return 0; |
|
|
GET_SBIC_csr(regs, csr); |
GET_SBIC_csr(regs, csr); |
|
|
do { |
do { |
|
|
QPRINTF(("intr[0x%x]", csr)); |
QPRINTF(("intr[0x%x]", csr)); |
|
|
i = sbicnextstate(dev, csr, asr); |
i = sbicnextstate(dev, csr, asr); |
#if 0 |
#if 0 |
WAIT_CIP(regs); |
WAIT_CIP(regs); |
#endif |
#endif |
if ( i == SBIC_STATE_RUNNING ) { |
if (i == SBIC_STATE_RUNNING) { |
GET_SBIC_asr(regs, asr); |
GET_SBIC_asr(regs, asr); |
|
|
if ( asr & SBIC_ASR_LCI ) |
if (asr & SBIC_ASR_LCI) |
printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); |
printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr); |
|
|
if ( asr & SBIC_ASR_INT ) |
if (asr & SBIC_ASR_INT) |
GET_SBIC_csr(regs, csr); |
GET_SBIC_csr(regs, csr); |
} |
} |
|
|
} while ( i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI) ); |
} while (i == SBIC_STATE_RUNNING && asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); |
|
|
QPRINTF(("intr done. state=%d, asr=0x%02x\n", i, asr)); |
QPRINTF(("intr done. state=%d, asr=0x%02x\n", i, asr)); |
|
|
return(1); |
return 1; |
} |
} |
|
|
/* |
/* |
|
|
* want to busy wait for it to finish. |
* want to busy wait for it to finish. |
*/ |
*/ |
int |
int |
sbicpoll(dev) |
sbicpoll(struct sbic_softc *dev) |
struct sbic_softc *dev; |
|
{ |
{ |
sbic_regmap_p regs = dev->sc_sbicp; |
sbic_regmap_p regs = dev->sc_sbicp; |
u_char asr, |
u_char asr, csr = SBIC_CSR_RESET; /* XXX: Quell un-init warning */ |
csr = SBIC_CSR_RESET; /* XXX: Quell un-init warning */ |
int i; |
int i; |
|
|
/* |
/* |
* Wait for the next interrupt |
* Wait for the next interrupt |
*/ |
*/ |
SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); |
SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); |
|
|
do { |
do { |
GET_SBIC_asr (regs, asr); |
GET_SBIC_asr (regs, asr); |
|
|
if (asr & SBIC_ASR_INT) |
if ( asr & SBIC_ASR_INT ) |
GET_SBIC_csr(regs, csr); |
GET_SBIC_csr(regs, csr); |
|
|
QPRINTF(("poll[0x%x]", csr)); |
QPRINTF(("poll[0x%x]", csr)); |
|
|
/* |
/* |
* Handle it |
* Handle it |
*/ |
*/ |
i = sbicnextstate(dev, csr, asr); |
i = sbicnextstate(dev, csr, asr); |
|
|
WAIT_CIP(regs); |
WAIT_CIP(regs); |
GET_SBIC_asr(regs, asr); |
GET_SBIC_asr(regs, asr); |
|
|
/* |
/* |
* tapes may take a loooong time.. |
* tapes may take a loooong time.. |
*/ |
*/ |
while (asr & SBIC_ASR_BSY) { |
while ( asr & SBIC_ASR_BSY ) { |
u_char z = 0; |
u_char z = 0; |
|
|
if (asr & SBIC_ASR_DBR) { |
if ( asr & SBIC_ASR_DBR ) { |
printf("sbipoll: Waiting while sbic is jammed," |
printf("sbipoll: Waiting while sbic is jammed, CSR:%02x,ASR:%02x\n", csr,asr); |
" CSR:%02x,ASR:%02x\n", csr, asr); |
#ifdef DDB |
#ifdef DDB |
Debugger(); |
Debugger(); |
#endif |
#endif |
/* |
/* |
* SBIC is jammed |
* SBIC is jammed |
* DUNNO which direction |
* DUNNO which direction |
* Try old direction |
* Try old direction |
*/ |
*/ |
GET_SBIC_data(regs, z); |
GET_SBIC_data(regs, z); |
GET_SBIC_asr(regs, asr); |
GET_SBIC_asr(regs, asr); |
|
|
if ( asr & SBIC_ASR_DBR ) /* Wants us to write */ |
if (asr & SBIC_ASR_DBR) /* Wants us to write */ |
SET_SBIC_data(regs, z); |
SET_SBIC_data(regs, z); |
} |
} |
|
|
GET_SBIC_asr(regs, asr); |
GET_SBIC_asr(regs, asr); |
} |
} |
|
|
if ( asr & SBIC_ASR_LCI ) |
if (asr & SBIC_ASR_LCI) |
printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr); |
printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr); |
else |
else if (i == SBIC_STATE_RUNNING) /* BSY */ |
if ( i == SBIC_STATE_RUNNING ) /* BSY */ |
SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); |
SBIC_WAIT(regs, SBIC_ASR_INT, sbic_cmd_wait); |
|
|
|
} while ( i == SBIC_STATE_RUNNING ); |
} while (i == SBIC_STATE_RUNNING); |
|
|
return(1); |
return 1; |
} |
} |
|
|
/* |
/* |
* Handle a single msgin |
* Handle a single msgin |
*/ |
*/ |
int |
int |
sbicmsgin(dev) |
sbicmsgin(struct sbic_softc *dev) |
struct sbic_softc *dev; |
|
{ |
{ |
sbic_regmap_p regs = dev->sc_sbicp; |
sbic_regmap_p regs = dev->sc_sbicp; |
int recvlen = 1; |
int recvlen = 1; |
u_char asr, |
u_char asr, csr, *tmpaddr, *msgaddr; |
csr, |
|
*tmpaddr, |
tmpaddr = msgaddr = dev->sc_msg; |
*msgaddr; |
|
|
tmpaddr[0] = 0xff; |
tmpaddr = msgaddr = dev->sc_msg; |
tmpaddr[1] = 0xff; |
|
|
tmpaddr[0] = 0xff; |
GET_SBIC_asr(regs, asr); |
tmpaddr[1] = 0xff; |
|
|
#ifdef DEBUG |
GET_SBIC_asr(regs, asr); |
if (reselect_debug > 1) |
|
printf("sbicmsgin asr=%02x\n", asr); |
#ifdef DEBUG |
#endif |
if ( reselect_debug > 1 ) |
|
printf("sbicmsgin asr=%02x\n", asr); |
GET_SBIC_selid (regs, csr); |
#endif |
SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); |
|
|
GET_SBIC_selid (regs, csr); |
SBIC_TC_PUT(regs, 0); |
SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI); |
SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); |
|
|
SBIC_TC_PUT(regs, 0); |
do { |
SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); |
while (recvlen--) { |
|
|
do { |
/* |
while( recvlen-- ) { |
* Fetch the next byte of the message |
|
*/ |
/* |
RECV_BYTE(regs, *tmpaddr); |
* Fetch the next byte of the message |
|
*/ |
/* |
RECV_BYTE(regs, *tmpaddr); |
* get the command completion interrupt, or we |
|
* can't send a new command (LCI) |
/* |
*/ |
* get the command completion interrupt, or we |
SBIC_WAIT(regs, SBIC_ASR_INT, 0); |
* can't send a new command (LCI) |
GET_SBIC_csr(regs, csr); |
*/ |
|
SBIC_WAIT(regs, SBIC_ASR_INT, 0); |
#ifdef DEBUG |
GET_SBIC_csr(regs, csr); |
if (reselect_debug > 1) |
|
printf("sbicmsgin: got %02x csr %02x\n", |
#ifdef DEBUG |
*tmpaddr, csr); |
if ( reselect_debug > 1 ) |
#endif |
printf("sbicmsgin: got %02x csr %02x\n", *tmpaddr, csr); |
|
#endif |
tmpaddr++; |
|
|
tmpaddr++; |
if (recvlen) { |
|
/* |
if ( recvlen ) { |
* Clear ACK, and wait for the interrupt |
/* |
* for the next byte |
* Clear ACK, and wait for the interrupt for the next byte |
*/ |
*/ |
SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); |
SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); |
SBIC_WAIT(regs, SBIC_ASR_INT, 0); |
SBIC_WAIT(regs, SBIC_ASR_INT, 0); |
GET_SBIC_csr(regs, csr); |
GET_SBIC_csr(regs, csr); |
} |
} |
} |
} |
|
|
if (msgaddr[0] == 0xff) { |
if ( msgaddr[0] == 0xff ) { |
printf("sbicmsgin: sbic swallowed our message\n"); |
printf("sbicmsgin: sbic swallowed our message\n"); |
break; |
break; |
} |
} |
|
|
#ifdef DEBUG |
#ifdef DEBUG |
if (sync_debug) { |
if ( sync_debug ) { |
GET_SBIC_asr(regs, asr); |
GET_SBIC_asr(regs, asr); |
printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", |
printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n", csr, asr, msgaddr[0]); |
csr, asr, msgaddr[0]); |
} |
} |
#endif |
#endif |
/* |
/* |
* test whether this is a reply to our sync |
* test whether this is a reply to our sync |
* request |
* request |
*/ |
*/ |
if ( MSG_ISIDENTIFY(msgaddr[0]) ) { |
if (MSG_ISIDENTIFY(msgaddr[0])) { |
|
|
/* |
/* |
* Got IFFY msg -- ack it |
* Got IFFY msg -- ack it |
*/ |
*/ |
QPRINTF(("IFFY")); |
QPRINTF(("IFFY")); |
|
|
} else |
} else if (msgaddr[0] == MSG_REJECT && |
if ( msgaddr[0] == MSG_REJECT && |
dev->sc_sync[dev->target].state == SYNC_SENT) { |
dev->sc_sync[dev->target].state == SYNC_SENT) { |
|
|
/* |
/* |
* Target probably rejected our Sync negotiation. |
* Target probably rejected our Sync negotiation. |
*/ |
*/ |
QPRINTF(("REJECT of SYN")); |
QPRINTF(("REJECT of SYN")); |
|
|
#ifdef DEBUG |
#ifdef DEBUG |
if (sync_debug) |
if ( sync_debug ) |
printf("target %d rejected sync, going async\n", |
printf("target %d rejected sync, going async\n", dev->target); |
dev->target); |
#endif |
#endif |
|
|
dev->sc_sync[dev->target].period = sbic_min_period; |
dev->sc_sync[dev->target].period = sbic_min_period; |
dev->sc_sync[dev->target].offset = 0; |
dev->sc_sync[dev->target].offset = 0; |
dev->sc_sync[dev->target].state = SYNC_DONE; |
dev->sc_sync[dev->target].state = SYNC_DONE; |
SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, |
SET_SBIC_syn(regs, |
dev->sc_sync[dev->target].period)); |
SBIC_SYN(dev->sc_sync[dev->target].offset, |
|
dev->sc_sync[dev->target].period)); |
} else |
|
if ( msgaddr[0] == MSG_REJECT ) { |
} else if (msgaddr[0] == MSG_REJECT) { |
|
|
/* |
/* |
* we'll never REJECt a REJECT message.. |
* we'll never REJECt a REJECT message.. |
*/ |
*/ |
QPRINTF(("REJECT")); |
QPRINTF(("REJECT")); |
|
|
} else |
} else if (msgaddr[0] == MSG_SAVE_DATA_PTR) { |
if ( msgaddr[0] == MSG_SAVE_DATA_PTR ) { |
|
|
/* |
/* |
* don't reject this either. |
* don't reject this either. |
*/ |
*/ |
QPRINTF(("MSG_SAVE_DATA_PTR")); |
QPRINTF(("MSG_SAVE_DATA_PTR")); |
|
|
} else if (msgaddr[0] == MSG_RESTORE_PTR) { |
} else |
|
if ( msgaddr[0] == MSG_RESTORE_PTR ) { |
/* |
|
* don't reject this either. |
/* |
*/ |
* don't reject this either. |
QPRINTF(("MSG_RESTORE_PTR")); |
*/ |
|
QPRINTF(("MSG_RESTORE_PTR")); |
} else if (msgaddr[0] == MSG_DISCONNECT) { |
|
|
} else |
/* |
if ( msgaddr[0] == MSG_DISCONNECT ) { |
* Target is disconnecting... |
|
*/ |
/* |
QPRINTF(("DISCONNECT")); |
* Target is disconnecting... |
|
*/ |
#ifdef DEBUG |
QPRINTF(("DISCONNECT")); |
if (reselect_debug > 1 && msgaddr[0] == MSG_DISCONNECT) |
|
printf("sbicmsgin: got disconnect msg %s\n", |
#ifdef DEBUG |
(dev->sc_flags & SBICF_ICMD) ? |
if ( reselect_debug > 1 && msgaddr[0] == MSG_DISCONNECT ) |
"rejecting" : ""); |
printf("sbicmsgin: got disconnect msg %s\n", |
#endif |
(dev->sc_flags & SBICF_ICMD) ? "rejecting" : ""); |
|
#endif |
if (dev->sc_flags & SBICF_ICMD) { |
|
/* |
if ( dev->sc_flags & SBICF_ICMD ) { |
* We're in immediate mode. Prevent disconnects. |
/* |
* prepare to reject the message, NACK |
* We're in immediate mode. Prevent disconnects. |
*/ |
* prepare to reject the message, NACK |
SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); |
*/ |
WAIT_CIP(regs); |
SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); |
} |
WAIT_CIP(regs); |
|
} |
} else if (msgaddr[0] == MSG_CMD_COMPLETE) { |
|
|
} else |
/* |
if ( msgaddr[0] == MSG_CMD_COMPLETE ) { |
* !! KLUDGE ALERT !! quite a few drives don't seem to |
|
* really like the current way of sending the |
/* |
* sync-handshake together with the ident-message, and |
* !! KLUDGE ALERT !! quite a few drives don't seem to |
* they react by sending command-complete and |
* really like the current way of sending the |
* disconnecting right after returning the valid sync |
* sync-handshake together with the ident-message, and |
* handshake. So, all I can do is reselect the drive, |
* they react by sending command-complete and |
* and hope it won't disconnect again. I don't think |
* disconnecting right after returning the valid sync |
* this is valid behavior, but I can't help fixing a |
* handshake. So, all I can do is reselect the drive, |
* problem that apparently exists. |
* and hope it won't disconnect again. I don't think |
* |
* this is valid behavior, but I can't help fixing a |
* Note: we should not get here on `normal' command |
* problem that apparently exists. |
* completion, as that condition is handled by the |
* |
* high-level sel&xfer resume command used to walk |
* Note: we should not get here on `normal' command |
* thru status/cc-phase. |
* completion, as that condition is handled by the |
*/ |
* high-level sel&xfer resume command used to walk |
QPRINTF(("CMD_COMPLETE")); |
* thru status/cc-phase. |
|
*/ |
#ifdef DEBUG |
QPRINTF(("CMD_COMPLETE")); |
if (sync_debug) |
|
printf("GOT MSG %d! target %d acting weird.." |
#ifdef DEBUG |
" waiting for disconnect...\n", |
if ( sync_debug ) |
msgaddr[0], dev->target); |
printf ("GOT MSG %d! target %d acting weird.." |
#endif |
" waiting for disconnect...\n", msgaddr[0], dev->target); |
|
#endif |
/* |
|
* Check to see if sbic is handling this |
/* |
*/ |
* Check to see if sbic is handling this |
GET_SBIC_asr(regs, asr); |
*/ |
|
GET_SBIC_asr(regs, asr); |
/* |
|
* XXXSCW: I'm not convinced of this, |
/* |
* we haven't negated ACK yet... |
* XXXSCW: I'm not convinced of this, we haven't negated ACK yet... |
*/ |
*/ |
if (asr & SBIC_ASR_BSY) |
if ( asr & SBIC_ASR_BSY ) |
return SBIC_STATE_RUNNING; |
return SBIC_STATE_RUNNING; |
|
|
/* |
/* |
* Let's try this: Assume it works and set status to 00 |
* Let's try this: Assume it works and set status to 00 |
*/ |
*/ |
dev->sc_stat[0] = 0; |
dev->sc_stat[0] = 0; |
|
|
} else if (msgaddr[0] == MSG_EXT_MESSAGE && |
} else |
tmpaddr == &(msgaddr[1])) { |
if ( msgaddr[0] == MSG_EXT_MESSAGE && tmpaddr == &(msgaddr[1]) ) { |
|
|
/* |
/* |
* Target is sending us an extended message. |
* Target is sending us an extended message. We'll assume it's |
* We'll assume it's the response to our Sync. |
* the response to our Sync. negotiation. |
* negotiation. |
*/ |
*/ |
QPRINTF(("ExtMSG\n")); |
QPRINTF(("ExtMSG\n")); |
|
|
/* |
/* |
* Read in whole extended message. First, negate ACK to accept |
* Read in whole extended message. |
* the MSG_EXT_MESSAGE byte... |
* First, negate ACK to accept |
*/ |
* the MSG_EXT_MESSAGE byte... |
SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); |
*/ |
|
SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); |
/* |
|
* Wait for the interrupt for the next byte (length) |
/* |
*/ |
* Wait for the interrupt for the next byte (length) |
SBIC_WAIT(regs, SBIC_ASR_INT, 0); |
*/ |
GET_SBIC_csr(regs, csr); |
SBIC_WAIT(regs, SBIC_ASR_INT, 0); |
|
GET_SBIC_csr(regs, csr); |
|
|
#ifdef DEBUG |
#ifdef DEBUG |
QPRINTF(("CLR ACK csr %02x\n", csr)); |
QPRINTF(("CLR ACK csr %02x\n", csr)); |
#endif |
#endif |
|
|
/* |
/* |
* Read the length byte |
* Read the length byte |
*/ |
*/ |
RECV_BYTE(regs, *tmpaddr); |
RECV_BYTE(regs, *tmpaddr); |
|
|
/* |
/* |
* Wait for command completion IRQ |
* Wait for command completion IRQ |
*/ |
*/ |
SBIC_WAIT(regs, SBIC_ASR_INT, 0); |
SBIC_WAIT(regs, SBIC_ASR_INT, 0); |
GET_SBIC_csr(regs, csr); |
GET_SBIC_csr(regs, csr); |
|
|
/* |
/* |
* Reload the loop counter |
* Reload the loop counter |
*/ |
*/ |
recvlen = *tmpaddr++; |
recvlen = *tmpaddr++; |
|
|
QPRINTF(("Recving ext msg, csr %02x len %02x\n", csr, recvlen)); |
QPRINTF(("Recving ext msg, csr %02x len %02x\n", |
|
csr, recvlen)); |
} else |
|
if ( msgaddr[0] == MSG_EXT_MESSAGE && msgaddr[1] == 3 && |
} else if (msgaddr[0] == MSG_EXT_MESSAGE && |
msgaddr[2] == MSG_SYNC_REQ ) { |
msgaddr[1] == 3 && |
|
msgaddr[2] == MSG_SYNC_REQ ) { |
/* |
|
* We've received the complete Extended Message Sync. Request... |
/* |
*/ |
* We've received the complete Extended Message Sync. |
QPRINTF(("SYN")); |
* Request... |
|
*/ |
/* |
QPRINTF(("SYN")); |
* Compute the required Transfer Period for the WD chip... |
|
*/ |
/* |
dev->sc_sync[dev->target].period = sbicfromscsiperiod(dev, msgaddr[3]); |
* Compute the required Transfer Period for |
dev->sc_sync[dev->target].offset = msgaddr[4]; |
* the WD chip... |
dev->sc_sync[dev->target].state = SYNC_DONE; |
*/ |
|
dev->sc_sync[dev->target].period = |
/* |
sbicfromscsiperiod(dev, msgaddr[3]); |
* Put the WD chip in synchronous mode |
dev->sc_sync[dev->target].offset = msgaddr[4]; |
*/ |
dev->sc_sync[dev->target].state = SYNC_DONE; |
SET_SBIC_syn(regs, SBIC_SYN(dev->sc_sync[dev->target].offset, |
|
dev->sc_sync[dev->target].period)); |
/* |
|
* Put the WD chip in synchronous mode |
|
*/ |
|
SET_SBIC_syn(regs, |
|
SBIC_SYN(dev->sc_sync[dev->target].offset, |
|
dev->sc_sync[dev->target].period)); |
#ifdef DEBUG |
#ifdef DEBUG |
if ( sync_debug ) |
if (sync_debug) |
printf("msgin(%d): sync reg = 0x%02x\n", dev->target, |
printf("msgin(%d): sync reg = 0x%02x\n", |
SBIC_SYN(dev->sc_sync[dev->target].offset, |
dev->target, |
dev->sc_sync[dev->target].period)); |
SBIC_SYN(dev->sc_sync[dev->target].offset, |
#endif |
dev->sc_sync[dev->target].period)); |
|
#endif |
printf("%s: target %d now synchronous, period=%dns, offset=%d.\n", |
|
dev->sc_dev.dv_xname, dev->target, |
printf("%s: target %d now synchronous, " |
msgaddr[3] * 4, msgaddr[4]); |
"period=%dns, offset=%d.\n", |
|
dev->sc_dev.dv_xname, dev->target, |
} else { |
msgaddr[3] * 4, msgaddr[4]); |
|
|
/* |
} else { |
* We don't support whatever this message is... |
|
*/ |
/* |
#ifdef DEBUG |
* We don't support whatever this message is... |
if ( sbic_debug || sync_debug ) |
*/ |
printf ("sbicmsgin: Rejecting message 0x%02x\n", msgaddr[0]); |
#ifdef DEBUG |
#endif |
if (sbic_debug || sync_debug) |
|
printf("sbicmsgin: Rejecting message 0x%02x\n", |
/* |
msgaddr[0]); |
* prepare to reject the message, NACK |
#endif |
*/ |
|
SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); |
/* |
WAIT_CIP(regs); |
* prepare to reject the message, NACK |
} |
*/ |
|
SET_SBIC_cmd(regs, SBIC_CMD_SET_ATN); |
/* |
WAIT_CIP(regs); |
* Negate ACK to complete the transfer |
} |
*/ |
|
SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); |
/* |
|
* Negate ACK to complete the transfer |
/* |
*/ |
* Wait for the interrupt for the next byte, or phase change. |
SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); |
* Only read the CSR if we have more data to transfer. |
|
* XXXSCW: We should really verify that we're still in MSG IN phase |
/* |
* before blindly going back around this loop, but that would mean |
* Wait for the interrupt for the next byte, or phase change. |
* we read the CSR... <sigh> |
* Only read the CSR if we have more data to transfer. |
*/ |
* XXXSCW: We should really verify that we're still in |
SBIC_WAIT(regs, SBIC_ASR_INT, 0); |
* MSG IN phase before blindly going back around this loop, |
if ( recvlen > 0 ) |
* but that would mean we read the CSR... <sigh> |
GET_SBIC_csr(regs, csr); |
*/ |
|
SBIC_WAIT(regs, SBIC_ASR_INT, 0); |
} while ( recvlen > 0 ); |
if (recvlen > 0) |
|
GET_SBIC_csr(regs, csr); |
/* |
|
* Should still have one CSR to read |
} while (recvlen > 0); |
*/ |
|
return SBIC_STATE_RUNNING; |
/* |
|
* Should still have one CSR to read |
|
*/ |
|
return SBIC_STATE_RUNNING; |
} |
} |
|
|
|
|
|
|
* SBIC_STATE_ERROR == error |
* SBIC_STATE_ERROR == error |
*/ |
*/ |
int |
int |
sbicnextstate(dev, csr, asr) |
sbicnextstate(struct sbic_softc *dev, u_char csr, u_char asr) |
struct sbic_softc *dev; |
{ |
u_char csr, |
sbic_regmap_p regs = dev->sc_sbicp; |
asr; |
struct sbic_acb *acb = dev->sc_nexus; |
{ |
|
sbic_regmap_p regs = dev->sc_sbicp; |
|
struct sbic_acb *acb = dev->sc_nexus; |
|
|
|
QPRINTF(("next[%02x,%02x]: ",asr,csr)); |
|
|
|
switch (csr) { |
|
|
|
case SBIC_CSR_XFERRED | CMD_PHASE: |
|
case SBIC_CSR_MIS | CMD_PHASE: |
|
case SBIC_CSR_MIS_1 | CMD_PHASE: |
|
case SBIC_CSR_MIS_2 | CMD_PHASE: |
|
{ |
|
if ( sbicxfout(regs, acb->clen, &acb->cmd) ) |
|
goto abort; |
|
} |
|
break; |
|
|
|
case SBIC_CSR_XFERRED | STATUS_PHASE: |
QPRINTF(("next[%02x,%02x]: ",asr,csr)); |
case SBIC_CSR_MIS | STATUS_PHASE: |
|
case SBIC_CSR_MIS_1 | STATUS_PHASE: |
switch (csr) { |
case SBIC_CSR_MIS_2 | STATUS_PHASE: |
|
{ |
|
SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); |
|
|
|
/* |
|
* this should be the normal i/o completion case. |
|
* get the status & cmd complete msg then let the |
|
* device driver look at what happened. |
|
*/ |
|
sbicxfdone(dev); |
|
|
|
#ifdef DEBUG |
|
dev->sc_dmatimo = 0; |
|
if ( data_pointer_debug > 1 ) |
|
printf("next dmastop: %d(%p:%lx)\n", dev->target, |
|
dev->sc_cur->dc_addr, |
|
dev->sc_tcnt); |
|
#endif |
|
/* |
|
* Stop the DMA chip |
|
*/ |
|
dev->sc_dmastop(dev); |
|
|
|
dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); |
|
|
|
/* |
|
* Indicate to the upper layers that the command is done |
|
*/ |
|
sbic_scsidone(acb, dev->sc_stat[0]); |
|
|
|
return SBIC_STATE_DONE; |
|
} |
|
|
|
case SBIC_CSR_XFERRED | DATA_OUT_PHASE: |
|
case SBIC_CSR_XFERRED | DATA_IN_PHASE: |
|
case SBIC_CSR_MIS | DATA_OUT_PHASE: |
|
case SBIC_CSR_MIS | DATA_IN_PHASE: |
|
case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: |
|
case SBIC_CSR_MIS_1 | DATA_IN_PHASE: |
|
case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: |
|
case SBIC_CSR_MIS_2 | DATA_IN_PHASE: |
|
{ |
|
/* |
|
* Verify that we expected to transfer data... |
|
*/ |
|
if ( acb->sc_kv.dc_count <= 0 ) { |
|
printf("next: DATA phase with xfer count == %d, asr:0x%02x csr:0x%02x\n", |
|
acb->sc_kv.dc_count, asr, csr); |
|
goto abort; |
|
} |
|
|
|
/* |
case SBIC_CSR_XFERRED | CMD_PHASE: |
* Should we transfer using PIO or DMA ? |
case SBIC_CSR_MIS | CMD_PHASE: |
*/ |
case SBIC_CSR_MIS_1 | CMD_PHASE: |
if ( dev->sc_xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || |
case SBIC_CSR_MIS_2 | CMD_PHASE: |
acb->sc_dmacmd == 0 ) { |
if ( sbicxfout(regs, acb->clen, &acb->cmd) ) |
|
goto abort; |
/* |
break; |
* Do PIO transfer |
|
*/ |
|
int i; |
|
|
|
#ifdef DEBUG |
|
if ( data_pointer_debug > 1 ) |
|
printf("next PIO: %d(%p:%x)\n", dev->target, |
|
acb->sc_kv.dc_addr, |
|
acb->sc_kv.dc_count); |
|
#endif |
|
|
|
if ( SBIC_PHASE(csr) == DATA_IN_PHASE ) |
|
/* |
|
* data in |
|
*/ |
|
i = sbicxfin(regs, acb->sc_kv.dc_count, |
|
acb->sc_kv.dc_addr); |
|
else |
|
/* |
|
* data out |
|
*/ |
|
i = sbicxfout(regs, acb->sc_kv.dc_count, |
|
acb->sc_kv.dc_addr); |
|
|
|
acb->sc_kv.dc_addr += (acb->sc_kv.dc_count - i); |
|
acb->sc_kv.dc_count = i; |
|
|
|
/* |
|
* Update current count... |
|
*/ |
|
acb->sc_tcnt = dev->sc_tcnt = i; |
|
|
|
dev->sc_flags &= ~SBICF_INDMA; |
|
|
|
} else { |
|
|
|
/* |
|
* Do DMA transfer |
|
* set next DMA addr and dec count |
|
*/ |
|
sbic_save_ptrs(dev); |
|
sbic_load_ptrs(dev); |
|
|
|
SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | |
|
SBIC_MACHINE_DMA_MODE); |
|
|
|
#ifdef DEBUG |
|
dev->sc_dmatimo = 1; |
|
if ( data_pointer_debug > 1 ) |
|
printf("next DMA: %d(%p:%lx)\n", dev->target, |
|
dev->sc_cur->dc_addr, |
|
dev->sc_tcnt); |
|
#endif |
|
/* |
|
* Start the DMA chip going |
|
*/ |
|
dev->sc_tcnt = dev->sc_dmanext(dev); |
|
|
|
/* |
|
* Tell the WD chip how much to transfer this time around |
|
*/ |
|
SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); |
|
|
|
/* |
|
* Start the transfer |
|
*/ |
|
SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); |
|
|
|
/* |
|
* Indicate that we're in DMA mode |
|
*/ |
|
dev->sc_flags |= SBICF_INDMA; |
|
} |
|
} |
|
break; |
|
|
|
case SBIC_CSR_XFERRED | MESG_IN_PHASE: |
|
case SBIC_CSR_MIS | MESG_IN_PHASE: |
|
case SBIC_CSR_MIS_1 | MESG_IN_PHASE: |
|
case SBIC_CSR_MIS_2 | MESG_IN_PHASE: |
|
{ |
|
sbic_save_ptrs(dev); |
|
|
|
/* |
|
* Handle a single message in... |
|
*/ |
|
return sbicmsgin(dev); |
|
} |
|
|
|
case SBIC_CSR_MSGIN_W_ACK: |
|
{ |
|
/* |
|
* We should never see this since it's handled in 'sbicmsgin()' |
|
* but just for the sake of paranoia... |
|
*/ |
|
SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); /* Dunno what I'm ACKing */ |
|
printf("Acking unknown msgin CSR:%02x",csr); |
|
} |
|
break; |
|
|
|
case SBIC_CSR_XFERRED | MESG_OUT_PHASE: |
|
case SBIC_CSR_MIS | MESG_OUT_PHASE: |
|
case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: |
|
case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: |
|
{ |
|
/* |
|
* We only ever handle a message out phase here for sending a |
|
* REJECT message. |
|
*/ |
|
sbic_save_ptrs(dev); |
|
|
|
#ifdef DEBUG |
|
if (sync_debug) |
|
printf ("sending REJECT msg to last msg.\n"); |
|
#endif |
|
|
|
SEND_BYTE(regs, MSG_REJECT); |
|
WAIT_CIP(regs); |
|
} |
|
break; |
|
|
|
case SBIC_CSR_DISC: |
|
case SBIC_CSR_DISC_1: |
|
{ |
|
/* |
|
* Try to schedule another target |
|
*/ |
|
sbic_save_ptrs(dev); |
|
|
|
dev->sc_flags &= ~SBICF_SELECTED; |
|
|
|
#ifdef DEBUG |
|
if ( reselect_debug > 1 ) |
|
printf("sbicnext target %d disconnected\n", dev->target); |
|
#endif |
|
|
|
TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); |
|
|
|
++dev->sc_tinfo[dev->target].dconns; |
|
|
|
dev->sc_nexus = NULL; |
|
dev->sc_xs = NULL; |
|
|
|
if ( acb->xs->xs_control & XS_CTL_POLL || dev->sc_flags & SBICF_ICMD || |
|
!sbic_parallel_operations ) |
|
return SBIC_STATE_DISCONNECT; |
|
|
|
QPRINTF(("sbicnext: calling sbic_sched\n")); |
|
|
|
sbic_sched(dev); |
|
|
|
QPRINTF(("sbicnext: sbic_sched returned\n")); |
|
|
|
return SBIC_STATE_DISCONNECT; |
|
} |
|
|
|
case SBIC_CSR_RSLT_NI: |
|
case SBIC_CSR_RSLT_IFY: |
|
{ |
|
/* |
|
* A reselection. |
|
* Note that since we don't enable Advanced Features (assuming |
|
* the WD chip is at least the 'A' revision), we're only ever |
|
* likely to see the 'SBIC_CSR_RSLT_NI' status. But for the |
|
* hell of it, we'll handle it anyway, for all the extra code |
|
* it needs... |
|
*/ |
|
u_char newtarget, |
|
newlun; |
|
|
|
GET_SBIC_rselid(regs, newtarget); |
|
|
|
/* |
|
* check SBIC_RID_SIV? |
|
*/ |
|
newtarget &= SBIC_RID_MASK; |
|
|
|
if ( csr == SBIC_CSR_RSLT_IFY ) { |
|
|
|
/* |
|
* Read Identify msg to avoid lockup |
|
*/ |
|
GET_SBIC_data(regs, newlun); |
|
WAIT_CIP(regs); |
|
newlun &= SBIC_TLUN_MASK; |
|
|
|
} else { |
|
|
|
/* |
|
* Need to read Identify message the hard way, assuming |
|
* the target even sends us one... |
|
*/ |
|
for (newlun = 255; newlun; --newlun) { |
|
GET_SBIC_asr(regs, asr); |
|
if (asr & SBIC_ASR_INT) |
|
break; |
|
delay(10); |
|
} |
|
|
|
/* |
|
* If we didn't get an interrupt, somethink's up |
|
*/ |
|
if ( (asr & SBIC_ASR_INT) == 0 ) { |
|
printf("%s: Reselect without identify? asr %x\n", |
|
dev->sc_dev.dv_xname, asr); |
|
newlun = 0; /* XXXX */ |
|
} else { |
|
/* |
|
* We got an interrupt, verify that it's a change to |
|
* message in phase, and if so read the message. |
|
*/ |
|
GET_SBIC_csr(regs,csr); |
|
|
|
if ( csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || |
|
csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || |
|
csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE) ) { |
|
/* |
|
* Yup, gone to message in. Fetch the target LUN |
|
*/ |
|
sbicmsgin(dev); |
|
newlun = dev->sc_msg[0] & 0x07; |
|
|
|
} else { |
|
/* |
|
* Whoops! Target didn't go to message in phase!! |
|
*/ |
|
printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); |
|
newlun = 0; /* XXXSCW */ |
|
} |
|
} |
|
} |
|
|
|
/* |
|
* Ok, we have the identity of the reselecting target. |
|
*/ |
|
#ifdef DEBUG |
|
if ( reselect_debug > 1 || |
|
(reselect_debug && csr == SBIC_CSR_RSLT_NI) ) { |
|
printf("sbicnext: reselect %s from targ %d lun %d\n", |
|
csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, newlun); |
|
} |
|
#endif |
|
|
|
if ( dev->sc_nexus ) { |
|
/* |
|
* Whoops! We've been reselected with an command in progress! |
|
* The best we can do is to put the current command back on the |
|
* ready list and hope for the best. |
|
*/ |
|
#ifdef DEBUG |
|
if ( reselect_debug > 1 ) { |
|
printf("%s: reselect %s with active command\n", |
|
dev->sc_dev.dv_xname, |
|
csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); |
|
} |
|
#endif |
|
|
|
TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); |
|
|
|
dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); |
|
|
|
dev->sc_nexus = NULL; |
|
dev->sc_xs = NULL; |
|
} |
|
|
|
/* |
|
* Reload sync values for this target |
|
*/ |
|
if ( dev->sc_sync[newtarget].state == SYNC_DONE ) |
|
SET_SBIC_syn(regs, SBIC_SYN (dev->sc_sync[newtarget].offset, |
|
dev->sc_sync[newtarget].period)); |
|
else |
|
SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); |
|
|
|
/* |
|
* Loop through the nexus list until we find the saved entry |
|
* for the reselecting target... |
|
*/ |
|
for (acb = dev->nexus_list.tqh_first; acb; |
|
acb = acb->chain.tqe_next) { |
|
|
|
if ( acb->xs->xs_periph->periph_target == newtarget && |
|
acb->xs->xs_periph->periph_lun == newlun) { |
|
/* |
|
* We've found the saved entry. Dequeue it, and |
|
* make it current again. |
|
*/ |
|
TAILQ_REMOVE(&dev->nexus_list, acb, chain); |
|
|
|
dev->sc_nexus = acb; |
|
dev->sc_xs = acb->xs; |
|
dev->sc_flags |= SBICF_SELECTED; |
|
dev->target = newtarget; |
|
dev->lun = newlun; |
|
break; |
|
} |
|
} |
|
|
|
if ( acb == NULL ) { |
|
printf("%s: reselect %s targ %d not in nexus_list %p\n", |
|
dev->sc_dev.dv_xname, |
|
csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, |
|
&dev->nexus_list.tqh_first); |
|
panic("bad reselect in sbic"); |
|
} |
|
|
|
if ( csr == SBIC_CSR_RSLT_IFY ) |
|
SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); |
|
} |
|
break; |
|
|
|
default: |
case SBIC_CSR_XFERRED | STATUS_PHASE: |
|
case SBIC_CSR_MIS | STATUS_PHASE: |
|
case SBIC_CSR_MIS_1 | STATUS_PHASE: |
|
case SBIC_CSR_MIS_2 | STATUS_PHASE: |
|
SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); |
|
|
|
/* |
|
* this should be the normal i/o completion case. |
|
* get the status & cmd complete msg then let the |
|
* device driver look at what happened. |
|
*/ |
|
sbicxfdone(dev); |
|
|
|
#ifdef DEBUG |
|
dev->sc_dmatimo = 0; |
|
if (data_pointer_debug > 1) |
|
printf("next dmastop: %d(%p:%lx)\n", |
|
dev->target, |
|
dev->sc_cur->dc_addr, |
|
dev->sc_tcnt); |
|
#endif |
|
/* |
|
* Stop the DMA chip |
|
*/ |
|
dev->sc_dmastop(dev); |
|
|
|
dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); |
|
|
|
/* |
|
* Indicate to the upper layers that the command is done |
|
*/ |
|
sbic_scsidone(acb, dev->sc_stat[0]); |
|
|
|
return SBIC_STATE_DONE; |
|
|
|
case SBIC_CSR_XFERRED | DATA_OUT_PHASE: |
|
case SBIC_CSR_XFERRED | DATA_IN_PHASE: |
|
case SBIC_CSR_MIS | DATA_OUT_PHASE: |
|
case SBIC_CSR_MIS | DATA_IN_PHASE: |
|
case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: |
|
case SBIC_CSR_MIS_1 | DATA_IN_PHASE: |
|
case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: |
|
case SBIC_CSR_MIS_2 | DATA_IN_PHASE: |
|
/* |
|
* Verify that we expected to transfer data... |
|
*/ |
|
if (acb->sc_kv.dc_count <= 0) { |
|
printf("next: DATA phase with xfer count == %d, " |
|
"asr:0x%02x csr:0x%02x\n", |
|
acb->sc_kv.dc_count, asr, csr); |
|
goto abort; |
|
} |
|
|
|
/* |
|
* Should we transfer using PIO or DMA ? |
|
*/ |
|
if (dev->sc_xs->xs_control & XS_CTL_POLL || |
|
dev->sc_flags & SBICF_ICMD || |
|
acb->sc_dmacmd == 0 ) { |
|
|
|
/* |
|
* Do PIO transfer |
|
*/ |
|
int i; |
|
|
|
#ifdef DEBUG |
|
if (data_pointer_debug > 1) |
|
printf("next PIO: %d(%p:%x)\n", dev->target, |
|
acb->sc_kv.dc_addr, |
|
acb->sc_kv.dc_count); |
|
#endif |
|
|
|
if (SBIC_PHASE(csr) == DATA_IN_PHASE) |
|
/* |
|
* data in |
|
*/ |
|
i = sbicxfin(regs, acb->sc_kv.dc_count, |
|
acb->sc_kv.dc_addr); |
|
else |
|
/* |
|
* data out |
|
*/ |
|
i = sbicxfout(regs, acb->sc_kv.dc_count, |
|
acb->sc_kv.dc_addr); |
|
|
|
acb->sc_kv.dc_addr += (acb->sc_kv.dc_count - i); |
|
acb->sc_kv.dc_count = i; |
|
|
|
/* |
|
* Update current count... |
|
*/ |
|
acb->sc_tcnt = dev->sc_tcnt = i; |
|
|
|
dev->sc_flags &= ~SBICF_INDMA; |
|
|
|
} else { |
|
|
|
/* |
|
* Do DMA transfer |
|
* set next DMA addr and dec count |
|
*/ |
|
sbic_save_ptrs(dev); |
|
sbic_load_ptrs(dev); |
|
|
|
SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI | |
|
SBIC_MACHINE_DMA_MODE); |
|
|
|
#ifdef DEBUG |
|
dev->sc_dmatimo = 1; |
|
if (data_pointer_debug > 1) |
|
printf("next DMA: %d(%p:%lx)\n", dev->target, |
|
dev->sc_cur->dc_addr, |
|
dev->sc_tcnt); |
|
#endif |
|
/* |
|
* Start the DMA chip going |
|
*/ |
|
dev->sc_tcnt = dev->sc_dmanext(dev); |
|
|
|
/* |
|
* Tell the WD chip how much to transfer |
|
* this time around |
|
*/ |
|
SBIC_TC_PUT(regs, (unsigned)dev->sc_tcnt); |
|
|
|
/* |
|
* Start the transfer |
|
*/ |
|
SET_SBIC_cmd(regs, SBIC_CMD_XFER_INFO); |
|
|
|
/* |
|
* Indicate that we're in DMA mode |
|
*/ |
|
dev->sc_flags |= SBICF_INDMA; |
|
} |
|
break; |
|
|
|
case SBIC_CSR_XFERRED | MESG_IN_PHASE: |
|
case SBIC_CSR_MIS | MESG_IN_PHASE: |
|
case SBIC_CSR_MIS_1 | MESG_IN_PHASE: |
|
case SBIC_CSR_MIS_2 | MESG_IN_PHASE: |
|
sbic_save_ptrs(dev); |
|
|
|
/* |
|
* Handle a single message in... |
|
*/ |
|
return sbicmsgin(dev); |
|
|
|
case SBIC_CSR_MSGIN_W_ACK: |
|
/* |
|
* We should never see this since it's handled in 'sbicmsgin()' |
|
* but just for the sake of paranoia... |
|
*/ |
|
/* Dunno what I'm ACKing */ |
|
SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); |
|
printf("Acking unknown msgin CSR:%02x",csr); |
|
break; |
|
|
|
case SBIC_CSR_XFERRED | MESG_OUT_PHASE: |
|
case SBIC_CSR_MIS | MESG_OUT_PHASE: |
|
case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: |
|
case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: |
|
/* |
|
* We only ever handle a message out phase here for sending a |
|
* REJECT message. |
|
*/ |
|
sbic_save_ptrs(dev); |
|
|
|
#ifdef DEBUG |
|
if (sync_debug) |
|
printf("sending REJECT msg to last msg.\n"); |
|
#endif |
|
|
|
SEND_BYTE(regs, MSG_REJECT); |
|
WAIT_CIP(regs); |
|
break; |
|
|
|
case SBIC_CSR_DISC: |
|
case SBIC_CSR_DISC_1: |
|
/* |
|
* Try to schedule another target |
|
*/ |
|
sbic_save_ptrs(dev); |
|
|
|
dev->sc_flags &= ~SBICF_SELECTED; |
|
|
|
#ifdef DEBUG |
|
if (reselect_debug > 1) |
|
printf("sbicnext target %d disconnected\n", |
|
dev->target); |
|
#endif |
|
|
|
TAILQ_INSERT_HEAD(&dev->nexus_list, acb, chain); |
|
|
|
++dev->sc_tinfo[dev->target].dconns; |
|
|
|
dev->sc_nexus = NULL; |
|
dev->sc_xs = NULL; |
|
|
|
if (acb->xs->xs_control & XS_CTL_POLL || |
|
dev->sc_flags & SBICF_ICMD || |
|
!sbic_parallel_operations ) |
|
return SBIC_STATE_DISCONNECT; |
|
|
|
QPRINTF(("sbicnext: calling sbic_sched\n")); |
|
|
|
sbic_sched(dev); |
|
|
|
QPRINTF(("sbicnext: sbic_sched returned\n")); |
|
|
|
return SBIC_STATE_DISCONNECT; |
|
|
|
case SBIC_CSR_RSLT_NI: |
|
case SBIC_CSR_RSLT_IFY: |
|
{ |
|
/* |
|
* A reselection. |
|
* Note that since we don't enable Advanced Features (assuming |
|
* the WD chip is at least the 'A' revision), we're only ever |
|
* likely to see the 'SBIC_CSR_RSLT_NI' status. But for the |
|
* hell of it, we'll handle it anyway, for all the extra code |
|
* it needs... |
|
*/ |
|
u_char newtarget, newlun; |
|
|
|
GET_SBIC_rselid(regs, newtarget); |
|
|
|
/* |
|
* check SBIC_RID_SIV? |
|
*/ |
|
newtarget &= SBIC_RID_MASK; |
|
|
|
if (csr == SBIC_CSR_RSLT_IFY) { |
|
|
|
/* |
|
* Read Identify msg to avoid lockup |
|
*/ |
|
GET_SBIC_data(regs, newlun); |
|
WAIT_CIP(regs); |
|
newlun &= SBIC_TLUN_MASK; |
|
|
|
} else { |
|
|
|
/* |
|
* Need to read Identify message the hard way, assuming |
|
* the target even sends us one... |
|
*/ |
|
for (newlun = 255; newlun; --newlun) { |
|
GET_SBIC_asr(regs, asr); |
|
if (asr & SBIC_ASR_INT) |
|
break; |
|
delay(10); |
|
} |
|
|
|
/* |
|
* If we didn't get an interrupt, somethink's up |
|
*/ |
|
if ((asr & SBIC_ASR_INT) == 0) { |
|
printf("%s: Reselect without identify?" |
|
" asr %x\n", dev->sc_dev.dv_xname, asr); |
|
newlun = 0; /* XXXX */ |
|
} else { |
|
/* |
|
* We got an interrupt, verify that |
|
* it's a change to message in phase, |
|
* and if so read the message. |
|
*/ |
|
GET_SBIC_csr(regs,csr); |
|
|
|
if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || |
|
csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || |
|
csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { |
|
/* |
|
* Yup, gone to message in. |
|
* Fetch the target LUN |
|
*/ |
|
sbicmsgin(dev); |
|
newlun = dev->sc_msg[0] & 0x07; |
|
|
|
} else { |
|
/* |
|
* Whoops! Target didn't go to |
|
* message in phase!! |
|
*/ |
|
printf("RSLT_NI - " |
|
"not MESG_IN_PHASE %x\n", csr); |
|
newlun = 0; /* XXXSCW */ |
|
} |
|
} |
|
} |
|
|
|
/* |
|
* Ok, we have the identity of the reselecting target. |
|
*/ |
|
#ifdef DEBUG |
|
if (reselect_debug > 1 || |
|
(reselect_debug && csr == SBIC_CSR_RSLT_NI)) { |
|
printf("sbicnext: reselect %s from targ %d lun %d\n", |
|
csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", |
|
newtarget, newlun); |
|
} |
|
#endif |
|
|
|
if (dev->sc_nexus) { |
|
/* |
|
* Whoops! We've been reselected with |
|
* an command in progress! |
|
* The best we can do is to put the current command |
|
* back on the ready list and hope for the best. |
|
*/ |
|
#ifdef DEBUG |
|
if (reselect_debug > 1) { |
|
printf("%s: reselect %s with active command\n", |
|
dev->sc_dev.dv_xname, |
|
csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY"); |
|
} |
|
#endif |
|
|
|
TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, |
|
chain); |
|
|
|
dev->sc_tinfo[dev->target].lubusy &= ~(1 << dev->lun); |
|
|
|
dev->sc_nexus = NULL; |
|
dev->sc_xs = NULL; |
|
} |
|
|
|
/* |
|
* Reload sync values for this target |
|
*/ |
|
if (dev->sc_sync[newtarget].state == SYNC_DONE) |
|
SET_SBIC_syn(regs, |
|
SBIC_SYN(dev->sc_sync[newtarget].offset, |
|
dev->sc_sync[newtarget].period)); |
|
else |
|
SET_SBIC_syn(regs, SBIC_SYN (0, sbic_min_period)); |
|
|
|
/* |
|
* Loop through the nexus list until we find the saved entry |
|
* for the reselecting target... |
|
*/ |
|
for (acb = dev->nexus_list.tqh_first; acb; |
|
acb = acb->chain.tqe_next) { |
|
|
|
if ( acb->xs->xs_periph->periph_target == newtarget && |
|
acb->xs->xs_periph->periph_lun == newlun) { |
|
/* |
|
* We've found the saved entry. Dequeue it, and |
|
* make it current again. |
|
*/ |
|
TAILQ_REMOVE(&dev->nexus_list, acb, chain); |
|
|
|
dev->sc_nexus = acb; |
|
dev->sc_xs = acb->xs; |
|
dev->sc_flags |= SBICF_SELECTED; |
|
dev->target = newtarget; |
|
dev->lun = newlun; |
|
break; |
|
} |
|
} |
|
|
|
if (acb == NULL) { |
|
printf("%s: reselect %s targ %d not in nexus_list %p\n", |
|
dev->sc_dev.dv_xname, |
|
csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget, |
|
&dev->nexus_list.tqh_first); |
|
panic("bad reselect in sbic"); |
|
} |
|
|
|
if (csr == SBIC_CSR_RSLT_IFY) |
|
SET_SBIC_cmd(regs, SBIC_CMD_CLR_ACK); |
|
break; |
|
} |
|
default: |
abort: |
abort: |
{ |
/* |
/* |
* Something unexpected happened -- deal with it. |
* Something unexpected happened -- deal with it. |
*/ |
*/ |
printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); |
printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); |
|
|
|
#ifdef DDB |
#ifdef DDB |
Debugger(); |
Debugger(); |
#endif |
#endif |
|
|
#ifdef DEBUG |
#ifdef DEBUG |
dev->sc_dmatimo = 0; |
dev->sc_dmatimo = 0; |
if ( data_pointer_debug > 1 ) |
if (data_pointer_debug > 1) |
printf("next dmastop: %d(%p:%lx)\n", dev->target, |
printf("next dmastop: %d(%p:%lx)\n", dev->target, |
dev->sc_cur->dc_addr, |
dev->sc_cur->dc_addr, |
dev->sc_tcnt); |
dev->sc_tcnt); |
#endif |
#endif |
|
|
dev->sc_dmastop(dev); |
dev->sc_dmastop(dev); |
SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); |
SET_SBIC_control(regs, SBIC_CTL_EDI | SBIC_CTL_IDI); |
if ( dev->sc_xs ) sbicerror(dev, csr); |
if (dev->sc_xs) |
sbicabort(dev, "next"); |
sbicerror(dev, csr); |
|
sbicabort(dev, "next"); |
|
|
if ( dev->sc_flags & SBICF_INDMA ) { |
if (dev->sc_flags & SBICF_INDMA) { |
dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); |
dev->sc_flags &= ~(SBICF_INDMA | SBICF_DCFLUSH); |
|
|
#ifdef DEBUG |
#ifdef DEBUG |
dev->sc_dmatimo = 0; |
dev->sc_dmatimo = 0; |
if ( data_pointer_debug > 1 ) |
if (data_pointer_debug > 1) |
printf("next dmastop: %d(%p:%lx)\n", dev->target, |
printf("next dmastop: %d(%p:%lx)\n", |
dev->sc_cur->dc_addr, |
dev->target, |
dev->sc_tcnt); |
dev->sc_cur->dc_addr, |
|
dev->sc_tcnt); |
#endif |
#endif |
sbic_scsidone(acb, -1); |
sbic_scsidone(acb, -1); |
} |
} |
|
|
return SBIC_STATE_ERROR; |
return SBIC_STATE_ERROR; |
} |
} |
} |
|
|
|
return(SBIC_STATE_RUNNING); |
return SBIC_STATE_RUNNING; |
} |
} |
|
|
|
|
Line 2564 sbicnextstate(dev, csr, asr) |
|
Line 2534 sbicnextstate(dev, csr, asr) |
|
* Check if DMA can not be used with specified buffer |
* Check if DMA can not be used with specified buffer |
*/ |
*/ |
int |
int |
sbiccheckdmap(bp, len, mask) |
sbiccheckdmap(void *bp, u_long len, u_long mask) |
void *bp; |
|
u_long len, |
|
mask; |
|
{ |
{ |
u_char *buffer; |
u_char *buffer; |
u_long phy_buf; |
u_long phy_buf; |
u_long phy_len; |
u_long phy_len; |
|
|
buffer = bp; |
buffer = bp; |
|
|
if ( len == 0 ) |
if (len == 0) |
return(1); |
return 1; |
|
|
while ( len ) { |
while (len) { |
|
|
phy_buf = kvtop((void *)buffer); |
phy_buf = kvtop((void *)buffer); |
phy_len = PAGE_SIZE - ((int) buffer & PGOFSET); |
phy_len = PAGE_SIZE - ((int)buffer & PGOFSET); |
|
|
if ( len < phy_len ) |
if (len < phy_len) |
phy_len = len; |
phy_len = len; |
|
|
if ( phy_buf & mask ) |
if (phy_buf & mask) |
return(1); |
return 1; |
|
|
buffer += phy_len; |
buffer += phy_len; |
len -= phy_len; |
len -= phy_len; |
} |
} |
|
|
return(0); |
return 0; |
} |
} |
|
|
int |
int |
sbictoscsiperiod(dev, a) |
sbictoscsiperiod(struct sbic_softc *dev, int a) |
struct sbic_softc *dev; |
|
int a; |
|
{ |
{ |
unsigned int fs; |
unsigned int fs; |
|
|
/* |
/* |
* cycle = DIV / (2 * CLK) |
* cycle = DIV / (2 * CLK) |
* DIV = FS + 2 |
* DIV = FS + 2 |
* best we can do is 200ns at 20 MHz, 2 cycles |
* best we can do is 200ns at 20 MHz, 2 cycles |
*/ |
*/ |
|
|
GET_SBIC_myid(dev->sc_sbicp, fs); |
GET_SBIC_myid(dev->sc_sbicp, fs); |
|
|
fs = (fs >> 6) + 2; /* DIV */ |
fs = (fs >> 6) + 2; /* DIV */ |
|
|
fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ |
fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ |
|
|
if ( a < 2 ) |
if (a < 2) |
a = 8; /* map to Cycles */ |
a = 8; /* map to Cycles */ |
|
|
return ( (fs * a) >> 2 ); /* in 4 ns units */ |
return (fs * a) >> 2; /* in 4 ns units */ |
} |
} |
|
|
int |
int |
sbicfromscsiperiod(dev, p) |
sbicfromscsiperiod(struct sbic_softc *dev, int p) |
struct sbic_softc *dev; |
|
int p; |
|
{ |
{ |
unsigned fs, |
unsigned int fs, ret; |
ret; |
|
|
|
/* |
/* |
* Just the inverse of the above |
* Just the inverse of the above |
*/ |
*/ |
GET_SBIC_myid(dev->sc_sbicp, fs); |
GET_SBIC_myid(dev->sc_sbicp, fs); |
|
|
fs = (fs >> 6) + 2; /* DIV */ |
fs = (fs >> 6) + 2; /* DIV */ |
|
|
fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ |
fs = (fs * 10000) / (dev->sc_clkfreq << 1); /* Cycle, in ns */ |
|
|
ret = p << 2; /* in ns units */ |
ret = p << 2; /* in ns units */ |
ret = ret / fs; /* in Cycles */ |
ret = ret / fs; /* in Cycles */ |
|
|
if ( ret < sbic_min_period ) |
if (ret < sbic_min_period) |
return(sbic_min_period); |
return(sbic_min_period); |
|
|
/* |
/* |
* verify rounding |
* verify rounding |
*/ |
*/ |
if ( sbictoscsiperiod(dev, ret) < p ) |
if (sbictoscsiperiod(dev, ret) < p) |
ret++; |
ret++; |
|
|
return( (ret >= 8) ? 0 : ret ); |
return (ret >= 8) ? 0 : ret; |
} |
} |
|
|
#ifdef DEBUG |
#ifdef DEBUG |
void |
void |
sbictimeout(dev) |
sbictimeout(struct sbic_softc *dev) |
struct sbic_softc *dev; |
|
{ |
{ |
int s, |
int s, asr; |
asr; |
|
|
|
s = splbio(); |
s = splbio(); |
|
|
if ( dev->sc_dmatimo ) { |
if (dev->sc_dmatimo) { |
|
|
if ( dev->sc_dmatimo > 1 ) { |
if (dev->sc_dmatimo > 1) { |
|
|
printf("%s: DMA timeout #%d\n", dev->sc_dev.dv_xname, |
printf("%s: DMA timeout #%d\n", dev->sc_dev.dv_xname, |
dev->sc_dmatimo - 1); |
dev->sc_dmatimo - 1); |
|
|
GET_SBIC_asr(dev->sc_sbicp, asr); |
GET_SBIC_asr(dev->sc_sbicp, asr); |
|
|
if ( asr & SBIC_ASR_INT ) { |
if (asr & SBIC_ASR_INT) { |
/* |
/* |
* We need to service a missed IRQ |
* We need to service a missed IRQ |
*/ |
*/ |
sbicintr(dev); |
sbicintr(dev); |
} else { |
} else { |
(void) sbicabort(dev, "timeout"); |
(void)sbicabort(dev, "timeout"); |
splx(s); |
splx(s); |
return; |
return; |
} |
} |
} |
} |
|
|
dev->sc_dmatimo++; |
dev->sc_dmatimo++; |
} |
} |
|
|
splx(s); |
splx(s); |
|
|
callout_reset(&dev->sc_timo_ch, 30 * hz, (void *)sbictimeout, dev); |
callout_reset(&dev->sc_timo_ch, 30 * hz, (void *)sbictimeout, dev); |
} |
} |
#endif |
#endif |