CVS log for src/sys/arch/mips/mips/vm_machdep.c

Up to [cvs.NetBSD.org] / src / sys / arch / mips / mips

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Keyword substitution: kv
Default branch: MAIN

Convert some assignments into KASSERTs.

l_md is zeroised by lwp_create with

         memset(&l2->l_startzero, 0, sizeof(*l2) -
                    offsetof(lwp_t, l_startzero));

Remove unnecessary include of <sys/malloc.h>.

Revert previous:

http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/arch/mips/mips/vm_machdep.c#rev1.163

> cpu_uarea_alloc: For ILP32, do not try to allocate physical memory above
> pmap_limits.avail_end.
>
> Fix NULL dereference in uvm_pglistalloc_contig_aggressive().

"high" argument larger than pmap_limits.avail_end is just legal for
uvm_pglistalloc(); uvm_pglistalloc_contig_aggressive() and friends
allocate memory between uvm_physseg_get_avail_start() and
uvm_physseg_get_avail_end().

It turned out that the NULL dereference took place as PHYS_TO_VM_PAGE()
aka uvm_phys_to_vm_page() returns NULL for a valid pa. I've not figured
out why...

Thanks chs@ for correcting my misunderstanding.

cpu_uarea_alloc: For ILP32, do not try to allocate physical memory above
pmap_limits.avail_end.

Fix NULL dereference in uvm_pglistalloc_contig_aggressive().

Use a 16kB USPACE (and larger kernel stack) for LP64 kernels.  Invert
the logic for setting the USPACE size.  Define a desired USPACE size
(16kB for LP64, 8kB otherwise) then divide by PAGE_SIZE to get UPAGES.

Fixes random segmap lossage, since the uarea usually sits immediately
above the segmap for a process.  Thanks to mrg@, skrll@ and dholland@
for testing, debugging and general help tracking down this problem.

Add a comment

Merge changes from current as of 20200406

Move all non-emulation-specific coredump code into the coredump module,
and remove all #ifdef COREDUMP conditional compilation.  Now, the
coredump module is completely separated from the emulation modules, and
they can all be independently loaded and unloaded.

Welcome to 9.99.18 !

update from HEAD

Pull up following revision(s) (requested by skrll in ticket #1056):
	sys/arch/mips/mips/pmap.c: revision 1.210-1.213
	sys/arch/mips/mips/vm_machdep.c: revision 1.143
Fix a logic inversion introduced with the matt-nb5-mips64 for
pmap_{zero,copy}_page cache alias handing. The check previously used
PG_MD_UNCACHED_P, where it now uses PG_MD_CACHED_P, when considering if
a cache invalidation is required.
Additionally flush the cache for the uarea va to avoid potential (future)
cache aliases in cpu_uarea_free when handing pages back to uvm for later
use.
ok matt@
Hopefully this addresses the instability reported in the following PRs:
PR/44900 - R5000/Rm5200 mips ports are broken
PR/46170 - NetBSD/cobalt 6.0_BETA does not boot
PR/46890 - upcoming NetBSD 6.0 release is very unstable / unusable on cobalt qube 2
PR/48628 - cobalt and hpcmips ports are dead
Grab pv_list lock in pmap_unmap_ephemeral_page only when needed.
Make PARANOIADIAG compile.
Use pmap_tlb_asid_check to reduce code c&p.

Pull up following revision(s) (requested by skrll in ticket #1056):
	sys/arch/mips/mips/pmap.c: revision 1.210-1.213
	sys/arch/mips/mips/vm_machdep.c: revision 1.143
Fix a logic inversion introduced with the matt-nb5-mips64 for
pmap_{zero,copy}_page cache alias handing. The check previously used
PG_MD_UNCACHED_P, where it now uses PG_MD_CACHED_P, when considering if
a cache invalidation is required.
Additionally flush the cache for the uarea va to avoid potential (future)
cache aliases in cpu_uarea_free when handing pages back to uvm for later
use.
ok matt@
Hopefully this addresses the instability reported in the following PRs:
PR/44900 - R5000/Rm5200 mips ports are broken
PR/46170 - NetBSD/cobalt 6.0_BETA does not boot
PR/46890 - upcoming NetBSD 6.0 release is very unstable / unusable on cobalt qube 2
PR/48628 - cobalt and hpcmips ports are dead
Grab pv_list lock in pmap_unmap_ephemeral_page only when needed.
Make PARANOIADIAG compile.
Use pmap_tlb_asid_check to reduce code c&p.

Sync with HEAD

2564721

file vm_machdep.c was added on branch perseant-stdc-iso10646 on 2017-07-14 17:54:01 +0000

KASSERT Fires for MIPS1, disable.

Resolve conflicts from previous merge (all resulting from $NetBSD
keywork expansion)

Fix non-DIAGNOSTIC build

Sync with HEAD

Add a KASSERT

Make cpu_uarea_{alloc,free} conditional on PMAP_{,UN}MAP_POOLPAGE and
use PMAP_{,UN}_POOLPAGE to ensure cache aliases are handled correctly
and for all the pages used.

Allow cpu_uarea_alloc to return NULL for non-system LWPs in the non-_LP64
case.  That way TLB mapped KVA can be found by uarea_poolpage_alloc.

Improve comment wording.

Sync with HEAD

Sign extended uarea va appropriately for mips_dcache_inv_range

Initialise md_upte for the new lwp
KASSERT that we're always direct mapped when we expect to be

Fixup the #if to reflect when we can have non-direct mappable USPACE

Sync with HEAD

Fix up uarea page mapping compile conditional - we only need code if
USPACE is > PAGE_SIZE.

For LP64 and N32 make sure KX is set in the trapframe as well.

KASSERT for KX in __mips_n32 as well.

Trailing whitespace

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Sync with HEAD

Add struct pmap_limits and pm_{min,max}addr from uvm/pmap/map.h and use it to
store avail_start, avail_end, virtual_start, and virtual_end.
Remove iospace and let emips just bump pmap_limits.virtual_start to get the
VA space it needs.
pmap_segtab.c is almost identical to uvm/pmap/pmap_segtab.c now.  It won't
be long until we switch to the uvm/pmap one.

Convert a KASSERT to KASSERTMSG

Rebase to HEAD as of a few days ago.

Rebase.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

Pull up following revision(s) (requested by skrll in ticket #1056):
	sys/arch/mips/mips/pmap.c: revision 1.211
	sys/arch/mips/mips/pmap.c: revision 1.212
	sys/arch/mips/mips/pmap.c: revision 1.213
	sys/arch/mips/mips/vm_machdep.c: revision 1.143
	sys/arch/mips/mips/pmap.c: revision 1.210
Fix a logic inversion introduced with the matt-nb5-mips64 for
pmap_{zero,copy}_page cache alias handing. The check previously used
PG_MD_UNCACHED_P, where it now uses PG_MD_CACHED_P, when considering if
a cache invalidation is required.
Additionally flush the cache for the uarea va to avoid potential (future)
cache aliases in cpu_uarea_free when handing pages back to uvm for later
use.
ok matt@
Hopefully this addresses the instability reported in the following PRs:
PR/44900 - R5000/Rm5200 mips ports are broken
PR/46170 - NetBSD/cobalt 6.0_BETA does not boot
PR/46890 - upcoming NetBSD 6.0 release is very unstable / unusable on cobalt qube 2
PR/48628 - cobalt and hpcmips ports are dead
Grab pv_list lock in pmap_unmap_ephemeral_page only when needed.
Make PARANOIADIAG compile.
Use pmap_tlb_asid_check to reduce code c&p.

sync with head

Fix a logic inversion introduced with the matt-nb5-mips64 for
pmap_{zero,copy}_page cache alias handing. The check previously used
PG_MD_UNCACHED_P, where it now uses PG_MD_CACHED_P, when considering if
a cache invalidation is required.

Additionally flush the cache for the uarea va to avoid potential (future)
cache aliases in cpu_uarea_free when handing pages back to uvm for later
use.

ok matt@

Hopefully this addresses the instability reported in the following PRs:

PR/44900 - R5000/Rm5200 mips ports are broken
PR/46170 - NetBSD/cobalt 6.0_BETA does not boot
PR/46890 - upcoming NetBSD 6.0 release is very unstable / unusable on cobalt qube 2
PR/48628 - cobalt and hpcmips ports are dead

Change KASSERTMSG/KDASSERTMSG to use varadic arguments like HEAD.
panic -> vpanic, add panic wrapper to vpanic.

Make MIPS use a multi-level page table for the kernel address space.
(just like the user address does).   XXX fix mips1

sync with head

sync to -current.

Remove COMPAT_SA / KERN_SA.  Welcome to 6.99.3!
Approved by core@.

mips_nfreelist is the one past the highest freelist used.

Fix various LP64 thinkos.

Add mm_md_direct_mapped_virt (inverse of mm_md_direct_mapped_phys).  Add a
third argument, vsize_t *, which, if not NULL, returns the amount of virtual
space left in that direct mapped segment.
Get rid most of the individual direct_mapped assert and use the above
routines instead.
Improve kernel core dump code.

Recognize KSEGX as FIRST512M (even though it isn't in the 512M it is
conceptually part of it since it's direct-mapped).

Add mips_page_to_pggroup which return what pggroup a page belongs to.
Eradicate VM_FREELIST_MAX
When adding pages to the system, track what freelists get pages.

When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses.  There are exceptions.
bus_space_handles are now register_t instead of intptr_t.  This allows them
to contain XKPHYS addresses.  Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address.  This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs.  If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.

Add code to deal with direct mapped uareas.

Take part of the KSEG2 space and use it to "almost" direct another 256MB
of memory so that N32 kernels can make use of ram outside of KSEG0.  This
allows N32 kernels to be useful on systems with 4GB of RAM or more.

Modify *ASSERTMSG() so they are now used as variadic macros. The main goal
is to provide routines that do as KASSERT(9) says: append a message
to the panic format string when the assertion triggers, with optional
arguments.

Fix call sites to reflect the new definition.

Discussed on tech-kern@. See
http://mail-index.netbsd.org/tech-kern/2011/09/07/msg011427.html

Use UVM_KMF_COLORMATCH and switch to pmap_kenter_pa for vmapbuf/vunmapbuf.

Catchup with rmind-uvmplock merge.

sync with head

Add some more MI hook points for PCU.  Discard the PCU state at lwp_exit and
at exec time.  Before forking, save the PCU state so that cpu_lwp_fork
doesn't have.  Remove MD code which did that before.

Sync with HEAD.

sync with head

Add MIPS64_RMIXL (XLR/XLS) and MIPS64R2_RMIXL (XLP).  This allows the kernel
to treat this special which is needed for MP support. When accessing the TLB,
always lock the TLB before hand.  If in the miss handlers, the TLB is already
locked let trap deal with the exeception.

Make uvm_map recognize UVM_FLAG_COLORMATCH which tells uvm_map that the
'align' argument specifies the starting color of the KVA range to be returned.

When calling uvm_km_alloc with UVM_KMF_VAONLY, also specify the starting
color of the kva range returned (UMV_KMF_COLORMATCH) and pass those to
uvm_map.

In uvm_pglistalloc, make sure the pages being returned have sequentially
advancing colors (so they can be mapped in a contiguous address range).
Add a few missing UVM_FLAG_COLORMATCH flags to uvm_pagealloc calls.

Make the socket and pipe loan color-safe.

Make the mips pmap enforce strict page color (color(VA) == color(PA)).

Extend PCU:
- Add pcu_ops_t::pcu_state_release() operation for PCU_RELEASE case.
- Add pcu_switchpoint() to perform release operation on context switch.
- Sprinkle const, misc.  Also, sync MIPS with changes.

Per discussions with matt@.

Deal with uarea mapped in either kseg0 or xkphys.

Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code.  (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.

sync with head

Sync with HEAD

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

Sync with HEAD

Make vmapbuf() return success/error and make physio deal with a
failure.

Remove clause 3 (UCB advertising clause) from the University of Utah
copyright.  Confirmed by Mike Hibler, mike at cs.utah.edu - thanks!
Also, merge UCB and Utah copyright texts back into one, as they
originally were.

Extra verification by snj@.

Sync with HEAD

Add support for the Extensible MIPS ("eMIPS") platform.  The
NetBSD/emips port runs on Xilinx and Beecube FPGA systems and the
Giano system simulator.

eMIPS is a platform developed at Microsoft Research for researching
reconfigurable computing.  eMIPS allows dynamic loading and scheduling
of application-specific circuits for the purpose of accelerating
computations based on the current workload.

NetBSD eMIPS support for NetBSD 4.x was written at Microsoft Research
by Alessandro Forin and Neil Pittman.  Microsoft Corporation has
donated full copyright to The NetBSD Foundation.

Platform support for eMIPS is the first part of Microsoft's
contribution.  The second part includes the hardware accelerator
framework and will be proposed on tech-kern soon.

Retire struct user, remove sys/user.h inclusions.  Note sys/user.h header
as obsolete.  Remove USER_TO_UAREA/UAREA_TO_USER macros.

Various #include fixes and review by matt@.

Janitorial work.
Move emulation prototypes here and get rid of StudLyCaps.
Remove kludgery for lwp/setfunc trampoline and just grab them of the damn
structure.
Make mips_locore_jumpvec contain the routines that don't get reassigned
and move wbflush to mips_locoresw since it does get overridden.

Fix a panic message.

- make sure cpu_switchto() not to touch MIPS_CURLWP register at newlwp
  switchframe restoration stage.
- discard MIPS_CURLWP assignments exposed in cpu_lwp_fork() and
  cpu_setfunc().
- use plain 'jal' instruction to call lwp_startup().

only copy PK_32, left rest of p_flag along.

Add support for setting/clearing PK_32 on _LP64 kernels.  Make cpu_proc_fork
a real function and add it to vm_machdep.c and let it copy PK_32 on fork.
Properly clear/set PK_32 depending on ABI in setregs.  Lack of PX_32 use
tracked down by Cliff Neighbors.  [Ya! ps now works!]

sync with head

Fix comment.

Split FPU support into separate file and keep internals private to that file.
Make it MPSAFE.  Change interface to be very similar to what's used on other
architectures.
Add l_md.md_fpcpu to mdlwp (needed for MPSAFE)
Move pridtab from <mips/cpu.h> to <mips/locore.h>
Add initial common IPI dispatcher.
Split cpu_* routines from mips_machdep.c into cpu_subr.c
Add cpu_startup_common which has the code replicated in half-dozen
plus machdep.c files.

Completely redo how interrupts and SPL are handled in NetBSD/mips.
[XXX locore_mips1.S still needs to adapted.]

Nested interrupts now work.  Except for MIPS_SOFT_MASK and MIPS_SR_INT_IE,
how interrupts work is completely abstracted.  spl is handled through the
mips_splsw table.  Direct manipulation of the status register is no longer
done (except for MIPS_SR_INT_IE).  A new <mips/intr.h> contains the common
IPL/IST/spl* definitions for all ports.

Interrupt delivery is completely different.  Clock interrupts may interrupt
device interrupts.  ci_idepth is now handled by the caller of cpu_intr as
are softints (both can be optimized/simplified in the case of interrupts of
usermode code).  cpu_intr has new arguments and now get called at IPL_HIGH
with MIPS_SR_INT_IE set and its logic is:

void
cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
	int ipl;
	uint32_t pending;
	while (ppl < (ipl = splintr(&pending))) {
		splx(ipl);		/* enable interrupts */
		<handle pending interrupts>
		(void)splhigh();	/* disable interrupts */
	}
}

mipsX_subr.S has been reworked.  All user handlers (user_intr, systemcall,
user_gen_exception) now use common return to usermode code in lwp_trampoline.
ast() has changed to void ast(void) since the previous pc argument was never
used.

The playstation IPL_ICU_MASK support has been nuked.
MIPS_DYNAMIC_STATUS_MASK may soon be nuked soon.

A bunch of debugging code was left conditionalized by PARANOIA.  If this
code detects a bug, it will enter an infinite loop.  It is expected that
the kernel will be debugged in a simulator or with a hardware debugger so
that the state at that point can be analyzed.

remove a debugging printf.  cleanup the reinit of the lwp.

Add __HAVE_FAST_SOFTINTS support.
Add routine to remap an uarea via a direct-mapped address.  This avoids
TLB machinations when swtching to/from the softint thread.  This can only
be done for lwp which won't exit.

Merge frame into trapframe.  While this costs a bit more stack space on
kernel exceptions, the resulting simplifications are worth it.  This is
a step to fast softints and kernel preemption.

trapframe now includes a struct reg instead of a separate array of registers.

Change MIPS_CURLWP from s7 to t8.  In a MALTA64 kernel, s6 is used 9155 times
which means the compiler could really use s7 is was free to do so.  The least
used temporary was t8 (288 times).  Once the kernel was switched to use t8 for
MIPS_CURLWP, s7 was used 7524 times.

Additionally a MALTA32 kernel shrunk by 6205 instructions (24820 bytes) or
about 1% of its text size.

[For some reason, pre-change t1 was never used and post change t2 was never
used.  Not sure why.]

fix a comment to tell register S7 ($23) is used for curlwp pointer.

Make sure the kernel pages allocated for vmmapbuf have the same page color.

Get rid of l_addr references pulled in via merge.

Merge from matt-nb5-mips64
Merge mips-specific arch files.

cpu_lwp_fork (MIPS): replace l_addr with uvm_lwp_getuarea(), clean up a little.

Use lwp_getpcb() on mips, powerpc and sh3, clean from struct user usage.

Remove uarea swap-out functionality:

- Addresses the issue described in PR/38828.
- Some simplification in threading and sleepq subsystems.
- Eliminates pmap_collect() and, as a side note, allows pmap optimisations.
- Eliminates XS_CTL_DATA_ONSTACK in scsipi code.
- Avoids few scans on LWP list and thus potentially long holds of proc_lock.
- Cuts ~1.5k lines of code.  Reduces amd64 kernel size by ~4k.
- Removes __SWAP_BROKEN cases.

Tested on x86, mips, acorn32 (thanks <mpumford>) and partly tested on
acorn26 (thanks to <bjh21>).

Discussed on <tech-kern>, reviewed by <ad>.

sync with head

To be consistent, always cast pointers to (intptr_t) even if the address is
in userspace.

Reviewed By:	matt

Use the new symbolic constants for label_t.
Use label_t where appropriate.
Add some LP64 KASSERTs

Use VM_MIN_KERNEL_ADDRESS instead of MIPS_KSEG2_START.
Switch to MIPS_KSEG?_P

Deal with fp save/restore changes.  Remove some more unneeded casts in trap.

Cast MIPS_K* to vaddr_t
Fix comments in cpu_lwp_fork
Stop casting l_md.md_regs

if USPACE <= PAGE_SIZE then the (single) upage will be mapped in kseg0 or xphys and cpu_swapin is null func.

sync with head.

Only include md_uptes if USPACE > PAGE_SIZE

sync with head

Pull up following revision(s) (requested by martin in ticket #799):
	sys/arch/mips/include/locore.h: revision 1.79
	sys/arch/mips/mips/locore_mips1.S: revision 1.65
	sys/arch/mips/mips/mipsX_subr.S: revision 1.28
	sys/arch/mips/mips/mips_machdep.c: revision 1.211
	sys/arch/mips/mips/vm_machdep.c: revision 1.123
Do not use the same trampoline for cpu_lwp_fork and cpu_setfunc - only
the former needs to call lwp_startup().

Pull up following revision(s) (requested by martin in ticket #799):
	sys/arch/mips/include/locore.h: revision 1.79
	sys/arch/mips/mips/locore_mips1.S: revision 1.65
	sys/arch/mips/mips/mipsX_subr.S: revision 1.28
	sys/arch/mips/mips/mips_machdep.c: revision 1.211
	sys/arch/mips/mips/vm_machdep.c: revision 1.123
Do not use the same trampoline for cpu_lwp_fork and cpu_setfunc - only
the former needs to call lwp_startup().

Do not use the same trampoline for cpu_lwp_fork and cpu_setfunc - only
the former needs to call lwp_startup().

sync with head.

Sync with HEAD.

Sync with HEAD.

Update haad-dm branch to haad-dm-base2.

Make the emulations, exec formats, coredump, NFS, and the NFS server
into modules. By and large this commit:

- shuffles header files and ifdefs
- splits code out where necessary to be modular
- adds module glue for each of the components
- adds/replaces hooks for things that can be installed at runtime

Sync with HEAD.

Merge wrstuden-revivesa into HEAD.

Initial checkin of re-adding SA. Everything except kern_sa.c
compiles in GENERIC for i386. This is still a work-in-progress, but
this checkin covers most of the mechanical work (changing signalling
to be able to accomidate SA's process-wide signalling and re-adding
includes of sys/sa.h and savar.h). Subsequent changes will be much
more interesting.

Also, kern_sa.c has received partial cleanup. There's still more
to do, though.

sync with HEAD

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Sync with HEAD

Sync with HEAD.

sync with head.

Sync with HEAD.

Sync with HEAD.

Pull up a change from HEAD: don't start new LWPs with interrupts enabled.

cpu_lwp_fork: don't rely on struct mdlwp being zeroed in advance.

Sync with HEAD.

Sync with HEAD.

Don't set PSL_LOWIPL to SR on switching to lwp_trampoline().
If interrupts are enabled when kernel is switched to lwp_trampoline(),
we could get lock errors by interrupts before lwp_unlock() in lwp_startup()
is called. The spl is lowered by spl0() in lwp_startup() after lwp_unlock().

Ok'ed by mhitch@ and ad@ on port-mips.

Sync with head.

Sync with head.

Update to HEAD.

merge yamt-idlelwp branch.  asked by core@.  some ports still needs work.

from doc/BRANCHES:

	idle lwp, and some changes depending on it.

	1. separate context switching and thread scheduling.
	   (cf. gmcgarry_ctxsw)
	2. implement idle lwp.
	3. clean up related MD/MI interfaces.
	4. make scheduler(s) modular.

- Further adaptations to MIPS for the yamt-idlelwp branch.
- Make curlwp a register variable on MIPS.

Initial changes for MIPS. Not yet working under gxemul.

Sync with HEAD.

Use (char *) on pointer arith.

Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

TRUE -> true, FALSE -> false

sync with head.

Merge newlock2 to head.

Remove support for SA. Ok core@.

Make mips systems work.

sync with head.

sync with head

sync with head.

Make cpu_coredump dependent on COREDUMP

Use vaddr_t for virtual addresses.  Don't cast pointers with int or
unsigned, use intptr_t or uintptr_t as appropriate.

sync with head.

Sync with head.

sync with head - hopefully this will work

sync with head.

Merge 2006-03-31 NetBSD-current into the "peter-altq" branch.

use uvm_km_alloc() instead of uvm_map().

merge ktrace-lwp.

Pull up following revision(s) (requested by tsutsui in ticket #961):
	sys/arch/mips/mips/cache.c: revision 1.27
	sys/arch/mips/include/cache.h: revision 1.8
	sys/arch/mips/mips/pmap.c: revision 1.158
	sys/arch/mips/mips/vm_machdep.c: revision 1.106
	sys/arch/mips/mips/mem.c: revision 1.30
	sys/arch/mips/include/pmap.h: revision 1.47
Add a workaround to handle virtual alias which may cause data corruption
on R5000/Rm52xx machines:
- Add a new global variable mips_cache_virtual_alias in mips/cache.c,
  which indicates that VIPT cache on the CPU could cause virtual alias
  and software support is required to handle it. (i.e. no VCED/VCEI)
- Add several cache flush/invalidate ops around KSEG0 access which
  might cause virtual alias if mips_cache_virtual_alias is true.
  (note checking mips_sdcache_line_size isn't valid for R5000/Rm52xx
   because only R4000/R4400 with L2 cache have VCED/VCEI)
- Remove a global variable mips_sdcache_forceinv, which is now superseded
  by new mips_cache_virtual_alias.
While here, also change some R4000/R4400 cache ops:
- Don't override mips_cache_alias_mask and mips_cache_prefer_mask with
  values based on MIPS3_MAX_PCACHE_SIZE for R4000/R4400 with L2 cache
  because it's still worth to reduce VCED/VCEI.
- Flush dcache in pmap_zero_page(9) unconditionally on all MIPS_HAS_R4K_MMU
  CPUs and remove cache flush code from cpu_lwp_fork() in vm_machdep.c.
Thanks to Markus W Kilbinger for testing patches on port-cobalt/port-mips.
XXX This fix is just a workaround because it doesn't handle all possible
XXX virtual aliases. As discussed on port-mips, maybe the real fix
XXX for virtual alias is to change MI UVM to adapt it to VIPT cache.
XXX (all VA mappings against the same PA must have the same VAC index etc.)

Sync with HEAD. Here we go again...

Rework the coredump code to have no explicit knownledge of how coredump
i/o is done.  Instead, pass an opaque cookie which is then passed to a
new routine, coredump_write, which does the actual i/o.  This allows the
method of doing i/o to change without affecting any future MD code.
Also, make netbsd32_core.c [re]use core_netbsd.c (in a similar manner that
core_elf64.c uses core_elf32.c) and eliminate that code duplication.
cpu_coredump{,32} is now called twice, first with a NULL iocookie to fill
the core structure and a second to actually write md parts of the coredump.
All i/o is nolonger random access and is suitable for shipping over a stream.

sync with -current

Sync with HEAD.

merge yamt-km branch.
- don't use managed mappings/backing objects for wired memory allocations.
  save some resources like pv_entry.  also fix (most of) PR/27030.
- simplify kernel memory management API.
- simplify pmap bootstrap of some ports.
- some related cleanups.

sync with head.

Add a workaround to handle virtual alias which may cause data corruption
on R5000/Rm52xx machines:
- Add a new global variable mips_cache_virtual_alias in mips/cache.c,
  which indicates that VIPT cache on the CPU could cause virtual alias
  and software support is required to handle it. (i.e. no VCED/VCEI)
- Add several cache flush/invalidate ops around KSEG0 access which
  might cause virtual alias if mips_cache_virtual_alias is true.
  (note checking mips_sdcache_line_size isn't valid for R5000/Rm52xx
   because only R4000/R4400 with L2 cache have VCED/VCEI)
- Remove a global variable mips_sdcache_forceinv, which is now superseded
  by new mips_cache_virtual_alias.

While here, also change some R4000/R4400 cache ops:
- Don't override mips_cache_alias_mask and mips_cache_prefer_mask with
  values based on MIPS3_MAX_PCACHE_SIZE for R4000/R4400 with L2 cache
  because it's still worth to reduce VCED/VCEI.
- Flush dcache in pmap_zero_page(9) unconditionally on all MIPS_HAS_R4K_MMU
  CPUs and remove cache flush code from cpu_lwp_fork() in vm_machdep.c.

Thanks to Markus W Kilbinger for testing patches on port-cobalt/port-mips.


XXX This fix is just a workaround because it doesn't handle all possible
XXX virtual aliases. As discussed on port-mips, maybe the real fix
XXX for virtual alias is to change MI UVM to adapt it to VIPT cache.
XXX (all VA mappings against the same PA must have the same VAC index etc.)

vunmapbuf: unmap correct range.

convert arch/mips to new apis.

Sync with HEAD.

Use "NULL" instead of "(something-or-other *)0".

Fix the sync with head I botched.

Sync with HEAD.

There's no need to pass a proc value when using UIO_SYSSPACE with
vn_rdwr(9) and uiomove(9).

OK'd by Jason Thorpe

Sync with HEAD

Garbage-collect pagemove(); nothing use it anymore (YAY!!!)

Sync with HEAD

Catch up with the November 2002 (!!) change to remove ABI exposure
from cpu_fork and the proc trampoline.  pthreads programs that fork
now work (at least the regress test case does).
Program reported by Florian Stöhr on port-sgimips.

ANSIfy, wrap long lines.

Rearrange process exit path to avoid need to free resources from different
process context ('reaper').

From within the exiting process context:
* deactivate pmap and free vmspace while we can still block
* introduce MD cpu_lwp_free() - this cleans all MD-specific context (such
  as FPU state), and is the last potentially blocking operation;
  all of cpu_wait(), and most of cpu_exit(), is now folded into cpu_lwp_free()
* process is now immediatelly marked as zombie and made available for pickup
  by parent; the remaining last lwp continues the exit as fully detached
* MI (rather than MD) code bumps uvmexp.swtch, cpu_exit() is now same
  for both 'process' and 'lwp' exit

uvm_lwp_exit() is modified to never block; the u-area memory is now
always just linked to the list of available u-areas. Introduce (blocking)
uvm_uarea_drain(), which is called to release the excessive u-area memory;
this is called by parent within wait4(), or by pagedaemon on memory shortage.
uvm_uarea_free() is now private function within uvm_glue.c.

MD process/lwp exit code now always calls lwp_exit2() immediatelly after
switching away from the exiting lwp.

g/c now unneeded routines and variables, including the reaper kernel thread

Hide the register number constants behind an _R_ prefix, and also
rename FPBASE to _FPBASE, so that we avoid polluting the user's
name space when e.g. <sys/ptrace.h> is included.  Previously, the
PC symbol in mips/regnum.h would conflict with the declaration of
the external variable by the same name in termcap.h, as discovered
by the ``okheaders'' regression test.

Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

LWP-ify to get algor/P4032 working.

Back out the lwp/ktrace changes. They contained a lot of colateral damage,
and need to be examined and discussed more.

Fix more needless 'struct proc *' to 'struct lwp *' fallout.

Use PAGE_SIZE rather than NBPG.

Assign to pcb->pcb_context[] in the same order in cpu_lwp_fork() and
cpu_setfunc().

Merge the nathanw_sa branch.

Merge switch_exit() and switch_lwp_exit().

Sync with HEAD.

Remove o32 stack layout exposure form cpu_fork().
Tested on R4000 and R3000.

Catch up to -current

Change pmap_kenter_pa/pmap_kremove pair back to pmap_enter/pmap_remove
in fear of the case choosen kva results in occupying inconsistent
distinctive cache lines of uva.

Use pmap_enter_pa and pmap_kremove for vmapbuf/vunmapbuf, respectively.
Have variable names renamed for the logic clarity.

Fix signed/unsigned comparison warnings.

Curproc->curlwp renaming.

Change uses of "curproc->l_proc" back to "curproc", which is more like the
original use. Bare uses of "curproc" are now "curlwp".

"curproc" is now #defined in proc.h as ((curlwp) ? (curlwp)->l_proc) : NULL)
so that it is always safe to reference curproc (*de*referencing curproc
is another story, but that's always been true).

Pull in <sys/sa.h>

Catch up to -current.
(CVS: It's not just a program. It's an adventure!)

Catch up with -current.

Add support for MIPS32 and MIPS64 architectures:
 - Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 - ANSIfy.

Don't need to declare phys_map - it is declared in <uvm/uvm_extern.h>.

Sync kqueue branch with -current.

Catch up to -current.

cpu_fork() -> cpu_lwp_fork().  This logically forks an LWP, not a
complete process.  As noted by Gregory McGarry on tech-kern.

Fix a small typo in comment.

Inital support for Scheduler Activation on MIPS architectures.

Compiles for sgimips.  Needs more work in locore.S in order to reach
single user and beyond.

file vm_machdep.c was added on branch nathanw_sa on 2001-11-17 23:43:45 +0000

Merge the thorpej-mips-cache branch onto the trunk.  This is an
overhaul of how caches are handled for NetBSD's MIPS ports.

Update for the new cache code.  Some careful code review is needed
here, esp. by people who have done recent MIPS pmap hacking.

R5900 support.
 COP0_SYNC
	In R5900 mtc0, tlbr, tlbp, tlbwi, tlbwr must be followed by sync.p.
	if defined MIPS3_5900, COP0_SYNC is defined as sync.p. else nothing.
 IPL_ICU_MASK
	mask interrupt directly ICU instead of SR.IM.
	I've added this feature to support software interrupt for R5900.
	and this option may be useful for platform which has cascaded ICU.

Catch up with -current.

Update the kqueue branch to HEAD.

Update pmap_update to now take the updated pmap as an argument.
This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment.

Currently this is a no-op on most platforms, so they should see no difference.

Reviewed by Jason.

Merge Aug 24 -current into the kqueue branch.

add missing pmap_update().

Pullup [shin]:

sys/arch/mips/mips/locore_mips3.S		1.70
sys/arch/mips/mips/vm_machdep.c			1.77-1.78

  Fix bugs in handling of SR on mips3 machines, causing TLB miss panics.

in vunmapbuf(), call pmap_remove() explicitly since uvm_km_free_wakeup()
will soon no longer do it for us.

Catch up to -current.

replace vm_map{,_entry}_t with struct vm_map{,_entry} *.

"opt_ddb.h" should be included at the beginning of source file,
because some headers (in this case <systm.h>) refers symbols (e.g. DDB)
defined in the opt_ddb.h

Pull up revisions 1.75-1.76 (via patch, requested by simonb):
  Make sure new processes (and kernel threads) gets created in spl0
  level.

Rather better to have |= to make sure spl0 condition, allowing to preserve
processor model specific SR bit pattern on pcb0 initialization.

Set SR to PSL_LOWIPL rather than MIPS_INT_MASK | MIPS_SR_INT_IE,
as the former accounts for some mips3-related options.

From Rafal K. Boni.

Add comment to tell what cpu_fork() does around at its bottom.

What's wrong; the initial SR value in pcb0 gets overwritten before
the first kthread_create1() is called.  For a normal process which
has user mode it doesn't matter because proc_trampoline() makes
the process to have spl0 during exception return path to user mode,
however, kthreads stay in kernel mode mistakenly left in splhigh
condition.  The trouble is visible as severe clock drifts when
system activity is high.

Make sure to have spl0 condition whenever a new thread of control
is created.  System kthreads are mistakenly left splhigh state.

pcb0 has an initial SR value for spl0 condition which are expected to
be propagated to all of children

Sprinkle pmap_update() calls after calls to:
- pmap_enter()
- pmap_remove()
- pmap_protect()
- pmap_kenter_pa()
- pmap_kremove()
as described in pmap(9).

These calls are relatively conservative.  It may be possible to
optimize these a little more.

Sync with HEAD

Catch up with -current.

include "opt_ddb.h" explicitely

Sync with HEAD.

Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.

Add mips_indexof() macro to make code for checking the cache index
easier to read.

Introduce 'segbase' global variable to hold the pointer to current
process's segtab, retiring 'pcb_segtab' field from 'struct pcb'.
This would be another MULTIPROCESSOR unfriendly and the necessity
might be eliminated when the way to hold PTE is redesigned.

Fix vmapbuf() to call uvm_km_valloc_perfer_wait() call, but trunc_page()
to the prefer arg so we free the correct page.

Back-out vmapbuf() change for now as locally it has been found to sleep
in some circumstances that don't sleep when not using pmap_prefer().

Use new uvm_km_valloc_prefer_wait() in vmapbuf().  This lets the K2
mapping of b_data have the same virtual index, so the mapping does
not degenerate into uncached in pmap_enter().

remove include of <vm/vm.h>. <vm/vm.h> -> <uvm/uvm_extern.h>

remove/move more mach vm header files:

	<vm/pglist.h> -> <uvm/uvm_pglist.h>
	<vm/vm_inherit.h> -> <uvm/uvm_inherit.h>
	<vm/vm_kern.h> -> into <uvm/uvm_extern.h>
	<vm/vm_object.h> -> nothing
	<vm/vm_pager.h> -> into <uvm/uvm_pager.h>

also includes a bunch of <vm/vm_page.h> include removals (due to redudancy
with <vm/vm.h>), and a scattering of other similar headers.

Sync w/ netbsd-1-5-base.

backout previous change.
cache operation in cpu_fork() is necessary for CPU's which
detect virtual alias by hardware (ex. R4000 with secondary cache).

Remove unnecessary HitFlushCache from cpu_fork(). From Toru Nishimura.

rename
	vad_to_pfn() -> mips_paddr_to_tlbpfn()
	pfn_to_vad() -> mips_tlbpfn_to_paddr()
as suggested by thorpej on port-mips Mar 27.

Add a missing closing parenthesis.

FPA ownership is now guarded by MDP_FPUSED flag and there is no necessity
to have #if ... around savefpregs() calls.

Put addtional checks to see the curproc is an FPA owner process.

Rather than starting init and creating kthreads by forking and then
doing a cpu_set_kpc(), just pass the entry point and argument all
the way down the fork path starting with fork1().  In order to
avoid special-casing the normal fork in every cpu_fork(), MI code
passes down child_return() and the child process pointer explicitly.

This fixes a race condition on multiprocessor systems; a CPU could
grab the newly created processes (which has been placed on a run queue)
before cpu_set_kpc() would be performed.

Appease gcc.

Take a straight way for pagemove() PTE manipulation, abandoning to
use MIPS_TBRPL().  When PTEs are modified, both src and dst TLBs
are invalidated.  MIPS3 single TLB entry has paired double PTE
and pagemove() likely walks through multiple pages.  The positive
effect of of MachTLBUpdate() or TBRPL() is unclear.

Fix a typo in the previous change.

Change the way to implement zero copy data move in pagemove() using
MIPS_TBRPL().  It saves about 20 instructions to run for each
iteration, and avoids TLB polution.  Currently works for MIPS1 only
configuration.

- Move a loop invariant of 'if (CPUISMIPS3)' out of pagemove().
- XXX I'm not sure whether the anticipatory MachTLBUpdate(to, pte) is
  a gain or loss on runtime.  If not a loss, it should be MIPS_TBIS().

- Implement mips3_TBIAP().
- Remove obsoluted routines in locore_mips3.S
- addiu -> addu, andi -> and, ori -> or.

Move fpcurproc declaration to <mips/cpu.h>.

Don't `extern' function declarations.  While we're there, remove trailing
blank lines and white space.

Merge parts of chs-ubc2 into the trunk:
* Remove the casts to vaddr_t from the round_page() and trunc_page() macros to
  make them type-generic, which is necessary i.e. to operate on file offsets
  without truncating them.
* In due course, cast pointer arguments to these macros to an appropriate
  integral type (paddr_t, vaddr_t).

Originally done by Chuck Silvers, updated by myself.

Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast.
Many thanks.

Actually use KSEG1 offset for KSEG1 addresses in kvtophys().
From Jeff Smith and Ethan Solomita at Geocast.

Fix PR9240: comment above cpu_fork() out of synch with reality on most ports.
(comment change only, but was wrong for more than just i386).

split 'options SOFTFLOAT' to

	NOFP		don't touch FPU registers in kernel
	SOFTFLOAT	emulate FPU instructions in kernel

Pull up to last week's -current.

CL* discarding.

on port-mips@netbsd.org:
Shuichiro URATA <ur@a-r.org> makes kernel softfloat emulation code.

http://www.a-r.org/~ur/softfloat1116.diff.gz

is Patch for
      sys/arch/mips/conf/files.mips
      sys/arch/mips/mips/fp.S
      sys/arch/mips/mips/fpemu.c
      sys/arch/mips/mips/genassym.cf
      sys/arch/mips/mips/locore.S
      sys/arch/mips/mips/mips_machdep.c
      sys/arch/mips/mips/process_machdep.c
      sys/arch/mips/mips/trap.c
      sys/arch/mips/mips/vm_machdep.c
After apply this patch,pmax package binary works on hpcmips!

Sync with -current

Update for pmap_enter() API change.  No functional difference.

Update from trunk.

Change the pmap_extract() interface to:
	boolean_t pmap_extract(pmap_t, vaddr_t, paddr_t *);
This makes it possible for the pmap to map physical address 0.

Sync w/ -current.

Clone vmapbuf() and vunmapbuf() from the Alpha port.

- Change a symbolic name of TLB entrylo from 'PG_M' to 'PG_D' to reflect
processor design.  MIPS 'dirty bit' is not the same as i386 'dirty bit'.
There is a growing concern of misuse in NetBSD/mips.

Generally update the comment above vunmapbuf().

Generally update the comment above the vmapbuf() implementations.

- Adjust descriptive comment of cpu_fork() which returns nothing and
returns once.
- Minor fixes in mips/vm_machdep.c.

Allow the caller to specify a stack for the child process.  If NULL,
the child inherits the stack pointer from the parent (traditional
behavior).  Like the signal stack, the stack area is secified as
a low address and a size; machine-dependent code accounts for stack
direction.

This is required for clone(2).

Nuke register and remove trailling white space.

completely remove Mach VM support.  all that is left is the all the
header files as UVM still uses (most of) these.

* Elimination of UADDR/KERNELSTACK

   Affected files:
	include/mips_param.h, include/pcb.h,
	mips/locore_mips1.S, mips/locore_mips3.S,
	mips/mips_machdep.c, mips/vm_machdep.c

   Issue:

So far, NetBSD/mips has not successfully got rid of fixed-address
kernel stack.  USPACE (two 4KB pages) of each process has two distinct
KSEG2 addresses, both refer to a single physical storage; one address
for fixed range [ UADDR .. KERNELSTACK ), and another for "normal" KSEG2
address which was allocated by kernel memory manager and unique to each
others of processes.

"Doubly mapped" USPACE complicates context switch.  Both address ranges
have to be managed with a special care of "wired" TLB entries which
are never replaced until next context switch to ensure no TLB miss for
USPACE access.  It's equally crumbersome that MIPS processor's cache
machinary gets be confused about USPACE contents because there are two
distinct KSEG2 addresses to manipulate one physical storage.

   Solution:

Purge KERNELSTACK constant for kernel stack pointer and replace
it with process unique values.  Kernel stack bottom is located at
'curproc->p_addr + USPACE'.  Context switch is simplified as it unloads
half of TLB hardwiring burden.  It just manages the unique KSEG2 address
of each USPACE to be wired.  As the side effect, switch_exit() has no
MIPS processor ISA dependent code anymore.  It switchs kernel stack to
proc0's USPACE which has KSEG0 address and no need of TLB entry.

* Extensive use of 'genassym.cf'

To hide target port dependent and/or processor register size dependent
constants from assembler routines, 'genassym.cf' now has an extentive
set of definitions for various constants and offset values of
structural objects.  This change will contribute possible NetBSD/mips64
portability too.

* Separation and rename of locore_r2000/_r4000.S

Those files are now indepedent standalones from locore.S to ease
maintainance works, and renamed to match MIPS processor ISA version.

* Changes in kernel mode exception handlers

Kernel mode exception handlers hold exception contexts by pushing a
certain set of register values on stack for resuming kernel mode
processing.  This context is now represented with 'struct trapframe',
which is smaller than full scale (user mode) exception context 'struct
frame'.  Stack consumption of kernel mode exception services is now
similar to 4.4BSD/mips.

* Relocation of exception frame

User mode context 'struct frame' is moved to the very bottom of kernel
stack at 'curproc->p_addr + USPACE - sizeof(struct frame)'  This change
saves a bit of instructions on every return to user processes as it
eliminates reference to global variable 'curpcb' each time.

* Refurblished DDB backtrace routine

It's a growing concern to maintain stacktrace() code correctly.  It
could be simplified by enforcing special arrangements for some of
obscure locore routines which violate usual coding conventions.

New backtrace code searchs for certain instructions peculiar to any of
function tails.  Specifically, "jr ra" for normal function returns, "jr
k0" for MIPS1 exception handlers and "eret" for MIPS3 handlers.

* Support for 64-bit safe user code
    Affected Files:
	${ARCH}/include/pubassym.cf lib/libc/arch/mips/gen/*setjmp*
	include/setjmp.h mips/include/[lots] mips/mips/[lots]

    Solution:

	We define macros REG_L/REG_S and SZREG for loading and storing
	registers and for the size of registers.  The exact meaning
	of these is controlled by a macro (currently _MIPS64) which
	allows one to treat the registers as either 32-bit or 64-bit.
	There are data types mips_reg_t and mips_fpreg_t which represent
	the true register sizes, and avoid confusing register_t.

	We needed a way to dynamically gen the structure sizes of things
	like sigcontext for setjmp.h, so we defined a pubassym.cf for
	libc routines like setjmp and longjmp.

	NetBSD/mips allows ${ARCH}'s to be defined which preserve
	all 64-bits of registers across user context switches.  There
	are still a few niceties to clean up for kernel mode context
	switches.

* Support for QED 52xx processors
    Affected Files:
	mips/locore_mips3.S mips/pmap.c include/locore.h

    Issue:
	The QED 52xx family of processors are targeted at low cost
	embedded systems, (i.e. CPUs ~$30) for systems like routers, printers,
	etc.  We have added preliminary support for some of the idiosyncrasies
	of this processor, e.g. no L2 cache, etc.  More work needs to be
	done here because with a modest 2-way  L1 cache, some of the rampant
	flushing has significant performance implications.  However,
	it doesn't crash, which is a start.

    Solution:
	A routine for flushing the cache based on virtual addresses was added;
	a routine which deals with the two-way set associativity of the
	5230 L1 cache was added, accomodations to 5230's instruction hazards
	were added.


* TLB Miss code for mips3/mips4 processors cleaned up significantly.
    Affected Files:
	mips/locore_mips3.S mips/vm_machdep.c include/locore.h mips_machdep.c
    Issue:
	The TLB Miss handler exceeded the allowed size, which wasn't
	a problem because there was no handler for when the processor
	was in 64-bit mode.  The handler for invalid TLB exceptions
	also appears to have much vestigial code, which made it
	difficult to understand.

    Solution:
	Use the XCONTEXT register to store a pointer to the segment
	map table, this coupled with removing some dead code allows
	the handlers to fit.

- Complete vm_offset_t purge for mips processor.
- bzero() -> memset() and bcopy() -> memcpy().
- Garbage collection in trap.c and db_interface.c.

- Use explicite structure member reference with 'struct frame' to alter
register values of exception frame pointed with p->p_md.md_regs.
- Local auto variable 'cpustate' in cpu_coredump() was never used correctly.

- Step forward to MIPS64 support.  Incorporate partially Caster Fu's
patches.  Still some work is missing to satisfy his QED 5230 port.

- More symbolic definitions in genassym.cf which improve possible 64bit-ness
of locore_mips{1,3}.S.

- Fix mips3 L1 cache line size detection logic in cpuarch.h as pointed by
Caster.

- Fix a bug in proc_trampoline() code in locore_mips3.S as pointed by Caster.

- Replace vm_offset_t with vaddr_t/paddr_t entirely.  Note that
NetBSD/newsmips has purged vm_offset_t too.

- Synchronize various files according to recent changes made in main trunk.

update for cpu_set_kpc() argument change

Changes to support fork_kthread():
- cpu_set_kpc() now takes void *arg third argument, passed to the
  entry point.
- cpu_fork() allows parent to be non-curproc iff parent is proc0.
  When forking non-curproc, assume its state has already been saved.
- Adjust various pieces of machine-dependent code to account of all of this.

- Split MIPS1/MIPS3 specific codes from locore.S.  They stand independently
  as locore_mips1.S and locore_mips3.S respectively.
- Change function declaration macros in asm.h.  They are now more NetBSD/alpha
  look like.  All of *.S files were changed.
- TLB dump codes now reside in db_interface.c.  Minor change was done in
  locore_mips1.S for it.

In cpu_coredump(), use MID_MACHINE rather than MID_* (whatever it expands
to).

Adjust for the new "reaper" kernel thread: do not free the vmspace and
u-area in machine-dependent code.  Instead, call exit2() to schedule
the reaper to free them for us, once it is safe to do so (i.e. we are
no longer running on the dead proc's vmspace and stack).

- kernel boot flag 'd' now means "enter DDB asap" like as other ports.
- bump cpu_model[] length as the longest name occupies over 30 characters.
- place machine_arch[] beside machine[] for clearity.
- nuke useless #include directives.
- small scale cleanup in vm_machdep.c

Don't cast the null residual pointer passed to vn_rdwr().

Add support for UVM.

Add explicit #include <vm/vm.h> before mips/pte.h is included.

* Change Sprite MACH_xxx prefix to MIPS_xxx.

* Use standard mips terminology (xxx_KSEG0, xxx_KSEG1) instead of the
  (more meaningful) Sprite names (xxx_CACHED, xxx_UNCACHED).

Merged mips1/mips3:  cache alias test in pagemove().

Use same cachesize variables for mips1 and mips3, and rename the variables
per Jonathan's request.
Remove switch_exit() declaration - it's now called via the locore jump vector.

MachHitFlushDCache() -> mips3_HitFlushDCache() outside pmap.c.

Changes for configuring both MIPS1 and MIPS3, from a merge of
similar design and code by Jason Thorpe and Jonathan Stone.

NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.

mips/include/cpu.h:
    Add CPUISMIPS3 for run-time tests of what CPU architecture level
    we're running on.

mips/include/locore.h:
    Add declarations of locore cache-size variables for ref/def toolchain.

mips/include/mips1_pte.h:
    mips1 TLB bit definitions.

mips/include/mips3_pte.h:
    mips3 TLB bit definitions.

mips/include/pte.h:
    define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
    that expand to CPU constants if only one CPU arch is configured,
    or to inline functions if both MIPS1 and MIPS3 are configured.

mips/mips/locore_r2000.S:
    Use MIPS1_PG_xxx constants inside mips1-specific code.

mips/mips/locore_r4000.S:
    Use MIPS3_PG_xxx constants inside mips3-specific code.

mips/mips/locore.S:
    Use MIPS1_PG_xxx constants inside mips3-specific code.
    Use MIPS1_PG_xxx constants inside mips1-specific code.
    (Needs more  work!)

mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
    Use MIPS3_PG_xxx constants inside mips3-specific functions,
         and MIPS1_PG_XXX inside mips1-specific code.
    Otherwise, use mips_pg_XXX_bit() macros where they apply,
    and use "if (CPUISMIPS3) { ... } else {... }" where they don't.

mips/mips/mips_machdep.c:
    Import Michael Hitch's fixes from the pmax locore-init code
    into mips_vector_init().

pmax/pmax/machdep.c:
    Use generic mips_vector_init() locore vector-init function.

Garbage-collect redundant declarations:
mips/include/locore.h:
  Add prototypes for HitFlushDCache() functions. Moe cpu_prid definition here.
mips/include/cpu.h:
  remove  cpu_prid definition.
pmax/pmax/machdep.c:
   remove local protoypes of HitFlushDCache() functions.
mips/mips/vm_machdep.c, mips/mips/vm_machdep.c::
   remove local protoypes of HitFlushDCache() functions.

Generic mips pmap/vm code: move the merged pmax mips1/mips3 vm_machdep
and pmap code to arch/mips/mips.
Use <mips/XXX.h> header files, not <machine/XXX.h>.

From Toru Nishimura: _FORKBRAINDAMAGE is gone, user process entered through
proc_trampoline().
More merged MIPS1/MIPS3 support.

lint: add prototype for kvtophys().

Eliminate vm_pmap.

backout previous kprintf change

printf -> kprintf, sprintf -> ksprintf

Add local declarations for locore functions. Fix pagemove() return
type to be void. Add explicit "int" return types.
Fix format/argument mismatches for vm_offset_t's in diagnostic messages.

Include <machine/locore.h>, to force all MIPS cpu-model specific
locore calls to go via a locore-entry jumptable.

Cast the (int) arguments  to MachTLBUpdateEntry() to avoid
warnings.  Variables TLB entries are still type-punned as either structs
or ints, without any regard, when the pmax-specific VM code passes
them as arguments to functions.

The prototyping `fixes' broke vmapbuf() and vunmapbuf(), due to a "sz"
parameter parameters shadowing locals.  Replace vmapbuf() and vunmapbuf()
with the Alpha-port versions, which are cleaner (use round_page(),
trunc_page(), etc.)

vm prototype changes

Add "kvtophys()", which maps MIPS R2000 kernel-virtual addresses to physical addresses,
so they can (e.g.) be written to DMA mapping registers.

Write out new-style core files

new RCS ID format.

bsd 4.4-lite pmax port as ported to NetBSD

upgrade to bsd 4.4-lite code base. only mod is rcsids

cpu_exit returns void

pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>

Initial revision