version 1.42, 1996/10/07 02:17:33 |
version 1.43, 1996/10/07 11:20:53 |
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* @(#)trap.c 8.5 (Berkeley) 1/11/94 |
* @(#)trap.c 8.5 (Berkeley) 1/11/94 |
*/ |
*/ |
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#if #defined(MIPS1) && !defined(MIPS3) |
#if !defined(MIPS1) && !defined(MIPS3) |
#error Neither "MIPS1" (r2000 family), "MIP3" (r4000 family) was configured. |
#error Neither "MIPS1" (r2000 family), "MIP3" (r4000 family) was configured. |
#endif |
#endif |
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Line 770 trap(statusReg, causeReg, vadr, pc, args |
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Line 770 trap(statusReg, causeReg, vadr, pc, args |
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locr0[V0] = i; |
locr0[V0] = i; |
locr0[A3] = 1; |
locr0[A3] = 1; |
} |
} |
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/* |
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* If we modified code or data, flush caches. |
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* XXX code unyderling ptrace() and/or proc fs should do this? |
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*/ |
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if (code == SYS_ptrace) |
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MachFlushCache(); |
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done: |
done: |
#ifdef SYSCALL_DEBUG |
#ifdef SYSCALL_DEBUG |
scdebug_ret(p, code, i, rval); |
scdebug_ret(p, code, i, rval); |
Line 1049 interrupt(statusReg, causeReg, pc /* XXX |
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Line 1056 interrupt(statusReg, causeReg, pc /* XXX |
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intrcnt[SOFTCLOCK_INTR]++; |
intrcnt[SOFTCLOCK_INTR]++; |
cnt.v_soft++; |
cnt.v_soft++; |
softclock(); |
softclock(); |
} |
} |
} |
} |
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Line 1139 GetBranchDest(InstPtr) |
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Line 1146 GetBranchDest(InstPtr) |
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return ((unsigned)InstPtr + 4 + ((short)InstPtr->IType.imm << 2)); |
return ((unsigned)InstPtr + 4 + ((short)InstPtr->IType.imm << 2)); |
} |
} |
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/* |
/* |
* Return the resulting PC as if the branch was executed. |
* Return the resulting PC as if the branch was executed. |
*/ |
*/ |
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Between((unsigned)a, pc, (unsigned)b) |
Between((unsigned)a, pc, (unsigned)b) |
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/* Backtraces should contine through interrupts from kernel mode */ |
/* Backtraces should continue through interrupts from kernel mode */ |
#ifdef MIPS1 /* r2000 family (mips-I cpu) */ |
#ifdef MIPS1 /* r2000 family (mips-I cpu) */ |
if (pcBetween(mips_r2000_KernIntr, mips_r2000_UserIntr)) { |
if (pcBetween(mips_r2000_KernIntr, mips_r2000_UserIntr)) { |
/* NOTE: the offsets depend on the code in locore.s */ |
/* NOTE: the offsets depend on the code in locore.s */ |
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#endif /* MIPS1 */ |
#endif /* MIPS1 */ |
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#ifdef MIPS3 /* r4000 family (mips-III cpu) */ |
#ifdef MIPS3 /* r4000 family (mips-III cpu) */ |
if (pcBetween(mips_r4000_KernIntr, mips_r4000_UserIntr) { |
if (pcBetween(mips_r4000_KernIntr, mips_r4000_UserIntr)) { |
/* NOTE: the offsets depend on the code in locore.s */ |
/* NOTE: the offsets depend on the code in locore.s */ |
(*printfn)("R4000 KernIntr+%x: (%x, %x ,%x) -------\n", |
(*printfn)("R4000 KernIntr+%x: (%x, %x ,%x) -------\n", |
pc-(unsigned)mips_r4000_KernIntr, a0, a1, a2); |
pc-(unsigned)mips_r4000_KernIntr, a0, a1, a2); |
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/* XXX fixup tests after cutting and pasting in locore.S */ |
/* XXX fixup tests after cutting and pasting in locore.S */ |
/* R4000 exception handlers */ |
/* R4000 exception handlers */ |
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#ifdef MIPS1 /* r2000 family (mips-I cpu) */ |
if (pcBetween(mips_r2000_KernGenException, mips_r2000_UserGenException)) |
if (pcBetween(mips_r2000_KernGenException, mips_r2000_UserGenException)) |
subr = (unsigned) mips_r2000_KernGenException; |
subr = (unsigned) mips_r2000_KernGenException; |
else if (pcBetween(mips_r2000_UserGenException,mips_r2000_KernIntr)) |
else if (pcBetween(mips_r2000_UserGenException,mips_r2000_KernIntr)) |
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else if (pcBetween(mips_r2000_UserIntr, mips_r2000_TLBMissException)) |
else if (pcBetween(mips_r2000_UserIntr, mips_r2000_TLBMissException)) |
subr = (unsigned) mips_r2000_UserIntr; |
subr = (unsigned) mips_r2000_UserIntr; |
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else |
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#endif /* MIPS1 */ |
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/* R4000 exception handlers */ |
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#ifdef MIPS3 /* r4000 family (mips-III cpu) */ |
#ifdef MIPS3 /* r4000 family (mips-III cpu) */ |
else if (pcBetween(mips_r4000_KernGenException, mips_r4000_UserGenException)) |
/* R4000 exception handlers */ |
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if (pcBetween(mips_r4000_KernGenException, mips_r4000_UserGenException)) |
subr = (unsigned) mips_r4000_KernGenException; |
subr = (unsigned) mips_r4000_KernGenException; |
else if (pcBetween(mips_r4000_UserGenException,mips_r4000_KernIntr)) |
else if (pcBetween(mips_r4000_UserGenException,mips_r4000_KernIntr)) |
subr = (unsigned) mips_r4000_UserGenException; |
subr = (unsigned) mips_r4000_UserGenException; |
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else if (pcBetween(mips_r4000_UserIntr, mips_r4000_TLBMissException)) |
else if (pcBetween(mips_r4000_UserIntr, mips_r4000_TLBMissException)) |
subr = (unsigned) mips_r4000_UserIntr; |
subr = (unsigned) mips_r4000_UserIntr; |
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else |
#endif /* MIPS3 */ |
#endif /* MIPS3 */ |
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else if (pcBetween(splx, MachEmptyWriteBuffer)) |
if (pcBetween(splx, wbflush)) |
subr = (unsigned) splx; |
subr = (unsigned) splx; |
else if (pcBetween(cpu_switch, fuword)) |
else if (pcBetween(cpu_switch, fuword)) |
subr = (unsigned) cpu_switch; |
subr = (unsigned) cpu_switch; |