CVS log for src/sys/arch/mips/mips/mips_machdep.c

Up to [cvs.NetBSD.org] / src / sys / arch / mips / mips

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Keyword substitution: kv
Default branch: MAIN

Remove funny blank line.

Add Cavium CN68xx to list of known CPUs.

Trailing whitespace.

s/fist/first/

Sync w/ HEAD.

s/leading spaces/tabs/

Sync with HEAD.

Sync with HEAD.

Work in progress for MIPS modules.  Only tested on mipseb64, not yet
enabled anywhere.

Octeon CN70XX CPUs have a COP0 config5 register.
XXX: The presense of these are defined by the MIPS architecture, should probe.

enable dumppcb.

Fix TLB count probe on MIPS32R2+/MIPS64R2+ for CPUs that have a Config4
register with a Config4[MMUExtDef] value.

CN70XX also has Config6 (CvmMemCtl2) and Config7 (CvmVMConfig) registers.

CN70XX has a config4 CP0 register.

Pull up following revision(s) (requested by simonb in ticket #1016):

	sys/arch/mips/mips/mips_machdep.c: revision 1.294

Fix mm_md_kernacc() for 64 bit kernels (including n32):
 - FAULT for any physical address less than start of cached XKPHY address.
 - Pass any remaining physical address less then end of RAM.
 - Pass any remaining physical address within the KEGS0 kernel address range.

Ignore all remaining addresses and fall back to uvm_kernacc() for checking
virtual address ranges.

Fixes pmap(1) (and probably other kmem grovellers).

Copy "mach reset" logic from arm32 recently added by jmcneill@.  The
previous MIPS "mach reset" DDB command was hard-coded for Octeon Cavium
CPUs only.

Fix mm_md_kernacc() for 64 bit kernels (including n32):
 - FAULT for any physical address less than start of cached XKPHY address.
 - Pass any remaining physical address less then end of RAM.
 - Pass any remaining physical address within the KEGS0 kernel address range.
Ignore all remaining addresses and fall back to uvm_kernacc() for checking
virtual address ranges.

Fixes pmap(1) (and probably other kmem grovellers).

KNF- wrap some long lines.

Finish CPU core support for Octeon Cavium CN70XX:
 - decode actual CPU name
 - per CPU core reset logic (partially adapted from OpenBSD)
 - handle Octeon 3 ioclock rate differences to other cores (from OpenBSD)

Remove mips32r2 error introduced in previous commit; there no MP support
at all for 32-bit MIPSNN kernels.

Revert thinko in previous.

Include room for the trailing NUL in the way name string.

Retire MIPS_CP0FL_USERLOCAL and MIPS_CP0FL_HWRENA and the flawed
logic that tried to deal with a MIPS processor that supports the ULR
CP0 register.  Probe correctly and save probed info somewhere we can
actually use it.  Avoids problems where libc expects ULR set to a
value but the CPU definition in the CPU table didn't have the right
combination of magic flags and thus never set ULR in the first place.

Correct a comment (or at least comment on what we do instead of half of
what we do).

Use the correct config3 field name (ULRI) for UserLocal register is
implemented bit.

Protect using mipsNN_foo() functions with an #ifdef MIPSNN.

Fixes non-MIPSNN kernel compiles pointed out by tsutsui@.

If we are on a SiByte or Cavium CPU with an FPU, report as "built-in FPU"
instead of saying it's an unknown FPU type.

XXX - add any other CPUs to this list?

Dynamically build the wayname strings instead of using a sparse array
populated with random N-ways entries.  Not only results in smaller code,
but also handles cases with 39-way caches without extra work.

Tidy up some ugly output from mips_page_physload() when a segment starts
and finishes in the same page.

The Cavium CN70xx PRID covers both the CN70xx and CN71xx CPU families.

Add SiByte SB-1 rev 0x11 cores and CN70xx CPUs to the CPU table.

Sync with HEAD

Add entry for MIPS 25Kf.

update from HEAD

Sync with HEAD

Pull up following revision(s) (requested by skrll in ticket #22):
	sys/arch/mips/mips/mips_machdep.c: revision 1.278
	sys/arch/mips/mips/pmap_machdep.c: revision 1.21
Always use XKPHYS for pool pages on _LP64; otherwise use KSEG0
--
Maintain the split of physical memory into the defined freelists, but
only force pool pages to VM_FREELIST_FIRST512M for non _LP64

Maintain the split of physical memory into the defined freelists, but
only force pool pages to VM_FREELIST_FIRST512M for non _LP64

Sync with HEAD

opt_multiprocessor.h police

Restore all work from the former pgoyette-localcount branch (which is
now abandoned doe to cvs merge botch).

The branch now builds, and installs via anita.  There are still some
problems (cgd is non-functional and all atf tests time-out) but they
will get resolved soon.

Sync with HEAD

Sync with HEAD.  (Note that most of these changes are simply $NetBSD$
tag issues.)

"Make NetBSD great again!"

Introduce uvm_hotplug(9) to the kernel.

Many thanks, in no particular order to:

TNF, for funding the project.

Chuck Silvers - for multiple API reviews and feedback.
Nick Hudson - for testing on multiple architectures and bugfix patches.
Everyone who helped with boot testing.

KeK (http://www.kek.org.in) for hosting the primary developers.

fix lp64 kvm access for many kernel addresses.
in mm_md_kernacc() allow an address if it matches MIPS_KSEG0_P().

now a static n64 kvm-using binary runs sanely on an n64 kernel.
(dynamic n64 has problems with non-trivial programs.)

ok matt@.

Sync with HEAD

Sync with HEAD

Fix typo.  N32 doesn't want UX on.

Sync with HEAD

xburst needs CPU_MIPS_D_CACHE_COHERENT

Adapt the machine/arch dependent code to the new {b,c}devsw reference
counting.

XXX Most of these will require testing by someone other than myself, as
I have a limited selection of hardware!

Trailing whitespace

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Add machdep.fpu_present sysctl node

Sync with HEAD

No more sysmapsize.

Add struct pmap_limits and pm_{min,max}addr from uvm/pmap/map.h and use it to
store avail_start, avail_end, virtual_start, and virtual_end.
Remove iospace and let emips just bump pmap_limits.virtual_start to get the
VA space it needs.
pmap_segtab.c is almost identical to uvm/pmap/pmap_segtab.c now.  It won't
be long until we switch to the uvm/pmap one.

Add entry for MIPS 1074K

sync _MTC0_V0_USERLOCAL with cpuregs.h
now CI20 boots again

Sync with HEAD

Rework cavium support in preparation for MULTIPROCESSOR support

Enable HWRENA for the CN50xx even though it doesn't support USERLOCAL.
Enable the MIPS64R2 locoresw.

Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.

fix _MTC0_V0_USERLOCAL for _LP64 as well
ok matt@

deal with Ingenic XBurst CPUs

Rebase to HEAD as of a few days ago.

Rebase.

apply __diagused.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

use cpu_{g,s}etmodel

fix unused variable warnings

G/C struct user *proc0paddr.

resync from head

add sysctl machdep.loongson-mmi to indicate wether Loongson Multimedia
Instructions are supported
mostly for pixman

Add initial support for XLP II (XLP2XX/XLP1XX).

Make MIPS use a multi-level page table for the kernel address space.
(just like the user address does).   XXX fix mips1

sync with head

normalise RCSID handling some.

sync to -current

sync to -current

sync to latest -current.

remove safepri declaration since it's defined in kern_synch.c

sync to -current.

Remove COMPAT_SA / KERN_SA.  Welcome to 6.99.3!
Approved by core@.

merge to -current.

mips_nfreelist is the one past the highest freelist used.

Fix various LP64 thinkos.

Add mm_md_direct_mapped_virt (inverse of mm_md_direct_mapped_phys).  Add a
third argument, vsize_t *, which, if not NULL, returns the amount of virtual
space left in that direct mapped segment.
Get rid most of the individual direct_mapped assert and use the above
routines instead.
Improve kernel core dump code.

Fix emulation to not panic when it encounters something it doesn't like.
(so running crashme won't crash the system).
Centralize the trapsignal processing so we can print out the trap info if
so desired.
Add a machdep.printfataltraps sysctl knob.

Add a posix_spawn syscall, as discussed on tech-kern.
Based on the summer of code project by Charles Zhang, heavily reworked
later by me - all bugs are likely mine.
Ok: core, releng.

Add mips_page_to_pggroup which return what pggroup a page belongs to.
Eradicate VM_FREELIST_MAX
When adding pages to the system, track what freelists get pages.

Fix mm_md_direct_mapped_phys

Add mm_md_direct_mapped_phys from current.

When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses.  There are exceptions.
bus_space_handles are now register_t instead of intptr_t.  This allows them
to contain XKPHYS addresses.  Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address.  This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs.  If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.

Use mips_ksegx_start (not mips3_ksegx_start).

Since MIPS supports multiple page sizes now, add pg_size to cpu_kcore_hdr_t
as well members to decode ksegx addresses.

Fix MIPS1 typo.

add entries for MIPS 1074K and RMI XLP3XX and XLP8XX.
for mipsNN, use TLB random register in case there are more than 64 TLB entries.
Add cpuname argument to cpu_identify.  Fix bug in mips_page_physaddr.
Print out number of ASIDs in cpu_identify.

If CID is RMI and we MIPS64R2, be sure to mips64_rmixl_*.

implement bdev_size(9) wrapper around d_psize() routine, so we can take
the device lock in relevant places.  avoid doing so while actually dumping.

tested i386 crash dumps still work, and that all touched files compile.

fixes PR#45705.

Fix $NetBSD$

Add Broadcom BCM3302 CPU to the table.

support BUS_SPACE_MAP_PREFETCH in order to allow mapping device memory and
DMA buffers with cacheing disabled but things like write combining, relaxed
ordering etc. allowed when the CPU supports it
so far enabled only on Loongson, should work on R1xk and probably newer CPUs

There are non-writable bits in MIPS_COP_0_TLB_HI between ASID and VPN, so
mips3_cp0_tlb_entry_hi_probe() returns a value with some 0 in the low 12 bits.
Thus the computed mips_vm_maxuser_address is wrong. Fix by oring PAGE_MASK to
return value of mips3_cp0_tlb_entry_hi_probe().

When using 16KB pages in a 64 bit kernel, the amount of address space our page
table can address can be larger than the amount of address space the CPU
implementation supports.  This change limits the amount address space to what
the CPU implementation provides.

Add support for the MIPS DSP ASE (as a second PCU).

Add support for a loongson2_subr.S.  This is needed since that chip needs
special handling to manually flush the ITLB on TLB updates.

Catchup with rmind-uvmplock merge.

Fix mm_md_direct_mapped_phys

Welcome to 5.99.53!  Merge rmind-uvmplock branch:

- Reorganize locking in UVM and provide extra serialisation for pmap(9).
  New lock order: [vmpage-owner-lock] -> pmap-lock.

- Simplify locking in some pmap(9) modules by removing P->V locking.

- Use lock object on vmobjlock (and thus vnode_t::v_interlock) to share
  the locks amongst UVM objects where necessary (tmpfs, layerfs, unionfs).

- Rewrite and optimise x86 TLB shootdown code, make it simpler and cleaner.
  Add TLBSTATS option for x86 to collect statistics about TLB shootdowns.

- Unify /dev/mem et al in MI code and provide required locking (removes
  kernel-lock on some ports).  Also, avoid cache-aliasing issues.

Thanks to Andrew Doran and Joerg Sonnenberger, as their initial patches
formed the core changes of this branch.

sync with head

Remove unused variable pcb.

Switch alpha to use PCU to manage the FPU.
Tested by mhitch and review by rmind.

Sync with HEAD.

sync with head

Add MIPS64_RMIXL (XLR/XLS) and MIPS64R2_RMIXL (XLP).  This allows the kernel
to treat this special which is needed for MP support. When accessing the TLB,
always lock the TLB before hand.  If in the miss handlers, the TLB is already
locked let trap deal with the exeception.

Since the RAS lock stubs are the default, don't bother assigning them just
make the default.

Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code.  (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.

sync with head

- add mips_watchpoint_init() to discover number of CPU watchpoints,
and call that from {mips32,mips32r2,mips64,mips64r2}_vector_init()

A little constification.
Add MIPS 1004K entry.

Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.

sync with head

Sync with HEAD

Refactor ps_strings access. Based on PK_32, write either the normal
version or the 32bit compat layout in execve1. Introduce a new function
copyin_psstrings for reading it back from userland and converting it to
the native layout. Refactor procfs to share most of the code with the
kern.proc_args sysctl handler.

This material is based upon work partially supported by
The NetBSD Foundation under a contract with Joerg Sonnenberger.

Change MIPS_CP0FL_CONFIG*
Add MIPS_CP0FL_HWRENA and USERLOCAL

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

Sync with HEAD

Add support for the Extensible MIPS ("eMIPS") platform.  The
NetBSD/emips port runs on Xilinx and Beecube FPGA systems and the
Giano system simulator.

eMIPS is a platform developed at Microsoft Research for researching
reconfigurable computing.  eMIPS allows dynamic loading and scheduling
of application-specific circuits for the purpose of accelerating
computations based on the current workload.

NetBSD eMIPS support for NetBSD 4.x was written at Microsoft Research
by Alessandro Forin and Neil Pittman.  Microsoft Corporation has
donated full copyright to The NetBSD Foundation.

Platform support for eMIPS is the first part of Microsoft's
contribution.  The second part includes the hardware accelerator
framework and will be proposed on tech-kern soon.

Whitespace nits.

Retire struct user, remove sys/user.h inclusions.  Note sys/user.h header
as obsolete.  Remove USER_TO_UAREA/UAREA_TO_USER macros.

Various #include fixes and review by matt@.

Make this build again by removing the const qualifier on the
local pcb0 variable in mips_init_lwp0_uarea().

- leave lwp0 trapframe zerod since it's never used.
- 64bit op SR[KX] bit is for !o32 cases.
- build struct sigframe_siginfo locally and then operate single copyout()
  to user stack as other ports do.

Janitorial work.
Move emulation prototypes here and get rid of StudLyCaps.
Remove kludgery for lwp/setfunc trampoline and just grab them of the damn
structure.
Make mips_locore_jumpvec contain the routines that don't get reassigned
and move wbflush to mips_locoresw since it does get overridden.

Bring locore_mips1.S into the new world order.  You can diff locore_mips1.S
against mipsX_subr.S and have reasonable output.  A lot of comments have
been changed to be common between the two.  The ordering of vectors/functions
have also changed to improve diff output.

Rework how fixups are processed.  Inside of generating a table, we just
scan kernel text for jumps to locations between (__stub_start, __stub_end]
and if found, we actually decode the instructions in the stub to find out
where the stub would eventually jump to and then patch the original jump
to jump directly to it bypassing the stub.  This is slightly slower than
the previous method but it's a simplier and new stubs get automagically
handled.

Use more VM_PHYSMEM_*() accessors.  No functional changes.

Machine dependent code is considered as part of UVM.  Include
internal API header.

Make sure UX is set if KX is set.  Use (intptr_t), not (int).

sync with head.

Add support for setting/clearing PK_32 on _LP64 kernels.  Make cpu_proc_fork
a real function and add it to vm_machdep.c and let it copy PK_32 on fork.
Properly clear/set PK_32 depending on ABI in setregs.  Lack of PX_32 use
tracked down by Cliff Neighbors.  [Ya! ps now works!]

sync with head

When use N32 and we are on a MIPS64 chip, enable 64-bit instructions via
PX so that we can still use the TLB miss exception instead of the XTLB miss
exception path.

Fix build.

add cputab[] entries for XLS models 208, 204, 108, 104

Sync with HEAD.

Always use struct vm_physseg *vm_physmem_ptrs[] in MD code.

add cputab[] entry for RMI CPU MIPS_XLR732C

A round of compile and other fixes to previous.

- Invent mm_md_getva() and mm_md_relva() routines, provided by MD and
  indicated with __HAVE_MM_MD_PREFER_VA.  It will be used to deal with
  cache aliasing issues and thus fix little MIPS, ARM and friends.

- Convert dev_mem_readwrite() to use unmanaged mappings.  Fix a missed
  offset addition in a case of direct map.  Sprinkle various comments in
  the memory device driver.

- Add missing direct map handling on hp700 and vax.  Make checks across
  m68k ports more consistent, reduce the diffs.  Fix kernacc check miss
  on news68k.  Minor off-by-one fix for alpha.  Add MEMC_PHYS_BASE for
  mmap() case check on acorn26.  Misc clean-up.

Remove lwp_uc_pool, replace it with kmem(9), plus add some consistency.
As discussed, a while ago, with ad@.

- add whitespace to make print format of regions in
mips_page_physload() more readable

- add a cputab[] entry for RMI XLR732 (other XLR models are TBD)

mips_vector_init now takes an argument to specify splsw.
NULL specifies use the default 'std_splsw'

Unify /dev/{mem,kmem,zero,null} implementations in MI code.  Based on patch
from Joerg Sonnenberger, proposed on tech-kern@, in February 2008.

Work and depression still in progress.

sync with head

Add secondary processor spinup support (cpu_trampoline is in locore_mips3.S).
Nuke lse_boot_secondary_processors (not needed).
Move cpu_info_store to cpu_subr.C

Split FPU support into separate file and keep internals private to that file.
Make it MPSAFE.  Change interface to be very similar to what's used on other
architectures.
Add l_md.md_fpcpu to mdlwp (needed for MPSAFE)
Move pridtab from <mips/cpu.h> to <mips/locore.h>
Add initial common IPI dispatcher.
Split cpu_* routines from mips_machdep.c into cpu_subr.c
Add cpu_startup_common which has the code replicated in half-dozen
plus machdep.c files.

#define __INTR_PRIVATE
Add calls to fixup the splcalls and fixup the call to mips_cpu_switch_resume
in cpu_switchto (which remove an indirect calls from a critical routine).

Add mipsXX_tlb_enter which modifies/sets a specific TLB entry with a new
mapping (useful for wired TLB entries).
Add mips_fixup_exceptions which will walk through the exception vectors
and allows the fixup of any cpu_info references to be changed to a more
MP-friendly incarnation.
Define a common fixup method to use a wired TLB entry at -PAGE_SIZE allowing
direct loads using a negative based from the zero register.
Change varible pmap_tlb_info t pmap_tlb0_info.

Add mipsXX_tlb_record_asids - records what ASIDs have valid TLB entries in
the TLB.
Move some mips3 specific routines from locore.S to locore_mips3.S

Make sure <mips/locore.h> is not included by MI code.
Add send_ipi and cpu_offline_md hooks to locoresw.
Add MP support to pmap (pvlist locking, tlb locking).
Add TLB shootdown support (see comment at the top of mips/pmap_tlb.c).
Add mipsXX_tlb_invalidate_globals routine

Add __HAVE_PREEMPTION support for NetBSD/mips.  Kill IPL_PREEMPT since it
isn't needed.

Completely redo how interrupts and SPL are handled in NetBSD/mips.
[XXX locore_mips1.S still needs to adapted.]

Nested interrupts now work.  Except for MIPS_SOFT_MASK and MIPS_SR_INT_IE,
how interrupts work is completely abstracted.  spl is handled through the
mips_splsw table.  Direct manipulation of the status register is no longer
done (except for MIPS_SR_INT_IE).  A new <mips/intr.h> contains the common
IPL/IST/spl* definitions for all ports.

Interrupt delivery is completely different.  Clock interrupts may interrupt
device interrupts.  ci_idepth is now handled by the caller of cpu_intr as
are softints (both can be optimized/simplified in the case of interrupts of
usermode code).  cpu_intr has new arguments and now get called at IPL_HIGH
with MIPS_SR_INT_IE set and its logic is:

void
cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
	int ipl;
	uint32_t pending;
	while (ppl < (ipl = splintr(&pending))) {
		splx(ipl);		/* enable interrupts */
		<handle pending interrupts>
		(void)splhigh();	/* disable interrupts */
	}
}

mipsX_subr.S has been reworked.  All user handlers (user_intr, systemcall,
user_gen_exception) now use common return to usermode code in lwp_trampoline.
ast() has changed to void ast(void) since the previous pc argument was never
used.

The playstation IPL_ICU_MASK support has been nuked.
MIPS_DYNAMIC_STATUS_MASK may soon be nuked soon.

A bunch of debugging code was left conditionalized by PARANOIA.  If this
code detects a bug, it will enter an infinite loop.  It is expected that
the kernel will be debugged in a simulator or with a hardware debugger so
that the state at that point can be analyzed.

When choosing a msgbuf for a LP32 kernel, make sure it's mappable via KSEG0

Allow port-specific code to init lwp0.l_addr early.  (pmax needs it so it
call badaddr).

Merge frame into trapframe.  While this costs a bit more stack space on
kernel exceptions, the resulting simplifications are worth it.  This is
a step to fast softints and kernel preemption.

trapframe now includes a struct reg instead of a separate array of registers.

rename pridtab{}::cpu_name to cpu_displayname.

should fix a build error reported by he@.

Mark RMIXL cpus as CPU_MIPS_I_DCACHE_COHERENT.
Print out whether the L1 cache is coherent or not.

Adjust things to the new world order.

Revamp things a bit.  Move of the globals mips uses into either cpu_info,
mips_options, or mips_cache_info.  Make MALT64 be able to boot MULTIPROCESSOR.
(some pmap MP work).

Rework the exception code.  All the exceptions (except for mips3_5900) are
now padded to 128 bytes each and placed in the right order so they can be
copied with one memcpy.  This also allows us to branch to unused space space
since the relative locations will remain the same.

When leaving the exception vectors, k1 will now always contain the address
of CURLWP for that CPU.  The rest of the exception code no longer needs (and
is not allowed to) to access CPUVAR(CURLWP).

kill outofworld and just let trap panic, if it can.  Allow for sb1_subr.S
or rmixl_subr.S in the future.  Fix TLB read/write code.

Get rid of most of the studly caps.
First to MULTIPROCESSOR support for pmap: move some pmap globals to cpu_info.
Define per-cpu ASID number spaces.
Remove some mips1/!mips1 difference in db_interface.c
Add mips32/64 knowledge to stacktrace.

Simplify mips_page_physload.

More fixes for the CFATTAL_DECL_NEW changes and rmixl cpucore/cpu changes.

- spec CIDFL's for RMI L2, cores, threads attributes
- add cputab[] entry for RMI XLS404LITE
- cpu_identify() now gets device_t arg; use it instead of static 'label'

On _LP64, allocate kernel memory from the first 4GB.  Otherwise first 512MB.
Until we get full bounce buffer support, this should with device that only
support <4GB addresses.

Fix a thinko (last -> start + size)

Use mips_page_physload and mips_init_lwp0_uarea.

Please segtab lookups into separate file.
Add mips_add_physload
Add mips_init_lwp0_uarea
cleanup lwp0/cpu_info_store initialization.

Make sure the pcb and initial frame area of lwp0 are zeroed since these will
be the basis for all future lwps.

Merge from matt-nb5-mips64
Merge mips-specific arch files.

Change u_long to vaddr_t/vsize_t in exec code where appropriate (mostly
involves setregs and vmcmds).  Should result in no code differences.

- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places.  Reduce sys/user.h inclusions.

Revert unrelated/unintended changes from previous commit.
Should fix MIPS builds (hi matt@).

Kill proc0paddr.  Use lwp0.l_addr instead.

Use lwp_getpcb() on mips, powerpc and sh3, clean from struct user usage.

- pridtab definition is removed to cpu.h
- pritab entries now initialize cpu_cp0flags and cpu_cidflags
except for RMI XLS entries, these are all 0 for now.
- pridtab entries for RMI XLS use those new fields and CPU_MIPS_HAVE_MxCR

Add XLS416.

add entries in cputab[] for RMI XLS408 and XLS408LITE

Set early clobber on status.  Make sure to preserve KX.

MIPS_XLS616 gets CPU_MIPS_NO_LLADDR

- add support for MIPS_XLS616.
- add RMI and others to cidnames[]
- use MIPS_PHYS_TO_XKPHYS_CACHED to make va for msgbuf and maddr #ifdef _LP64

Fix a few IPL32 kernel thinkos.

Add COMPAT_NETBSD32 support.

Fix PFN width calculation.

Add code to probe TLB for VA/PA/PG_MASK sizes
Increase waynames to include 8-way.

For LP64 kernels, only use KSEG0 for pmap_steal_memory.  Everything else uses
XKPHYS.  Use the new MIPS_PHYS_TO_XKPHYS_{,UN}CACHED macros.

To be consistent, always cast pointers to (intptr_t) even if the address is
in userspace.

Reviewed By:	matt

Set segbase to an invalid kernel address by default.

PRIxVADDR, PRIdVSIZE, PRIxVSIZE, or PRIxPADDR as appropriate.
Use __intXX_t or __uintXX_t as appropriate in <mips/types.h>

Change lazy fp load/save is done.  fpcurlwp is never NULL.
If no current lwp has the FP, then fpcurlwp is set to lwp0.
this allows many check for NULL and avoids a few null-derefs.
Since savefpregs clear COP1, loadfpregs can be called to reload
fpregs.  If it notices that situation, it just sets COP1 and returns
Save does not reset fpcurlwp, just clears COP1.  load does set fpcurlwp.

If MIPS3_SR_FR is set, all 32 64-bit FP registers are saved/restored via Xdc1.
If MIPS3_SR_FR is clear, only 32 32-bit FP register are saved/restore via Xwc1.
This preserves the existing ABI.

Make prototype locoresw const.
Don't cast l_md.md_regs anymore.
Make FP save/resume ABI agnostic.

Cast register_t to intptr_t before casting to (void *) because
sizeof(register_t) == 64 and sizeof(void *) == 32 in N32 ABI.

sync with head.

If using 16KB pages, don't enable special CCA for loongson2 cpus.

Initialize Page Mask register based on PAGE_SIZE, don't assume it's always
going to be 4KB.  (And this change, I can boot a GDIUM kernel with 16KB
pages as far as I could with 4KB).

Add disabled code to set K0 CCA if CCA_SPECIAL is being used.

Mark LOONGSON as uncached for the moment.

Make cidnames const

Add ICT Loongson2 identification.

sync with head

Pull up following revision(s) (requested by martin in ticket #799):
	sys/arch/mips/include/locore.h: revision 1.79
	sys/arch/mips/mips/locore_mips1.S: revision 1.65
	sys/arch/mips/mips/mipsX_subr.S: revision 1.28
	sys/arch/mips/mips/mips_machdep.c: revision 1.211
	sys/arch/mips/mips/vm_machdep.c: revision 1.123
Do not use the same trampoline for cpu_lwp_fork and cpu_setfunc - only
the former needs to call lwp_startup().

Pull up following revision(s) (requested by martin in ticket #799):
	sys/arch/mips/include/locore.h: revision 1.79
	sys/arch/mips/mips/locore_mips1.S: revision 1.65
	sys/arch/mips/mips/mipsX_subr.S: revision 1.28
	sys/arch/mips/mips/mips_machdep.c: revision 1.211
	sys/arch/mips/mips/vm_machdep.c: revision 1.123
Do not use the same trampoline for cpu_lwp_fork and cpu_setfunc - only
the former needs to call lwp_startup().

Do not use the same trampoline for cpu_lwp_fork and cpu_setfunc - only
the former needs to call lwp_startup().

Sync with HEAD.

Commit is split, to avoid a "too many arguments" protocol error.

sync with head.

Sync with HEAD.

ANSIfy functions with function-pointer arguments

Change about 4500 of the K&R function definitions to ANSI ones.
There are still about 1600 left, but they have ',' or /* ... */
in the actual variable definitions - which my awk script doesn't handle.
There are also many that need () -> (void).
(The script does handle misordered arguments.)

Sync with HEAD.

Pull up following revision(s) (requested by ad in ticket #346):
	sys/arch/alpha/alpha/machdep.c: revision 1.311
	sys/arch/amiga/amiga/machdep.c: revision 1.211
	sys/arch/atari/atari/machdep.c: revision 1.153
	sys/arch/hp700/hp700/machdep.c: revision 1.53
	sys/arch/i386/i386/dumpsys.c: revision 1.5
	sys/arch/mips/mips/mips_machdep.c: revision 1.206
	sys/arch/mvme68k/mvme68k/machdep.c: revision 1.132
	sys/arch/news68k/news68k/machdep.c: revision 1.75
	sys/arch/next68k/next68k/machdep.c: revision 1.88
	sys/arch/sparc/sparc/machdep.c: revision 1.285
	sys/arch/sparc64/sparc64/machdep.c: revision 1.230
	sys/arch/sun2/sun2/machdep.c: revision 1.56
	sys/arch/sun3/sun3/machdep.c: revision 1.188
	sys/arch/sun3/sun3x/machdep.c: revision 1.114
	sys/arch/x68k/x68k/machdep.c: revision 1.153
dumpsys: don't spew numbers into the log.

major() and minor() are now int32_t.

Sync with HEAD.

Sync with HEAD.

Make this compile.

Update haad-dm branch to haad-dm-base2.

dumpsys: don't spew numbers into the log.

Sync with HEAD.

Oops; redo previous.

p_smutex was merged into p_lock some time ago.

Merge wrstuden-revivesa into HEAD.

Sync with HEAD.

Sync with wrstuden-revivesa-base-2.

Sync with netbsd-4.

Pull up following revision(s) (requested by tsutsui in ticket #1181):
	sys/arch/mips/mips/mips_machdep.c: revision 1.202
Add CPU_MIPS_DOUBLE_COUNT to R10K family CPUs and
also remove (unused?) MIPS_NOT_SUPP flag from them.
Problem on R10k O2 is reported by martin@ on port-sgimips.

Add CPU_MIPS_DOUBLE_COUNT to R10K family CPUs and
also remove (unused?) MIPS_NOT_SUPP flag from them.

Problem on R10k O2 is reported by martin@ on port-sgimips.

Re-add cpu_upcall() and page fault code. i386 kernels now compile.
They don't boot, but that seems to be a consequence of current from the
day this branch was started.

Sync with HEAD.

sync with head.

sync with head.

Per discussion with ad at n dot o, revert signal mask handling
changes.

The l_sigstk changes are most likely totally un-needed as SA will
never use a signal stack - we send an upcall (or will as other
diffs are brought in).

The l_sigmask changes were too controvertial. In all honesty, I
think it's probably best to revert them. The main reason they were
there is the fact that in an SA process, we don't mask signals per
kernel thread, we mask them per user thread. In the kernel, we want
them all to get turned into upcalls. Thus the normal state of
l_sigmask in an SA process is for it to always be empty.

While we are in the process of delivering a signal, we want to
temporarily mask a signal (so we don't recursively exhaust our
upcall stacks). However signal delivery is rare (important, but
rare), and delivering back-to-back signals is even rarer. So rather
than cause every user of a signal mask to be prepared for this very
rare case, we will just add a second check later in the signal
delivery code. Said change is not in this diff.

This also un-compensates all of our compatability code for dealing
with SA. SA is a NetBSD-specific thing, so there's no need for
Irix, Linux, Solaris, SVR4 and so on to cope with it.

As previously, everything other than kern_sa.c compiles in i386
GENERIC as of this checkin. I will switch to ALL soon for compile
testing.

Initial checkin of re-adding SA. Everything except kern_sa.c
compiles in GENERIC for i386. This is still a work-in-progress, but
this checkin covers most of the mechanical work (changing signalling
to be able to accomidate SA's process-wide signalling and re-adding
includes of sys/sa.h and savar.h). Subsequent changes will be much
more interesting.

Also, kern_sa.c has received partial cleanup. There's still more
to do, though.

Remove clause 3 and 4 from TNF licenses

Merge proc::p_mutex and proc::p_smutex into a single adaptive mutex, since
we no longer need to guard against access from hardware interrupt handlers.

Additionally, if cloning a process with CLONE_SIGHAND, arrange to have the
child process share the parent's lock so that signal state may be kept in
sync. Partially addresses PR kern/37437.

sync with HEAD

sync with head.

Add entries for MIPS's 24K, 24KE, 34K and 74K cores.

From Alexander Voropay in mail to port-mips@.

sync with HEAD

Catch up to netbsd-4.0 release.

Sync with HEAD.

Sync with HEAD.

sync with head

Sync with HEAD.

Sync with HEAD.

Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

Sync with HEAD.

Sync with HEAD

Pull up following revision(s) (requested by simonb in ticket #1865):
	sys/arch/mips/include/cpuregs.h: revision 1.72
	sys/arch/mips/mips/mips_machdep.c: revision 1.195
Recognise the R2000A cpu as found in some pmaxen.
From Dennis Grevenstein on port-pmax@.
--

Fix cpu_need_resched().

sync with HEAD

sync with head.

Sync with HEAD.

Follow the merge of pmap.c on i386 and amd64 and move
pmap_init_tmp_pgtbl into arch/x86/x86/pmap.c. Modify the ACPI wakeup
code to restore CR4 before jumping back into kernel space as the large
page option might cover that.

Pull up following revision(s) (requested by simonb in ticket #936):
	sys/arch/mips/include/cpuregs.h: revision 1.72
	sys/arch/mips/mips/mips_machdep.c: revision 1.195

Recognise the R2000A cpu as found in some pmaxen.
From Dennis Grevenstein on port-pmax@.

Sync with head.

cpu_need_resched: RESCHED_IMMED refers to IPIs, so ignore it and
always do aston(l).

sync with head.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Sync with HEAD

Recognise the R2000A cpu as found in some pmaxen.

From Dennis Grevenstein on port-pmax@.

sync with head.

Sync with head.

Sync with head.

Update to HEAD.

merge yamt-idlelwp branch.  asked by core@.  some ports still needs work.

from doc/BRANCHES:

	idle lwp, and some changes depending on it.

	1. separate context switching and thread scheduling.
	   (cf. gmcgarry_ctxsw)
	2. implement idle lwp.
	3. clean up related MD/MI interfaces.
	4. make scheduler(s) modular.

... but temporarily continue to set them here too, until I figure out why
pmax clobbers them. Forcing things into the data segment doesn't help.

Set up curlwp/curcpu very early, before calling mach_init. Avoids a null
pointer deref on curcpu().

- Further adaptations to MIPS for the yamt-idlelwp branch.
- Make curlwp a register variable on MIPS.

Initial changes for MIPS. Not yet working under gxemul.

Sync with HEAD.

Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.

sync with head.

Merge newlock2 to head.

Sync with head.

Remove support for SA. Ok core@.

Remove duplicate #includes, patch contributed in private mail
by Slava Semushin <slava.semushin@gmail.com>.

To verify that no nasty side effects of duplicate includes (or their
removal) have an effect here, I've compiled an i386/ALL kernel with
and without the patch, and the only difference in the resulting .o
files was in shifted line numbers in some assert() calls.
The comparison of the .o files was based on the output of "objdump -D".

Thanks to martin@ for the input on testing.

Checkpoint work in progress.

sync with head.

Checkpoint work in progress.

sync with head.

Sync with head.

Constify, since the new gcc propagates constness to struct members.

sync with head

fix errors in the previous changes.

in cpu_dumpconf(), don't panic() if we can't bdevsw_lookup() the
dumpdev.  this occurs when we try to set the dumpdev to a device
with no driver loaded.  this fixes PR#34872.

in sys_swapctl, if bdevsw_lookup() fails, set dumpdev = NODEV
before calling cpu_dumpconf().  (this also fixes PR#34872.)

XXX: cpu_dumpconf() should probably be changed to take a dumpdev
XXX: and return an error in such cases, but that is a much more
XXX: intrusive change.

XXX2: this is only run-tested on sparc64 and compile tested on a
XXX2: couple of platforms.

sync with head

sync with head.

Use vaddr_t for virtual addresses.  Don't cast pointers with int or
unsigned, use intptr_t or uintptr_t as appropriate.

sync with head.

Sync with head.

sync with head - hopefully this will work

sync with head.

Merge 2006-03-28 NetBSD-current into the "peter-altq" branch.

Reorder a few entries in the CPU table.

Added support for MIPS architecture revision 2.
Added definitions for various rev 2 CP0 configuration register bits.
Added support for MIPS 4KEc Rev 2 (found in Atheros AR2316, for example).

Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

Add basic support for Alchemy Au1550 processor (CPU and devices).
Patch contributed by Garrett D'Amore in PR port-evbmips/32030.

merge ktrace-lwp.

Sync with HEAD. Here we go again...

Make MIPS3_PG_SHIFT a variable and initialize it accordingly
in mips_vector_init() if options MIPS3_4100 is specified
so that kernels which have options MIPS3_4100 also work
on other MIPS3 CPUs.

XXX: now should we rename options MIPS3_4100 to options ENABLE_MIPS_R4100,
XXX: or just make MIPS3_PG_SHIFT always a variable?

Check MIPS_PRID_IMPL(cpu_id) for MIPS3_4100 CPUs at runtime to
initialize the MIPS_COP_0_TLB_PG_MASK register with their specific value.

Pull up following revision(s) (requested by tsutsui in ticket #5829):
	sys/arch/mips/mips/mips_machdep.c: revision 1.179
Initilize CP0 pagemask register properly.
Fixes PR 30590 and some other mips port.

Pull up following revision(s) (requested by tsutsui in ticket #758):
	sys/arch/mips/mips/mips_machdep.c: revision 1.179
Initilize CP0 pagemask register properly.
Fixes PR 30590 and some other mips port.

Initilize CP0 pagemask register properly.
Fixes PR 30590 and some other mips port.

cast-qual fallout

Sync with HEAD.

Use "NULL" instead of "(something-or-other *)0".

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

Pull up revisoin 1.176 (requested by simonb in ticket #589):
  Changes fixing PR#25942:
   o In cpu_{set,get}context(), copy fht FP registers themselves
     and the FP CSR separately, and from a correctly sized
     __fpregset_t.  The FP CSR is copied separately to avoid
     endianness or alignment issues.

In cpu_{set,get}context(), copy the FP registers themselves and the FP
CSR separately (and now from the correctly sized __fpregset_t).  The
FP CSR is copied separately to avoid endianness/alignment issues.

Part of fix for PR port-mips/25942.  Thanks to Christos Zoulas and
Klaus Klein for help with debugging this.

Tango on sysctl_createv() and flags.  The flags have all been renamed,
and sysctl_createv() now uses more arguments.

proper name for SB-1 is ... SB-1 (not SB1).

Uppercase CPU, plural is CPUs.

Only compile in sysctl_machdep_booted_kernel() if __HAVE_BOOTINFO_H
is defined.

Dynamic sysctl.

Gone are the old kern_sysctl(), cpu_sysctl(), hw_sysctl(),
vfs_sysctl(), etc, routines, along with sysctl_int() et al.  Now all
nodes are registered with the tree, and nodes can be added (or
removed) easily, and I/O to and from the tree is handled generically.

Since the nodes are registered with the tree, the mapping from name to
number (and back again) can now be discovered, instead of having to be
hard coded.  Adding new nodes to the tree is likewise much simpler --
the new infrastructure handles almost all the work for simple types,
and just about anything else can be done with a small helper function.

All existing nodes are where they were before (numerically speaking),
so all existing consumers of sysctl information should notice no
difference.

PS - I'm sorry, but there's a distinct lack of documentation at the
moment.  I'm working on sysctl(3/8/9) right now, and I promise to
watch out for buses.

netbsd.org -> NetBSD.org

All "netbsd.org" is now gone from src/sys/arch.

Hide the register number constants behind an _R_ prefix, and also
rename FPBASE to _FPBASE, so that we avoid polluting the user's
name space when e.g. <sys/ptrace.h> is included.  Previously, the
PC symbol in mips/regnum.h would conflict with the declaration of
the external variable by the same name in termcap.h, as discovered
by the ``okheaders'' regression test.

set the onstack flag if requested.

Update comment to follow the previous R4000 ID addtion.

Add another R4000 CPU revision ID. From Christopher SEKIYA.

LWP-ify to get algor/P4032 working.

Back out the lwp/ktrace changes. They contained a lot of colateral damage,
and need to be examined and discussed more.

Fix more needless 'struct proc *' to 'struct lwp *' fallout.

Consistency nit- always use "#if defined(foo)" for checking MIPSn.

Don't use "return;" as last statement of a void function.

Don't use magic numbers in asm code (use MIPS_COP_0_STATUS instead
of "12").

Make cpu_getmcontext() run the PC through ras_lookup() so that kernel
getcontext() plus userlevel setcontext() (as used in libpthread) respects
the atomicity of RAS regions.

Use PAGE_SIZE rather than NBPG.