CVS log for src/sys/arch/mips/mips/locore_octeon.S

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Keyword substitution: kv
Default branch: MAIN

mips: Fix cpuids synchronization at boot.

Change cpus_booted back to a simple variable instead of a kcpuset.
octeon_cpu_spinup() was trying to set CPU status immediately on kernel
startup _well_ before the kcpuset was initialised.

Adjust for new CP0 reg names, comment out most of the Cavium CP0
specific functions that are unused.

Remove check/limit for only 2 cores.
Use MIPS_EBASE_CPUNUM instead of magic numbers.

update from HEAD

Sync with HEAD

Sync with HEAD

file locore_octeon.S was added on branch tls-maxphys on 2017-12-03 11:36:28 +0000

Sprinle RCSID

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Use the correct register (s0) for the cpu number to copy to the second
argument (a1)

Sync with HEAD

Transition from __cpuset_t to kcpuset_t *.  This brings the local pmap one
step closer to uvm/pmap, its eventual replacement.  Tested on ERLITE MP kernel.

Fix octeon_reset_vector to work in non-MP kernels.

Define COP0 register that use select value in <mips/cpuregs.h>
Use those new definitions

Add octeon_reset_vector which handles soft resets and nmi that comes through
the boot vector @ 0xbfc00000.

Sync with HEAD

file locore_octeon.S was added on branch nick-nhusb on 2015-06-06 14:40:02 +0000

Fix octeon spinup code to branch to right instruction and to jump to the
right routine.

Rework cavium support in preparation for MULTIPROCESSOR support

Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.