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Diff for /src/sys/arch/mips/mips/cache_tx39.c between version 1.7 and 1.8

version 1.7, 2011/02/20 07:45:47 version 1.8, 2016/07/11 16:15:36
Line 67  tx3900_icache_sync_all_16(void)
Line 67  tx3900_icache_sync_all_16(void)
 }  }
   
 void  void
 tx3900_icache_sync_range_16(vaddr_t va, vsize_t size)  tx3900_icache_sync_range_16(register_t va, vsize_t size)
 {  {
         vaddr_t eva = round_line(va + size);          vaddr_t eva = round_line(va + size);
   
Line 117  tx3900_pdcache_wbinv_all_4(void)
Line 117  tx3900_pdcache_wbinv_all_4(void)
 }  }
   
 void  void
 tx3900_pdcache_inv_range_4(vaddr_t va, vsize_t size)  tx3900_pdcache_inv_range_4(register_t va, vsize_t size)
 {  {
         vaddr_t eva = round_line(va + size);          vaddr_t eva = round_line(va + size);
   
Line 136  tx3900_pdcache_inv_range_4(vaddr_t va, v
Line 136  tx3900_pdcache_inv_range_4(vaddr_t va, v
 }  }
   
 void  void
 tx3900_pdcache_wb_range_4(vaddr_t va, vsize_t size)  tx3900_pdcache_wb_range_4(register_t va, vsize_t size)
 {  {
   
         /* Cache is write-through. */          /* Cache is write-through. */
Line 161  tx3920_icache_sync_all_16wb(void)
Line 161  tx3920_icache_sync_all_16wb(void)
 }  }
   
 void  void
 tx3920_icache_sync_range_16wt(vaddr_t va, vsize_t size)  tx3920_icache_sync_range_16wt(register_t va, vsize_t size)
 {  {
         vaddr_t eva = round_line(va + size);          vaddr_t eva = round_line(va + size);
   
Line 171  tx3920_icache_sync_range_16wt(vaddr_t va
Line 171  tx3920_icache_sync_range_16wt(vaddr_t va
 }  }
   
 void  void
 tx3920_icache_sync_range_16wb(vaddr_t va, vsize_t size)  tx3920_icache_sync_range_16wb(register_t va, vsize_t size)
 {  {
         vaddr_t eva = round_line(va + size);          vaddr_t eva = round_line(va + size);
   
Line 221  tx3920_pdcache_wbinv_all_16wb(void)
Line 221  tx3920_pdcache_wbinv_all_16wb(void)
 }  }
   
 void  void
 tx3920_pdcache_wbinv_range_16wb(vaddr_t va, vsize_t size)  tx3920_pdcache_wbinv_range_16wb(register_t va, vsize_t size)
 {  {
         vaddr_t eva = round_line(va + size);          vaddr_t eva = round_line(va + size);
   
Line 240  tx3920_pdcache_wbinv_range_16wb(vaddr_t 
Line 240  tx3920_pdcache_wbinv_range_16wb(vaddr_t 
 }  }
   
 void  void
 tx3920_pdcache_inv_range_16(vaddr_t va, vsize_t size)  tx3920_pdcache_inv_range_16(register_t va, vsize_t size)
 {  {
         vaddr_t eva = round_line(va + size);          vaddr_t eva = round_line(va + size);
   
Line 259  tx3920_pdcache_inv_range_16(vaddr_t va, 
Line 259  tx3920_pdcache_inv_range_16(vaddr_t va, 
 }  }
   
 void  void
 tx3920_pdcache_wb_range_16wt(vaddr_t va, vsize_t size)  tx3920_pdcache_wb_range_16wt(register_t va, vsize_t size)
 {  {
   
         /* Cache is write-through. */          /* Cache is write-through. */
 }  }
   
 void  void
 tx3920_pdcache_wb_range_16wb(vaddr_t va, vsize_t size)  tx3920_pdcache_wb_range_16wb(register_t va, vsize_t size)
 {  {
         vaddr_t eva = round_line(va + size);          vaddr_t eva = round_line(va + size);
   

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Removed from v.1.7  
changed lines
  Added in v.1.8

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