version 1.7, 2011/02/20 07:45:47 |
version 1.8, 2016/07/11 16:15:36 |
Line 67 tx3900_icache_sync_all_16(void) |
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Line 67 tx3900_icache_sync_all_16(void) |
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} |
} |
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void |
void |
tx3900_icache_sync_range_16(vaddr_t va, vsize_t size) |
tx3900_icache_sync_range_16(register_t va, vsize_t size) |
{ |
{ |
vaddr_t eva = round_line(va + size); |
vaddr_t eva = round_line(va + size); |
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Line 117 tx3900_pdcache_wbinv_all_4(void) |
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Line 117 tx3900_pdcache_wbinv_all_4(void) |
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} |
} |
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void |
void |
tx3900_pdcache_inv_range_4(vaddr_t va, vsize_t size) |
tx3900_pdcache_inv_range_4(register_t va, vsize_t size) |
{ |
{ |
vaddr_t eva = round_line(va + size); |
vaddr_t eva = round_line(va + size); |
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Line 136 tx3900_pdcache_inv_range_4(vaddr_t va, v |
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Line 136 tx3900_pdcache_inv_range_4(vaddr_t va, v |
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} |
} |
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void |
void |
tx3900_pdcache_wb_range_4(vaddr_t va, vsize_t size) |
tx3900_pdcache_wb_range_4(register_t va, vsize_t size) |
{ |
{ |
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/* Cache is write-through. */ |
/* Cache is write-through. */ |
Line 161 tx3920_icache_sync_all_16wb(void) |
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Line 161 tx3920_icache_sync_all_16wb(void) |
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} |
} |
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void |
void |
tx3920_icache_sync_range_16wt(vaddr_t va, vsize_t size) |
tx3920_icache_sync_range_16wt(register_t va, vsize_t size) |
{ |
{ |
vaddr_t eva = round_line(va + size); |
vaddr_t eva = round_line(va + size); |
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Line 171 tx3920_icache_sync_range_16wt(vaddr_t va |
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Line 171 tx3920_icache_sync_range_16wt(vaddr_t va |
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} |
} |
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void |
void |
tx3920_icache_sync_range_16wb(vaddr_t va, vsize_t size) |
tx3920_icache_sync_range_16wb(register_t va, vsize_t size) |
{ |
{ |
vaddr_t eva = round_line(va + size); |
vaddr_t eva = round_line(va + size); |
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Line 221 tx3920_pdcache_wbinv_all_16wb(void) |
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Line 221 tx3920_pdcache_wbinv_all_16wb(void) |
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} |
} |
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void |
void |
tx3920_pdcache_wbinv_range_16wb(vaddr_t va, vsize_t size) |
tx3920_pdcache_wbinv_range_16wb(register_t va, vsize_t size) |
{ |
{ |
vaddr_t eva = round_line(va + size); |
vaddr_t eva = round_line(va + size); |
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Line 240 tx3920_pdcache_wbinv_range_16wb(vaddr_t |
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Line 240 tx3920_pdcache_wbinv_range_16wb(vaddr_t |
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} |
} |
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void |
void |
tx3920_pdcache_inv_range_16(vaddr_t va, vsize_t size) |
tx3920_pdcache_inv_range_16(register_t va, vsize_t size) |
{ |
{ |
vaddr_t eva = round_line(va + size); |
vaddr_t eva = round_line(va + size); |
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Line 259 tx3920_pdcache_inv_range_16(vaddr_t va, |
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Line 259 tx3920_pdcache_inv_range_16(vaddr_t va, |
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} |
} |
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void |
void |
tx3920_pdcache_wb_range_16wt(vaddr_t va, vsize_t size) |
tx3920_pdcache_wb_range_16wt(register_t va, vsize_t size) |
{ |
{ |
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/* Cache is write-through. */ |
/* Cache is write-through. */ |
} |
} |
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void |
void |
tx3920_pdcache_wb_range_16wb(vaddr_t va, vsize_t size) |
tx3920_pdcache_wb_range_16wb(register_t va, vsize_t size) |
{ |
{ |
vaddr_t eva = round_line(va + size); |
vaddr_t eva = round_line(va + size); |
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