Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

===================================================================
RCS file: /ftp/cvs/cvsroot/src/sys/arch/mips/mips/cache_r5k.c,v
rcsdiff: /ftp/cvs/cvsroot/src/sys/arch/mips/mips/cache_r5k.c,v: warning: Unknown phrases like `commitid ...;' are present.
retrieving revision 1.16
retrieving revision 1.16.2.1
diff -u -p -r1.16 -r1.16.2.1
--- src/sys/arch/mips/mips/cache_r5k.c	2016/07/11 16:15:36	1.16
+++ src/sys/arch/mips/mips/cache_r5k.c	2016/11/04 14:49:02	1.16.2.1
@@ -1,4 +1,4 @@
-/*	$NetBSD: cache_r5k.c,v 1.16 2016/07/11 16:15:36 matt Exp $	*/
+/*	$NetBSD: cache_r5k.c,v 1.16.2.1 2016/11/04 14:49:02 pgoyette Exp $	*/
 
 /*
  * Copyright 2001 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache_r5k.c,v 1.16 2016/07/11 16:15:36 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache_r5k.c,v 1.16.2.1 2016/11/04 14:49:02 pgoyette Exp $");
 
 #include <sys/param.h>
 
@@ -259,7 +259,7 @@ r4600v2_pdcache_wbinv_range_32(register_
 	(void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0);
 	for (; va < eva; va += 32) {
 		cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
-		
+
 	}
 
 	mips_cp0_status_write(ostatus);
@@ -275,7 +275,7 @@ vr4131v1_pdcache_wbinv_range_16(register
 	for (; (eva - va) >= (32 * 16); va += (32 * 16)) {
 		cache_r4k_op_32lines_16(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
 		cache_r4k_op_32lines_16(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
-		
+
 	}
 
 	for (; va < eva; va += 16) {
@@ -287,7 +287,7 @@ vr4131v1_pdcache_wbinv_range_16(register
 void
 r4600v1_pdcache_inv_range_32(register_t va, vsize_t size)
 {
-	const vaddr_t eva = round_line32(va + size);
+	const register_t eva = round_line32(va + size);
 
 	/*
 	 * This is pathetically slow, but the chip bug is pretty
@@ -304,7 +304,7 @@ r4600v1_pdcache_inv_range_32(register_t 
 	for (; va < eva; va += 32) {
 		__asm volatile("nop; nop; nop; nop;");
 		cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
-		
+
 	}
 
 	mips_cp0_status_write(ostatus);
@@ -313,7 +313,7 @@ r4600v1_pdcache_inv_range_32(register_t 
 void
 r4600v2_pdcache_inv_range_32(register_t va, vsize_t size)
 {
-	const vaddr_t eva = round_line32(va + size);
+	const register_t eva = round_line32(va + size);
 
 	va = trunc_line32(va);
 
@@ -328,13 +328,13 @@ r4600v2_pdcache_inv_range_32(register_t 
 	for (; (eva - va) >= (32 * 32); va += (32 * 32)) {
 		(void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0);
 		cache_r4k_op_32lines_32(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
-		
+
 	}
 
 	(void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0);
 	for (; va < eva; va += 32) {
 		cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
-		
+
 	}
 
 	mips_cp0_status_write(ostatus);
@@ -360,7 +360,7 @@ r4600v1_pdcache_wb_range_32(register_t v
 	for (; va < eva; va += 32) {
 		__asm volatile("nop; nop; nop; nop;");
 		cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
-		
+
 	}
 
 	mips_cp0_status_write(ostatus);
@@ -384,7 +384,7 @@ r4600v2_pdcache_wb_range_32(register_t v
 	for (; (eva - va) >= (32 * 32); va += (32 * 32)) {
 		(void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0);
 		cache_r4k_op_32lines_32(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
-		
+
 	}
 
 	(void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0);
@@ -428,11 +428,11 @@ r5k_sdcache_wbinv_range_index(vaddr_t va
 	 * address out of them.
 	 */
 	va = MIPS_PHYS_TO_KSEG0(va & (mips_cache_info.mci_sdcache_size - 1));
-	r5k_sdcache_wbinv_range(va, size);
+	r5k_sdcache_wbinv_range((intptr_t)va, size);
 }
 
-#define	mips_r5k_round_page(x)	round_line(x, 128 * 32)
-#define	mips_r5k_trunc_page(x)	trunc_line(x, 128 * 32)
+#define	mips_r5k_round_page(x)	round_line(x, PAGE_SIZE)
+#define	mips_r5k_trunc_page(x)	trunc_line(x, PAGE_SIZE)
 
 void
 r5k_sdcache_wbinv_range(register_t va, vsize_t size)
@@ -442,14 +442,8 @@ r5k_sdcache_wbinv_range(register_t va, v
 
 	va = mips_r5k_trunc_page(va);
 
-	__asm volatile(
-		".set noreorder		\n\t"
-		".set noat		\n\t"
-		"mfc0 %0, $12		\n\t"
-		"mtc0 $0, $12		\n\t"
-		".set reorder		\n\t"
-		".set at"
-		: "=r"(ostatus));
+	ostatus = mips_cp0_status_read();
+	mips_cp0_status_write(ostatus & ~MIPS_SR_INT_IE);
 
 	__asm volatile("mfc0 %0, $28" : "=r"(taglo));
 	__asm volatile("mtc0 $0, $28");
@@ -458,6 +452,6 @@ r5k_sdcache_wbinv_range(register_t va, v
 		cache_op_r4k_line(va, CACHEOP_R4K_HIT_WB_INV|CACHE_R4K_SD);
 	}
 
-	__asm volatile("mtc0 %0, $12; nop" :: "r"(ostatus));
+	mips_cp0_status_write(ostatus);
 	__asm volatile("mtc0 %0, $28; nop" :: "r"(taglo));
 }