CVS log for src/sys/arch/mips/mips/cache_r5k.c

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Pull up following revision(s) (requested by tsutsui in ticket #965):

	sys/arch/mips/include/cache_r5k.h: revision 1.5
	sys/arch/mips/mips/cache_r5k_subr.S: revision 1.4
	sys/arch/mips/mips/cache_r5k.c: revision 1.21

Use proper "page" alignments for R5k Page Invalidate(S) op.  PR/55139

According to NEC "User's Manual VR5000, VR1000 64-BIT MICROPROCESSOR
INSTRUCTION" (U12754EJ1V0UMJ1), R5000 Page Invalidate (S) op does
"a page invalidate by doing a burst of 128 line invalidates to
the secondary cache at the page specified by the effective address
generated by the CACHE instruction, which must be page aligned."

This description looks a bit confusing, but "page" used here
implies fixed 32 byte cacheline * 128 lines == 4096 bytes,
not our variable "PAGE_SIZE" used in VM paging ops.  Note
the current default PAGE_SIZE for MIPS3 has been changed to 8192.

While here, also define and use proper macro for the "page" and CACHEOP
arg for the R5k Page_Invalidate_S op, as the manual also describes
the cache op field 10111 as "Page Invalidate" for the secondary cache.

No visible regression on Cobalt Qube 2700 (Rm5230) through
whole installation using netbsd-9 based Cobalt RestoreCD/USB.

Use proper "page" alignments for R5k Page Invalidate(S) op.  PR/55139

According to NEC "User's Manual VR5000, VR1000 64-BIT MICROPROCESSOR
INSTRUCTION" (U12754EJ1V0UMJ1), R5000 Page Invalidate (S) op does
"a page invalidate by doing a burst of 128 line invalidates to
the secondary cache at the page specified by the effective address
generated by the CACHE instruction, which must be page aligned."

This description looks a bit confusing, but "page" used here
implies fixed 32 byte cacheline * 128 lines == 4096 bytes,
not our variable "PAGE_SIZE" used in VM paging ops.  Note
the current default PAGE_SIZE for MIPS3 has been changed to 8192.

While here, also define and use proper macro for the "page" and CACHEOP
arg for the R5k Page_Invalidate_S op, as the manual also describes
the cache op field 10111 as "Page Invalidate" for the secondary cache.

No visible regression on Cobalt Qube 2700 (Rm5230) through
whole installation using netbsd-9 based Cobalt RestoreCD/USB.

update from HEAD

Sync with HEAD

Sync with HEAD - tag prg-localcount2-base1

Typo in comment

Sync with HEAD

Sync with HEAD

Trailing whitespace

vaddr_t -> register_t in range cache ops

- don't clear KX when disabling interrupts
- sign extend addresses as needed
- use PAGE_SIZE instead of blindly assuming 4KB
now n32 kernels work again on my R5k SGIs
thanks to skrll@ for helping me with this

Sync with HEAD

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses.  There are exceptions.
bus_space_handles are now register_t instead of intptr_t.  This allows them
to contain XKPHYS addresses.  Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address.  This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs.  If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.

Sync with HEAD.

sync with head

whitespace cleanup

Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code.  (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.

sync with head

Sync with HEAD

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

Sync with HEAD.

Don't redefine famous round_page() / trunc_page() locally.

Adjust things to the new world order.

sync with head.

Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

Sync with HEAD.

Implement r5k indexed writeback-invalidate, and fix usage of Page_Invalidate_S.

Originally written by rafal@ back in April 2003.  Field-tested by many
people since.

(I am not committing the pmap hack at this time; although pmap changes are
necessary to fully address the r5k panic/coma problems, the implementation
needs further thought)

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

__KERNEL_RCSID()

Add support for R5k secondary caches, from code Chris Sekiya sent me a long
time ago, with small tweaks by me.  Since the R5k doesn't do VCE, the pmap
still needs to be whacked for R5kSC CPUs to work correctly, but this is a
start.

Make whitespace in multi-way loops line up a bit nicer.

Catch up to -current

fix errors in calculating the ending VA to use in r4k_icache_sync_range_16
and r5k_icache_sync_range_32.  (reviewed by thorpej.)

Catch up to -current.

Sync w/ -current.

Pull-up cache ops from -current

add VR4131 cache-op bug workaround code.
we can't use Hit_WriteBack_Invalidate.

More catchup.

Sync kqueue branch with -current.

file cache_r5k.c was added on branch kqueue on 2002-01-10 19:46:05 +0000

fix pasto.
s/trunc_line/trunc_line16/

Added Vr4131 support.

file cache_r5k.c was added on branch nathanw_sa on 2002-01-11 23:38:39 +0000

Merge the thorpej-mips-cache branch onto the trunk.  This is an
overhaul of how caches are handled for NetBSD's MIPS ports.

Be more conservative with interrupt blocking in the R4600 ops
that require chip bug work-arounds.

XXX Should probably just consider using Index ops where feasible on
the buggy R4600s.

icache_sync_range_index: wbinv the dcache before reducing the virtual
address to an index (in the event that the significant index bits for
the dcache are different than those for the icache).

* fix size calculation.
* add missing cache operation for 2nd way.
* fix pasto (s/CACHEOP_R4K_HIT_WB_INV/CACHEOP_R4K_INDEX_WB_INV/).

New style cache operations for R4600/R5000-style caches.

file cache_r5k.c was initially added on branch thorpej-mips-cache.