Annotation of src/sys/arch/mips/mips/cache.c, Revision 1.8
1.8 ! shin 1: /* $NetBSD: cache.c,v 1.7 2001/12/28 04:06:07 shin Exp $ */
1.2 thorpej 2:
3: /*
4: * Copyright 2001 Wasabi Systems, Inc.
5: * All rights reserved.
6: *
7: * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8: *
9: * Redistribution and use in source and binary forms, with or without
10: * modification, are permitted provided that the following conditions
11: * are met:
12: * 1. Redistributions of source code must retain the above copyright
13: * notice, this list of conditions and the following disclaimer.
14: * 2. Redistributions in binary form must reproduce the above copyright
15: * notice, this list of conditions and the following disclaimer in the
16: * documentation and/or other materials provided with the distribution.
17: * 3. All advertising materials mentioning features or use of this software
18: * must display the following acknowledgement:
19: * This product includes software developed for the NetBSD Project by
20: * Wasabi Systems, Inc.
21: * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22: * or promote products derived from this software without specific prior
23: * written permission.
24: *
25: * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27: * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28: * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29: * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30: * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31: * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32: * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33: * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34: * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35: * POSSIBILITY OF SUCH DAMAGE.
36: */
37:
38: #include "opt_cputype.h"
39:
40: #include <sys/param.h>
41:
42: #include <uvm/uvm_extern.h>
43:
44: #include <mips/cache.h>
45: #include <mips/locore.h>
46:
47: #ifdef MIPS1
48: #include <mips/cache_r3k.h>
49: #endif
50:
51: #ifdef MIPS3
52: #include <mips/cache_r4k.h> /* includes r5k */
53: #endif
54:
55: /* PRIMARY CACHE VARIABLES */
56: int mips_picache_size;
57: int mips_picache_line_size;
58: int mips_picache_ways;
59: int mips_picache_way_size;
60: int mips_picache_way_mask;
61:
62: int mips_pdcache_size; /* and unified */
63: int mips_pdcache_line_size;
64: int mips_pdcache_ways;
65: int mips_pdcache_way_size;
66: int mips_pdcache_way_mask;
67: int mips_pdcache_write_through;
68:
69: int mips_pcache_unified;
70:
71: /* SECONDARY CACHE VARIABLES */
72: int mips_sicache_size;
73: int mips_sicache_line_size;
74: int mips_sicache_ways;
75: int mips_sicache_way_size;
76: int mips_sicache_way_mask;
77:
78: int mips_sdcache_size; /* and unified */
79: int mips_sdcache_line_size;
80: int mips_sdcache_ways;
81: int mips_sdcache_way_size;
82: int mips_sdcache_way_mask;
83: int mips_sdcache_write_through;
84:
85: int mips_scache_unified;
86:
87: /* TERTIARY CACHE VARIABLES */
88: int mips_tcache_size; /* always unified */
89: int mips_tcache_line_size;
90: int mips_tcache_ways;
91: int mips_tcache_way_size;
92: int mips_tcache_way_mask;
93: int mips_tcache_write_through;
94:
1.4 thorpej 95: /*
96: * These two variables inform the rest of the kernel about the
97: * size of the largest D-cache line present in the system. The
98: * mask can be used to determine if a region of memory is cache
99: * line size aligned.
100: *
101: * Whenever any code updates a data cache line size, it should
102: * call mips_dcache_compute_align() to recompute these values.
103: */
104: int mips_dcache_align;
105: int mips_dcache_align_mask;
106:
1.2 thorpej 107: int mips_cache_alias_mask; /* for virtually-indexed caches */
108: int mips_cache_prefer_mask;
109:
110: struct mips_cache_ops mips_cache_ops;
111:
112: #ifdef MIPS1
113: #ifdef ENABLE_MIPS_TX3900
114: #include <mips/cache_tx39.h>
115: void tx3900_get_cache_config(void);
116: void tx3920_get_cache_config(void);
117: #endif /* ENABLE_MIPS_TX3900 */
118: #endif /* MIPS1 */
119:
120: #ifdef MIPS3
121: #ifdef MIPS3_5900
122: #include <mips/cache_r5900.h>
123: #endif /* MIPS3_5900 */
124: #endif /* MIPS3 */
125:
126: #ifdef MIPS3
127: void mips3_get_cache_config(int);
128: #endif /* MIPS3 */
129:
130: /*
1.4 thorpej 131: * mips_dcache_compute_align:
132: *
133: * Compute the D-cache alignment values.
134: */
135: void
136: mips_dcache_compute_align(void)
137: {
138: int align;
139:
140: align = mips_pdcache_line_size;
141:
142: if (mips_sdcache_line_size > align)
143: align = mips_sdcache_line_size;
144:
145: if (mips_tcache_line_size > align)
146: align = mips_tcache_line_size;
147:
148: mips_dcache_align = align;
149: mips_dcache_align_mask = align - 1;
150: }
151:
152: /*
1.2 thorpej 153: * mips_config_cache:
154: *
155: * Configure the cache for the system.
156: *
157: * XXX DOES NOT HANDLE SPLIT SECONDARY CACHES.
158: */
159: void
160: mips_config_cache(void)
161: {
162: #ifdef MIPS3
163: int csizebase = MIPS3_CONFIG_C_DEFBASE;
164: #endif
165:
166: KASSERT(PAGE_SIZE != 0);
167:
168: /*
169: * Configure primary caches.
170: */
171: switch (MIPS_PRID_IMPL(cpu_id)) {
172: #ifdef MIPS1
173: case MIPS_R2000:
174: case MIPS_R3000:
175: mips_picache_size = r3k_picache_size();
176: mips_pdcache_size = r3k_pdcache_size();
177:
178: mips_picache_line_size = 4;
179: mips_pdcache_line_size = 4;
180:
181: mips_picache_ways = 1;
182: mips_pdcache_ways = 1;
183:
184: mips_pdcache_write_through = 1;
185:
186: mips_cache_ops.mco_icache_sync_all =
187: r3k_icache_sync_all;
188: mips_cache_ops.mco_icache_sync_range =
189: r3k_icache_sync_range;
190: mips_cache_ops.mco_icache_sync_range_index =
191: mips_cache_ops.mco_icache_sync_range;
192:
193: mips_cache_ops.mco_pdcache_wbinv_all =
194: r3k_pdcache_wbinv_all;
195: mips_cache_ops.mco_pdcache_wbinv_range =
196: r3k_pdcache_inv_range;
197: mips_cache_ops.mco_pdcache_wbinv_range_index =
198: mips_cache_ops.mco_pdcache_wbinv_range;
199: mips_cache_ops.mco_pdcache_inv_range =
200: r3k_pdcache_inv_range;
201: mips_cache_ops.mco_pdcache_wb_range =
202: r3k_pdcache_wb_range;
203:
204: uvmexp.ncolors = atop(mips_pdcache_size);
205: break;
206:
207: #ifdef ENABLE_MIPS_TX3900
208: case MIPS_TX3900:
209: switch (MIPS_PRID_REV_MAJ(cpu_id)) {
210: case 1: /* TX3912 */
211: mips_picache_ways = 1;
212: mips_picache_line_size = 16;
213: mips_pdcache_line_size = 4;
214:
215: tx3900_get_cache_config();
216:
217: mips_pdcache_write_through = 1;
218:
219: mips_cache_ops.mco_icache_sync_all =
220: tx3900_icache_sync_all_16;
221: mips_cache_ops.mco_icache_sync_range =
222: tx3900_icache_sync_range_16;
223: mips_cache_ops.mco_icache_sync_range_index =
224: tx3900_icache_sync_range_16;
225:
226: mips_cache_ops.mco_pdcache_wbinv_all =
227: tx3900_pdcache_wbinv_all_4;
228: mips_cache_ops.mco_pdcache_wbinv_range =
229: tx3900_pdcache_inv_range_4;
230: mips_cache_ops.mco_pdcache_wbinv_range_index =
231: tx3900_pdcache_inv_range_4;
232: mips_cache_ops.mco_pdcache_inv_range =
233: tx3900_pdcache_inv_range_4;
234: mips_cache_ops.mco_pdcache_wb_range =
235: tx3900_pdcache_wb_range_4;
236: break;
237:
238: case 3: /* TX3922 */
239: mips_picache_ways = 2;
240: mips_picache_line_size = 16;
241: mips_pdcache_line_size = 16;
242:
243: tx3920_get_cache_config();
244:
245: mips_cache_ops.mco_icache_sync_all =
246: mips_pdcache_write_through ?
247: tx3900_icache_sync_all_16 :
248: tx3920_icache_sync_all_16wb;
249: mips_cache_ops.mco_icache_sync_range =
250: mips_pdcache_write_through ?
251: tx3920_icache_sync_range_16wt :
252: tx3920_icache_sync_range_16wb;
253: mips_cache_ops.mco_icache_sync_range_index =
254: mips_cache_ops.mco_icache_sync_range;
255:
256: mips_cache_ops.mco_pdcache_wbinv_all =
257: mips_pdcache_write_through ?
258: tx3920_pdcache_wbinv_all_16wt :
259: tx3920_pdcache_wbinv_all_16wb;
260: mips_cache_ops.mco_pdcache_wbinv_range =
261: mips_pdcache_write_through ?
262: tx3920_pdcache_inv_range_16 :
263: tx3920_pdcache_wbinv_range_16wb;
264: mips_cache_ops.mco_pdcache_wbinv_range_index =
265: mips_cache_ops.mco_pdcache_wbinv_range;
266: mips_cache_ops.mco_pdcache_inv_range =
267: tx3920_pdcache_inv_range_16;
268: mips_cache_ops.mco_pdcache_wb_range =
269: mips_pdcache_write_through ?
270: tx3920_pdcache_wb_range_16wt :
271: tx3920_pdcache_wb_range_16wb;
272: break;
273:
274: default:
275: panic("mips_config_cache: unsupported TX3900");
276: }
277:
278: mips_pdcache_ways = 2;
279: tx3900_get_cache_config();
280:
281: uvmexp.ncolors = atop(mips_pdcache_size) / mips_pdcache_ways;
282: break;
283: #endif /* ENABLE_MIPS_TX3900 */
284: #endif /* MIPS1 */
285:
286: #ifdef MIPS3
1.6 takemura 287: case MIPS_R4100:
288: /*
289: * R4100 (NEC VR series) revision number means:
290: *
291: * MIPS_PRID_REV_MAJ MIPS_PRID_REV_MIN
292: * VR4102 4 ?
293: * VR4111 5 ?
294: * VR4181 5 ?
295: * VR4121 6 ?
296: * VR4122 7 0 or 1
297: * VR4181A 7 3 <
298: * VR4131 8 ?
299: */
300: /* Vr4131 has R4600 style 2-way set-associative cache */
301: if (MIPS_PRID_REV_MAJ(cpu_id) == 8)
302: goto primary_cache_is_2way;
303: /* FALLTHROUGH */
304:
1.2 thorpej 305: case MIPS_R4000:
306: case MIPS_R4300:
307: mips_picache_ways = 1;
308: mips_pdcache_ways = 1;
309: mips_sdcache_ways = 1;
310:
311: mips3_get_cache_config(csizebase);
312:
313: switch (mips_picache_line_size) {
314: case 16:
315: mips_cache_ops.mco_icache_sync_all =
316: r4k_icache_sync_all_16;
317: mips_cache_ops.mco_icache_sync_range =
318: r4k_icache_sync_range_16;
319: mips_cache_ops.mco_icache_sync_range_index =
320: r4k_icache_sync_range_index_16;
321: break;
322:
1.5 tsutsui 323: case 32:
324: mips_cache_ops.mco_icache_sync_all =
325: r4k_icache_sync_all_32;
326: mips_cache_ops.mco_icache_sync_range =
327: r4k_icache_sync_range_32;
328: mips_cache_ops.mco_icache_sync_range_index =
329: r4k_icache_sync_range_index_32;
330: break;
331:
1.2 thorpej 332: default:
333: panic("r4k picache line size %d",
334: mips_picache_line_size);
335: }
336:
337: switch (mips_pdcache_line_size) {
338: case 16:
339: mips_cache_ops.mco_pdcache_wbinv_all =
340: r4k_pdcache_wbinv_all_16;
341: mips_cache_ops.mco_pdcache_wbinv_range =
342: r4k_pdcache_wbinv_range_16;
343: mips_cache_ops.mco_pdcache_wbinv_range_index =
344: r4k_pdcache_wbinv_range_index_16;
345: mips_cache_ops.mco_pdcache_inv_range =
346: r4k_pdcache_inv_range_16;
347: mips_cache_ops.mco_pdcache_wb_range =
348: r4k_pdcache_wb_range_16;
1.5 tsutsui 349: break;
350:
351: case 32:
352: mips_cache_ops.mco_pdcache_wbinv_all =
353: r4k_pdcache_wbinv_all_32;
354: mips_cache_ops.mco_pdcache_wbinv_range =
355: r4k_pdcache_wbinv_range_32;
356: mips_cache_ops.mco_pdcache_wbinv_range_index =
357: r4k_pdcache_wbinv_range_index_32;
358: mips_cache_ops.mco_pdcache_inv_range =
359: r4k_pdcache_inv_range_32;
360: mips_cache_ops.mco_pdcache_wb_range =
361: r4k_pdcache_wb_range_32;
1.2 thorpej 362: break;
363:
364: default:
365: panic("r4k pdcache line size %d",
366: mips_pdcache_line_size);
367: }
368:
369: /* Virtually-indexed cache; no use for colors. */
370: break;
371:
372: case MIPS_R4600:
373: #ifdef ENABLE_MIPS_R4700
374: case MIPS_R4700:
375: #endif
376: #ifndef ENABLE_MIPS_R3NKK
377: case MIPS_R5000:
378: #endif
379: case MIPS_RM5200:
1.6 takemura 380: primary_cache_is_2way:
1.2 thorpej 381: mips_picache_ways = 2;
382: mips_pdcache_ways = 2;
383:
384: mips3_get_cache_config(csizebase);
385:
386: switch (mips_picache_line_size) {
387: case 32:
388: mips_cache_ops.mco_icache_sync_all =
389: r5k_icache_sync_all_32;
390: mips_cache_ops.mco_icache_sync_range =
391: r5k_icache_sync_range_32;
392: mips_cache_ops.mco_icache_sync_range_index =
393: r5k_icache_sync_range_index_32;
394: break;
395:
396: default:
397: panic("r5k picache line size %d",
398: mips_picache_line_size);
399: }
400:
401: switch (mips_pdcache_line_size) {
1.6 takemura 402: case 16:
403: mips_cache_ops.mco_pdcache_wbinv_all =
404: r5k_pdcache_wbinv_all_16;
405: mips_cache_ops.mco_pdcache_wbinv_range =
406: r5k_pdcache_wbinv_range_16;
407: mips_cache_ops.mco_pdcache_wbinv_range_index =
408: r5k_pdcache_wbinv_range_index_16;
409: mips_cache_ops.mco_pdcache_inv_range =
410: r5k_pdcache_inv_range_16;
411: mips_cache_ops.mco_pdcache_wb_range =
412: r5k_pdcache_wb_range_16;
413: break;
414:
1.2 thorpej 415: case 32:
416: mips_cache_ops.mco_pdcache_wbinv_all =
417: r5k_pdcache_wbinv_all_32;
418: mips_cache_ops.mco_pdcache_wbinv_range =
419: r5k_pdcache_wbinv_range_32;
420: mips_cache_ops.mco_pdcache_wbinv_range_index =
421: r5k_pdcache_wbinv_range_index_32;
422: mips_cache_ops.mco_pdcache_inv_range =
423: r5k_pdcache_inv_range_32;
424: mips_cache_ops.mco_pdcache_wb_range =
425: r5k_pdcache_wb_range_32;
426: break;
427:
428: default:
429: panic("r5k pdcache line size %d",
430: mips_pdcache_line_size);
431: }
432:
433: /*
434: * Deal with R4600 chip bugs.
435: */
436: if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4600 &&
437: MIPS_PRID_REV_MAJ(cpu_id) == 1) {
438: KASSERT(mips_pdcache_line_size == 32);
439: mips_cache_ops.mco_pdcache_wbinv_range =
440: r4600v1_pdcache_wbinv_range_32;
441: mips_cache_ops.mco_pdcache_inv_range =
442: r4600v1_pdcache_inv_range_32;
443: mips_cache_ops.mco_pdcache_wb_range =
444: r4600v1_pdcache_wb_range_32;
445: } else if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4600 &&
446: MIPS_PRID_REV_MAJ(cpu_id) == 2) {
447: KASSERT(mips_pdcache_line_size == 32);
448: mips_cache_ops.mco_pdcache_wbinv_range =
449: r4600v2_pdcache_wbinv_range_32;
450: mips_cache_ops.mco_pdcache_inv_range =
451: r4600v2_pdcache_inv_range_32;
452: mips_cache_ops.mco_pdcache_wb_range =
453: r4600v2_pdcache_wb_range_32;
1.8 ! shin 454: }
! 455:
! 456: /*
! 457: * Deal with VR4131 chip bugs.
! 458: */
! 459: if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4100 &&
! 460: MIPS_PRID_REV_MAJ(cpu_id) == 8) {
! 461: KASSERT(mips_pdcache_line_size == 16);
! 462: mips_cache_ops.mco_pdcache_wbinv_range =
! 463: vr4131v1_pdcache_wbinv_range_16;
1.2 thorpej 464: }
465:
466: /* Virtually-indexed cache; no use for colors. */
467: break;
468: #ifdef MIPS3_5900
469: case MIPS_R5900:
470: /* cache spec */
471: mips_picache_ways = 2;
472: mips_pdcache_ways = 2;
473: mips_picache_size = CACHE_R5900_SIZE_I;
474: mips_picache_line_size = CACHE_R5900_LSIZE_I;
475: mips_pdcache_size = CACHE_R5900_SIZE_D;
476: mips_pdcache_line_size = CACHE_R5900_LSIZE_D;
477: mips_cache_alias_mask =
478: ((mips_pdcache_size / mips_pdcache_ways) - 1) &
479: ~(PAGE_SIZE - 1);
480: mips_cache_prefer_mask =
481: max(mips_pdcache_size, mips_picache_size) - 1;
482: /* cache ops */
483: mips_cache_ops.mco_icache_sync_all =
484: r5900_icache_sync_all_64;
485: mips_cache_ops.mco_icache_sync_range =
486: r5900_icache_sync_range_64;
487: mips_cache_ops.mco_icache_sync_range_index =
488: r5900_icache_sync_range_index_64;
489: mips_cache_ops.mco_pdcache_wbinv_all =
490: r5900_pdcache_wbinv_all_64;
491: mips_cache_ops.mco_pdcache_wbinv_range =
492: r5900_pdcache_wbinv_range_64;
493: mips_cache_ops.mco_pdcache_wbinv_range_index =
494: r5900_pdcache_wbinv_range_index_64;
495: mips_cache_ops.mco_pdcache_inv_range =
496: r5900_pdcache_inv_range_64;
497: mips_cache_ops.mco_pdcache_wb_range =
498: r5900_pdcache_wb_range_64;
499: break;
500: #endif /* MIPS3_5900 */
501: #endif /* MIPS3 */
502:
503: default:
504: panic("can't handle primary cache on impl 0x%x\n",
505: MIPS_PRID_IMPL(cpu_id));
506: }
507:
508: /*
509: * Compute the "way mask" for each cache.
510: */
511: if (mips_picache_size) {
512: KASSERT(mips_picache_ways != 0);
513: mips_picache_way_size = (mips_picache_size / mips_picache_ways);
514: mips_picache_way_mask = mips_picache_way_size - 1;
515: }
516: if (mips_pdcache_size) {
517: KASSERT(mips_pdcache_ways != 0);
518: mips_pdcache_way_size = (mips_pdcache_size / mips_pdcache_ways);
519: mips_pdcache_way_mask = mips_pdcache_way_size - 1;
520: }
521:
1.4 thorpej 522: mips_dcache_compute_align();
523:
1.2 thorpej 524: if (mips_sdcache_line_size == 0)
525: return;
526:
527: /*
528: * Configure the secondary cache.
529: */
530: switch (MIPS_PRID_IMPL(cpu_id)) {
531: #ifdef MIPS3
532: case MIPS_R4000:
1.7 shin 533: /*
534: * R4000/R4400 always detects virtual alias as if
535: * primary cache size is 32KB. Actual primary cache size
536: * is ignored wrt VCED/VCEI.
537: */
538: mips_cache_alias_mask =
539: (MIPS3_MAX_PCACHE_SIZE - 1) & ~(PAGE_SIZE - 1);
540: mips_cache_prefer_mask = MIPS3_MAX_PCACHE_SIZE - 1;
541: /* FALLTHROUGH */
1.2 thorpej 542: case MIPS_R4100:
543: case MIPS_R4300:
544: case MIPS_R4600:
545: #ifdef ENABLE_MIPS_R4700
546: case MIPS_R4700:
547: #endif
548: #ifndef ENABLE_MIPS_R3NKK
549: case MIPS_R5000:
550: #endif
551: case MIPS_RM5200:
552: switch (mips_sdcache_ways) {
553: case 1:
554: switch (mips_sdcache_line_size) {
555: case 32:
556: mips_cache_ops.mco_sdcache_wbinv_all =
557: r4k_sdcache_wbinv_all_32;
558: mips_cache_ops.mco_sdcache_wbinv_range =
559: r4k_sdcache_wbinv_range_32;
560: mips_cache_ops.mco_sdcache_wbinv_range_index =
561: r4k_sdcache_wbinv_range_index_32;
562: mips_cache_ops.mco_sdcache_inv_range =
563: r4k_sdcache_inv_range_32;
564: mips_cache_ops.mco_sdcache_wb_range =
565: r4k_sdcache_wb_range_32;
566: break;
567:
568: case 16:
569: case 64:
570: mips_cache_ops.mco_sdcache_wbinv_all =
571: r4k_sdcache_wbinv_all_generic;
572: mips_cache_ops.mco_sdcache_wbinv_range =
573: r4k_sdcache_wbinv_range_generic;
574: mips_cache_ops.mco_sdcache_wbinv_range_index =
575: r4k_sdcache_wbinv_range_index_generic;
576: mips_cache_ops.mco_sdcache_inv_range =
577: r4k_sdcache_inv_range_generic;
578: mips_cache_ops.mco_sdcache_wb_range =
579: r4k_sdcache_wb_range_generic;
1.3 thorpej 580: break;
581:
582: case 128:
583: mips_cache_ops.mco_sdcache_wbinv_all =
584: r4k_sdcache_wbinv_all_128;
585: mips_cache_ops.mco_sdcache_wbinv_range =
586: r4k_sdcache_wbinv_range_128;
587: mips_cache_ops.mco_sdcache_wbinv_range_index =
588: r4k_sdcache_wbinv_range_index_128;
589: mips_cache_ops.mco_sdcache_inv_range =
590: r4k_sdcache_inv_range_128;
591: mips_cache_ops.mco_sdcache_wb_range =
592: r4k_sdcache_wb_range_128;
1.2 thorpej 593: break;
594:
595: default:
596: panic("r4k sdcache %d way line size %d\n",
597: mips_sdcache_ways, mips_sdcache_line_size);
598: }
599: break;
600:
601: default:
602: panic("r4k sdcache %d way line size %d\n",
603: mips_sdcache_ways, mips_sdcache_line_size);
604: }
605: break;
606: #endif /* MIPS3 */
607:
608: default:
609: panic("can't handle secondary cache on impl 0x%x\n",
610: MIPS_PRID_IMPL(cpu_id));
611: }
612:
613: /*
614: * Compute the "way mask" for each secondary cache.
615: */
616: if (mips_sdcache_size) {
617: KASSERT(mips_sdcache_ways != 0);
618: mips_sdcache_way_size = (mips_sdcache_size / mips_sdcache_ways);
619: mips_sdcache_way_mask = mips_sdcache_way_size - 1;
620: }
1.4 thorpej 621:
622: mips_dcache_compute_align();
1.2 thorpej 623: }
624:
625: #ifdef MIPS1
626: #ifdef ENABLE_MIPS_TX3900
627: /*
628: * tx3900_get_cache_config:
629: *
630: * Fetch cache size information for the TX3900.
631: */
632: void
633: tx3900_get_cache_config(void)
634: {
635: uint32_t config;
636:
637: config = tx3900_cp0_config_read();
638:
639: mips_picache_size = R3900_C_SIZE_MIN <<
640: ((config & R3900_CONFIG_ICS_MASK) >> R3900_CONFIG_ICS_SHIFT);
641:
642: mips_pdcache_size = R3900_C_SIZE_MIN <<
643: ((config & R3900_CONFIG_DCS_MASK) >> R3900_CONFIG_DCS_SHIFT);
644: }
645:
646: /*
647: * tx3920_get_cache_config:
648: *
649: * Fetch cache size information for the TX3920.
650: */
651: void
652: tx3920_get_cache_config(void)
653: {
654:
655: /* Size is the same as TX3900. */
656: tx3900_get_cache_config();
657:
658: /* Now determine write-through/write-back mode. */
659: if ((tx3900_cp0_config_read() & R3900_CONFIG_WBON) == 0)
660: mips_pdcache_write_through = 1;
661: }
662: #endif /* ENABLE_MIPS_TX3900 */
663: #endif /* MIPS1 */
664:
665: #ifdef MIPS3
666: /*
667: * mips3_get_cache_config:
668: *
669: * Fetch the cache config information for a MIPS-3 or MIPS-4
670: * processor (virtually-indexed cache).
671: *
672: * NOTE: Fetching the size of the secondary cache is something
673: * that platform specific code has to do. We'd appreciate it
674: * if they initialized the size before now.
675: *
676: * ALSO NOTE: The number of ways in the cache must already be
677: * initialized.
678: */
679: void
680: mips3_get_cache_config(int csizebase)
681: {
682: uint32_t config = mips3_cp0_config_read();
683:
684: mips_picache_size = MIPS3_CONFIG_CACHE_SIZE(config,
685: MIPS3_CONFIG_IC_MASK, csizebase, MIPS3_CONFIG_IC_SHIFT);
686: mips_picache_line_size = MIPS3_CONFIG_CACHE_L1_LSIZE(config,
687: MIPS3_CONFIG_IB);
688:
689: mips_pdcache_size = MIPS3_CONFIG_CACHE_SIZE(config,
690: MIPS3_CONFIG_DC_MASK, csizebase, MIPS3_CONFIG_DC_SHIFT);
691: mips_pdcache_line_size = MIPS3_CONFIG_CACHE_L1_LSIZE(config,
692: MIPS3_CONFIG_DB);
693:
694: mips_cache_alias_mask =
695: ((mips_pdcache_size / mips_pdcache_ways) - 1) & ~(PAGE_SIZE - 1);
696: mips_cache_prefer_mask =
697: max(mips_pdcache_size, mips_picache_size) - 1;
698:
699: if ((config & MIPS3_CONFIG_SC) == 0) {
700: mips_sdcache_line_size = MIPS3_CONFIG_CACHE_L2_LSIZE(config);
701: if ((config & MIPS3_CONFIG_SS) == 0)
702: mips_scache_unified = 1;
703: }
704: }
705: #endif /* MIPS3 */
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