CVS log for src/sys/arch/mips/include/pmap.h

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MI PMAP hardware page table walker support.

This is based on code given to me by Matt Thomas a long time ago with
many updates and bugs fixes from me.

consistency. NFCI.

Sync w/ HEAD.

Support __HAVE_PMAP_PV_TRACK in sys/uvm/pmap based pmaps (aka common pmap)

port crash(8) to mips.  (most of the kernel side.)

- expose parts of _KERNEL to _KMEMUSER as well
- hide more things for _KERNEL
- avoid DB_MACHINE_COMMANDS in crash(8)
- XXX add mips_label_t for !_KERNEL and use it in the pcb to
  avoid conflicting with the ddb/crash one
- enable dumppcb

some changes to make stack trace fail instead of SEGV and
the userland changes to crash itself not part of this change.

Provide a pmap_segtab_deactivate for symmetry with pmap_segtab_activate
and use it in pmap_deactivate

Call pmap_md_xtab_{,de}activate from pmap_segtab_{,de}activate to be used
for PMAP_HWPAGEWALKER and any caches ops that might be required.

Provide empty (for now) pmap_md_xtab_{,de}activate functions on the
platforms that use sys/uvm/pmap

#define<tab>
Nuke trailing whitespace.

Sync with HEAD

s/adddress/address/

update from HEAD

Pull up following revision(s) (requested by skrll in ticket #1068):
	sys/arch/mips/include/pmap.h: revision 1.63
	sys/arch/mips/mips/pmap.c: revision 1.214
	sys/arch/mips/mips/pmap_segtab.c: revision 1.8
Deal with incompatible cache aliases. Specifically,
- always flush an ephemeral page on unmap
- track unmanaged mappings (mappings entered via pmap_kenter_pa) for
    aliases where required and handle appropriately (via pmap_enter_pv)
Hopefully this (finally) addresses the instability reported in the
following PRs:
PR/44900 - R5000/Rm5200 mips ports are broken
PR/46890 - upcoming NetBSD 6.0 release is very unstable / unusable on cobalt qube 2
PR/48628 - cobalt and hpcmips ports are dead

Pull up following revision(s) (requested by skrll in ticket #1068):
	sys/arch/mips/include/pmap.h: revision 1.63
	sys/arch/mips/mips/pmap.c: revision 1.214
	sys/arch/mips/mips/pmap_segtab.c: revision 1.8
Deal with incompatible cache aliases. Specifically,
- always flush an ephemeral page on unmap
- track unmanaged mappings (mappings entered via pmap_kenter_pa) for
    aliases where required and handle appropriately (via pmap_enter_pv)
Hopefully this (finally) addresses the instability reported in the
following PRs:
PR/44900 - R5000/Rm5200 mips ports are broken
PR/46890 - upcoming NetBSD 6.0 release is very unstable / unusable on cobalt qube 2
PR/48628 - cobalt and hpcmips ports are dead

Pull up following revision(s) (requested by mrg in ticket #231):
	distrib/sets/lists/base/md.evbmips		1.3
	doc/CHANGES					1.2303-1.2304
	etc/etc.evbmips/MAKEDEV.conf			1.8
	etc/etc.evbmips/Makefile.inc			1.22
	etc/mtree/Makefile				1.37
	etc/mtree/NetBSD.dist.evbmips			1.1
	sys/arch/evbmips/Makefile			1.9
	sys/arch/evbmips/conf/SBMIPS			upto 1.2
	sys/arch/evbmips/conf/SBMIPS.MP			upto 1.2
	sys/arch/evbmips/conf/SBMIPS64			upto 1.2
	sys/arch/evbmips/conf/SBMIPS64.MP		upto 1.2
	sys/arch/evbmips/conf/files.sbmips		upto 1.2
	sys/arch/evbmips/conf/std.sbmips		upto 1.2
	sys/arch/evbmips/include/disklabel.h		1.6
	sys/arch/evbmips/include/loadfile_machdep.h
	sys/arch/evbmips/include/param.h		1.10
	sys/arch/evbmips/include/pci_machdep.h		1.3
	sys/arch/evbmips/sbmips/TODO
	sys/arch/evbmips/sbmips/autoconf.c
	sys/arch/evbmips/sbmips/autoconf.h
	sys/arch/evbmips/sbmips/console.c
	sys/arch/evbmips/sbmips/cpu.c			upto 1.3
	sys/arch/evbmips/sbmips/cpuvar.h
	sys/arch/evbmips/sbmips/disksubr.c
	sys/arch/evbmips/sbmips/leds.h
	sys/arch/evbmips/sbmips/locore_machdep.S
	sys/arch/evbmips/sbmips/machdep.c		upto 1.2
	sys/arch/evbmips/sbmips/rtc.c			upto 1.2
	sys/arch/evbmips/sbmips/sb1250_icu.c		upto 1.2
	sys/arch/evbmips/sbmips/swarm.h
	sys/arch/evbmips/sbmips/systemsw.c		upto 1.2
	sys/arch/evbmips/sbmips/systemsw.h
	sys/arch/evbmips/sbmips/zbbus.c			upto 1.2
	sys/arch/evbmips/stand/Makefile			1.1
	sys/arch/evbmips/stand/sbmips/Makefile
	sys/arch/evbmips/stand/sbmips/Makefile.bootprogs upto 1.2
	sys/arch/evbmips/stand/sbmips/Makefile.bootprogs 1.3
	sys/arch/evbmips/stand/sbmips/Makefile.bootxx
	sys/arch/evbmips/stand/sbmips/Makefile.inc	upto 1.3
	sys/arch/evbmips/stand/sbmips/boot/Makefile
	sys/arch/evbmips/stand/sbmips/boot/filesystem.c
	sys/arch/evbmips/stand/sbmips/boot/version
	sys/arch/evbmips/stand/sbmips/bootxx_cd9660/Makefile
	sys/arch/evbmips/stand/sbmips/bootxx_ffs/Makefile
	sys/arch/evbmips/stand/sbmips/bootxx_lfs/Makefile
	sys/arch/evbmips/stand/sbmips/common/bbinfo.h
	sys/arch/evbmips/stand/sbmips/common/blkdev.c	upto 1.2
	sys/arch/evbmips/stand/sbmips/common/blkdev.h
	sys/arch/evbmips/stand/sbmips/common/boot.c	upto 1.2
	sys/arch/evbmips/stand/sbmips/common/boot.ldscript
	sys/arch/evbmips/stand/sbmips/common/booted_dev.c upto 1.2
	sys/arch/evbmips/stand/sbmips/common/bootxx.c
	sys/arch/evbmips/stand/sbmips/common/cfe.c
	sys/arch/evbmips/stand/sbmips/common/cfe_api.c
	sys/arch/evbmips/stand/sbmips/common/cfe_api.h
	sys/arch/evbmips/stand/sbmips/common/cfe_api_int.h
	sys/arch/evbmips/stand/sbmips/common/cfe_error.h
	sys/arch/evbmips/stand/sbmips/common/cfe_ioctl.h
	sys/arch/evbmips/stand/sbmips/common/checksize.sh
	sys/arch/evbmips/stand/sbmips/common/common.h
	sys/arch/evbmips/stand/sbmips/common/panic_putstr.c
	sys/arch/evbmips/stand/sbmips/common/putstr.c
	sys/arch/evbmips/stand/sbmips/common/start.S
	sys/arch/evbmips/stand/sbmips/netboot/Makefile
	sys/arch/evbmips/stand/sbmips/netboot/conf.c
	sys/arch/evbmips/stand/sbmips/netboot/dev_net.c
	sys/arch/evbmips/stand/sbmips/netboot/devopen.c
	sys/arch/evbmips/stand/sbmips/netboot/getsecs.c	upto 1.2
	sys/arch/evbmips/stand/sbmips/netboot/if_cfe.c	upto 1.2
	sys/arch/evbmips/stand/sbmips/netboot/version
	sys/arch/mips/conf/files.sibyte			1.8
	sys/arch/mips/include/pmap.h			1.70
	sys/arch/mips/sibyte/dev/sbbuswatch.c		1.4
	sys/arch/mips/sibyte/dev/sbmac.c		1.49
	sys/arch/mips/sibyte/dev/sbscn.c		1.43
	sys/arch/mips/sibyte/dev/sbsmbus.c		1.17
	sys/arch/mips/sibyte/dev/sbtimer.c		1.21
	sys/arch/mips/sibyte/dev/sbwdog.c		1.15
	sys/arch/mips/sibyte/pci/sbbrz_pci.c		1.8
	usr.sbin/installboot/installboot.8		1.94

Move sys/arch/sbmips/* into sys/arch/evbmips/*/sbmips.

Sync with HEAD

mostly converted sbmips -> evbmips.  the SBMIPS kernel builds fully
sans disksubr.c.  intr.h does not need any additional fixes now,
only disklabel.h.

also test-built some other mips kernels.

Sync with HEAD

Sync with HEAD.  (Note that most of these changes are simply $NetBSD$
tag issues.)

"Make NetBSD great again!"

Introduce uvm_hotplug(9) to the kernel.

Many thanks, in no particular order to:

TNF, for funding the project.

Chuck Silvers - for multiple API reviews and feedback.
Nick Hudson - for testing on multiple architectures and bugfix patches.
Everyone who helped with boot testing.

KeK (http://www.kek.org.in) for hosting the primary developers.

Sync with HEAD

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Sync with HEAD

Define (but not use) separate kernel and user pagetables.
Move to the new names.

Add struct pmap_limits and pm_{min,max}addr from uvm/pmap/map.h and use it to
store avail_start, avail_end, virtual_start, and virtual_end.
Remove iospace and let emips just bump pmap_limits.virtual_start to get the
VA space it needs.
pmap_segtab.c is almost identical to uvm/pmap/pmap_segtab.c now.  It won't
be long until we switch to the uvm/pmap one.

Transition from __cpuset_t to kcpuset_t *.  This brings the local pmap one
step closer to uvm/pmap, its eventual replacement.  Tested on ERLITE MP kernel.

assembly no longer include <machine/cpu.h>.  Instead MIPS_CURLWP is gotten
from regdef.h and everything else from assym.h.  <mips/mips_param.h> no
longer include <machine/cpu.h>

Rebase to HEAD as of a few days ago.

Rebase.

Pull up following revision(s) (requested by skrll in ticket #1068):
	sys/arch/mips/mips/pmap.c: revision 1.214
	sys/arch/mips/include/pmap.h: revision 1.63
	sys/arch/mips/mips/pmap_segtab.c: revision 1.8
Deal with incompatible cache aliases. Specifically,
- always flush an ephemeral page on unmap
- track unmanaged mappings (mappings entered via pmap_kenter_pa) for
    aliases where required and handle appropriately (via pmap_enter_pv)
Hopefully this (finally) addresses the instability reported in the
following PRs:
PR/44900 - R5000/Rm5200 mips ports are broken
PR/46890 - upcoming NetBSD 6.0 release is very unstable/unusable on cobalt qube2
PR/48628 - cobalt and hpcmips ports are dead

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Deal with incompatible cache aliases. Specifically,

- always flush an ephemeral page on unmap
- track unmanaged mappings (mappings entered via pmap_kenter_pa) for
  aliases where required and handle appropriately (via pmap_enter_pv)

Hopefully this (finally) addresses the instability reported in the
following PRs:

PR/44900 - R5000/Rm5200 mips ports are broken
PR/46890 - upcoming NetBSD 6.0 release is very unstable / unusable on cobalt qube 2
PR/48628 - cobalt and hpcmips ports are dead

sync with head

Fix some LP64 bugs

Make MIPS use a multi-level page table for the kernel address space.
(just like the user address does).   XXX fix mips1

Use a spinlock to protect the segtab queues.  Use union pmap_segmap and
pmap_segmap_t to track -HEAD.  Use KERNEL_PID for the same reason.

Pull up following revision(s) (requested by matt in ticket #406):
	sys/arch/mips/include/pmap.h: revision 1.62
	sys/arch/mips/mips/pmap.c: revision 1.208
	sys/arch/mips/mips/pmap_segtab.c: revision 1.5
Change lockless segtab management to use a mutex for protection.  Some =
minor
changes to make this closer to common/pmap/tlb/pmap_segtab.c
=20
=20

Change lockless segtab management to use a mutex for protection.  Some minor
changes to make this closer to common/pmap/tlb/pmap_segtab.c

Add a page-table-page cache to keep reuse just released page table tables.
Actually remove the addresses in pmap_remove_all.

Move the ksegx tlb init code into its own function.
Fix a problem with concurrent shootdowns by tracking what cpus want a
shootdown for a pmap, and if anoter cpu wants a shootdown, perform the
shootdown on ourselves.

When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses.  There are exceptions.
bus_space_handles are now register_t instead of intptr_t.  This allows them
to contain XKPHYS addresses.  Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address.  This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs.  If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.

Deal with not defining PAGE_SIZE or PAGE_SHIFT for non-kernel inclusion.

Make these play nice with modules.

Split syncicache functions into separate file: pmap_syncicache.
Support up to 1024 ASIDs.
Always use atomic ops for manipulating pm_shootdown_pending
Nuke PMAP_POOLPAGE_DEBUG
defparam MIPS_PAGE_SHIFT
Track colors of execpages.

Rework things a bit for the XLR/XLS/XLP TLB.  Before dealing with the TLB when
MP on the XL?, disable interrupts and take out a lock to prevent concurrent
updates to the TLB.  In the TLB miss and invalid exception handlers, if the
lock is already owned by another CPU, simply return from the exception and
let it continue or restart as appropriate.  This prevents concurrent TLB
exceptions in multiple threads from possibly updating the TLB multiple times
for a single address.

support BUS_SPACE_MAP_PREFETCH in order to allow mapping device memory and
DMA buffers with cacheing disabled but things like write combining, relaxed
ordering etc. allowed when the CPU supports it
so far enabled only on Loongson, should work on R1xk and probably newer CPUs

Sync with HEAD.

Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code.  (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.

sync with head

Sync with HEAD

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

- protect option includes ("opt_multiprocessor.h") with #ifdef _KERNEL_OPT

- include opt_multiprocessor.h for explicit MULTIPROCESSOR dependency

Add a pmap_asid_check which verifies the current ASID is in COP0 ENTRY_HI

Sync with HEAD.

Move struct vm_page_md definition from vmparam.h to pmap.h, because
it's used only by pmap.  vmparam.h has definitions for wider
audience.

All GENERIC kernels build tested, except ia64.

powerpc/include/booke/vmparam.h has one too, but it has no pmap.h,
so it's left as is.

Sync with HEAD.

Support user VAs > 4GB (but less than 1TB for now) using a 3 level page table.
Add debug code to help find redundant faults (PMAP_FAULTINFO).

sync with head.

Turn PMAP_NOCACHE into MI flag.
Add MI flags PMAP_WRITE_COMBINE, PMAP_WRITE_BACK, PMAP_NOCACHE_OVR.
Update pmap(9) manpage.

hppa: Remove MD PMAP_NOCACHE flag as it exists as MI flag
mips: Rename MD PMAP_NOCACHE to PGC_NOCACHE.

x86: Implement new MI flags using Page-Attribute Tables.
x86: Implement BUS_SPACE_MAP_PREFETCHABLE.

Patch presented on tech-kern@:
http://mail-index.netbsd.org/tech-kern/2010/06/30/msg008458.html

No comments on this last version.

Add pm_flags and PMAP_DEFERRED_ACTIVATE

sync with head

Add MP-aware icache support.

Add mipsXX_tlb_enter which modifies/sets a specific TLB entry with a new
mapping (useful for wired TLB entries).
Add mips_fixup_exceptions which will walk through the exception vectors
and allows the fixup of any cpu_info references to be changed to a more
MP-friendly incarnation.
Define a common fixup method to use a wired TLB entry at -PAGE_SIZE allowing
direct loads using a negative based from the zero register.
Change varible pmap_tlb_info t pmap_tlb0_info.

Make the UP and MP ASID allocation algorithm common.  Significantly improve
the algorithm.  Now when we exhaust the ASIDs, interrogate the TLB for active
ASIDS and release all the other for future allocations.  This leaves the
TLB entries with ASIDs valid avoiding the need to re-incur TLB misses for
them.

Make sure <mips/locore.h> is not included by MI code.
Add send_ipi and cpu_offline_md hooks to locoresw.
Add MP support to pmap (pvlist locking, tlb locking).
Add TLB shootdown support (see comment at the top of mips/pmap_tlb.c).
Add mipsXX_tlb_invalidate_globals routine

Revamp pmap.  Add exec page caching logic from powerpc oea pmap.  Shrink struct
vm_page by placing the first pv_entry in it.  Remove pv_flags since nothing
really needed it.  Add pmap counters.  Rework virtual cache alias logic.
Allow pmap_copy_page and pmap_zero_page to deal with non-KSEG0 mappable pages.

Seperate the pmap TLB functions into their own file.
For 32 bit kernels, make sure that mips_virtual_end doesn't go past
VM_MAX_KERNEL_ADDRESS.

Revamp things a bit.  Move of the globals mips uses into either cpu_info,
mips_options, or mips_cache_info.  Make MALT64 be able to boot MULTIPROCESSOR.
(some pmap MP work).

Get rid of most of the studly caps.
First to MULTIPROCESSOR support for pmap: move some pmap globals to cpu_info.
Define per-cpu ASID number spaces.
Remove some mips1/!mips1 difference in db_interface.c
Add mips32/64 knowledge to stacktrace.

Add generic support for DMA bounce buffers and real version of
bus_dmatag_subregion.  MALTA uses it for ISADMA.  Make RMIXL use
for creating 32bit and 29bit subregions.

Use mips_page_physload and mips_init_lwp0_uarea.

Please segtab lookups into separate file.
Add mips_add_physload
Add mips_init_lwp0_uarea
cleanup lwp0/cpu_info_store initialization.

Merge from matt-nb5-mips64
Merge mips-specific arch files.

Cleanup for LP64.  XXX pv_entry needs work.

sync with head.

Since pmap.c rev 1.163, page attributes of PV_MODIFIED and PV_REFERENCED
have beem moved from pv_flags in struct pv_entry to pvh_attrs in
struct vm_page_md, so no need to copy pv_flags to keep these flags
in pv header in pmap_remove_pv(). Pointed out by uebayasi@ on port-mips.
Also rename those page attribute flags from PV_FOO to PGA_FOO like alpha.
While here, make pv_flags unsigned.

Briefly tested on sgimips O2.

sync with head.

Sync with HEAD.

Sync with HEAD.

Update haad-dm branch to haad-dm-base2.

Make pmap_kernel() a MI macro for struct pmap *kernel_pmap_ptr,
which is now the "API" provided by the pmap module.  pmap_kernel()
remains as the syntactic sugar.

Bonus cosmetics round: move all the pmap_t pointer typedefs into
uvm_pmap.h.

Thanks to Greg Oster for providing cpu muscle for doing test builds.

Sync with HEAD.

sync with head

sync with HEAD

Sync with HEAD

Merge more changes from vmlocking2, mainly:

- Locking improvements.
- Use pool_cache for more items.

Pull the vmlocking changes into a new branch.

sync with HEAD

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Sync with HEAD

sync with head.

Sync with HEAD.

if we have 64bit paddr_t add a flag which indicates non-cachable for use
with mmap*() and pmap_enter()
Mainly for allowing userland to mmap() the O2's framebuffer uncached

change pmap_phys_address()s parameter to paddr_t since that's what it gets
fed from mmap*() anyway
approved by gimpy

Get pmax working.

sync with head

Sync with head.

sync with head.

Change "inline" back to "__inline" in .h files -- C99 is still too
new, and some apps compile things in C89 mode. C89 keywords stay.

As per core@.

Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.

merge ktrace-lwp.

Pull up following revision(s) (requested by tsutsui in ticket #961):
	sys/arch/mips/mips/cache.c: revision 1.27
	sys/arch/mips/include/cache.h: revision 1.8
	sys/arch/mips/mips/pmap.c: revision 1.158
	sys/arch/mips/mips/vm_machdep.c: revision 1.106
	sys/arch/mips/mips/mem.c: revision 1.30
	sys/arch/mips/include/pmap.h: revision 1.47
Add a workaround to handle virtual alias which may cause data corruption
on R5000/Rm52xx machines:
- Add a new global variable mips_cache_virtual_alias in mips/cache.c,
  which indicates that VIPT cache on the CPU could cause virtual alias
  and software support is required to handle it. (i.e. no VCED/VCEI)
- Add several cache flush/invalidate ops around KSEG0 access which
  might cause virtual alias if mips_cache_virtual_alias is true.
  (note checking mips_sdcache_line_size isn't valid for R5000/Rm52xx
   because only R4000/R4400 with L2 cache have VCED/VCEI)
- Remove a global variable mips_sdcache_forceinv, which is now superseded
  by new mips_cache_virtual_alias.
While here, also change some R4000/R4400 cache ops:
- Don't override mips_cache_alias_mask and mips_cache_prefer_mask with
  values based on MIPS3_MAX_PCACHE_SIZE for R4000/R4400 with L2 cache
  because it's still worth to reduce VCED/VCEI.
- Flush dcache in pmap_zero_page(9) unconditionally on all MIPS_HAS_R4K_MMU
  CPUs and remove cache flush code from cpu_lwp_fork() in vm_machdep.c.
Thanks to Markus W Kilbinger for testing patches on port-cobalt/port-mips.
XXX This fix is just a workaround because it doesn't handle all possible
XXX virtual aliases. As discussed on port-mips, maybe the real fix
XXX for virtual alias is to change MI UVM to adapt it to VIPT cache.
XXX (all VA mappings against the same PA must have the same VAC index etc.)

sync with -current

Sync with HEAD.

sync with head.

Add a workaround to handle virtual alias which may cause data corruption
on R5000/Rm52xx machines:
- Add a new global variable mips_cache_virtual_alias in mips/cache.c,
  which indicates that VIPT cache on the CPU could cause virtual alias
  and software support is required to handle it. (i.e. no VCED/VCEI)
- Add several cache flush/invalidate ops around KSEG0 access which
  might cause virtual alias if mips_cache_virtual_alias is true.
  (note checking mips_sdcache_line_size isn't valid for R5000/Rm52xx
   because only R4000/R4400 with L2 cache have VCED/VCEI)
- Remove a global variable mips_sdcache_forceinv, which is now superseded
  by new mips_cache_virtual_alias.

While here, also change some R4000/R4400 cache ops:
- Don't override mips_cache_alias_mask and mips_cache_prefer_mask with
  values based on MIPS3_MAX_PCACHE_SIZE for R4000/R4400 with L2 cache
  because it's still worth to reduce VCED/VCEI.
- Flush dcache in pmap_zero_page(9) unconditionally on all MIPS_HAS_R4K_MMU
  CPUs and remove cache flush code from cpu_lwp_fork() in vm_machdep.c.

Thanks to Markus W Kilbinger for testing patches on port-cobalt/port-mips.


XXX This fix is just a workaround because it doesn't handle all possible
XXX virtual aliases. As discussed on port-mips, maybe the real fix
XXX for virtual alias is to change MI UVM to adapt it to VIPT cache.
XXX (all VA mappings against the same PA must have the same VAC index etc.)

Sync with HEAD.

Teach mips pmap_prefer() to deal with topdown.

Tested by simonb.

Convert the PMAP_PREFER() macro from two arguments (offset and hint)
to four (adding size and direction).

In order for topdown uvm to be an option on ports using PMAP_PREFER,
they will need to "prefer" lower addresses if topdown is being used.
Additionally, at least one port also needs to know the size.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

Cast the arg to MIPS_KSEG0_TO_PHYS() in POOL_VTOPHYS() (thanks, nathan!).

Add the ability for pool caches to cache the physical address of
objects.  Clients of the pool_cache API must consistently use
the "paddr" variants or not, otherwise behavior is undefined.

Enable this on Alpha, ARM, MIPS, and x86.  Other platforms must
define POOL_VTOPHYS() in the appropriate manner in order to enable
the feature.

Part 1 of a series of simple patches contributed by Wasabi Systems
to improve network performance.

Sync with HEAD.

Standardise on #ifdef _MIPS_<header>_H_ for multiple inclusion tests.

Catch up to -current.

sync kqueue with -current; this includes merge of gehenna-devsw branch,
merge of i386 MP branch, and part of autoconf rototil work

it really helps to get the stub right before cutting + pasting it 27 times.
alas, I did not.  doh.

add pmap_remove_all() hook (empty on most platforms so far).

Catch up to -current.
(CVS: It's not just a program. It's an adventure!)

Catch up with -current.

Add support for MIPS32 and MIPS64 architectures:
  Better cache coherency attribute macros (from Broadcom Corp).

Catch up with -current.

Update the kqueue branch to HEAD.

file pmap.h was added on branch nathanw_sa on 2002-04-01 07:40:59 +0000

Update pmap_update to now take the updated pmap as an argument.
This will allow improvements to the pmaps so that they can more easily defer expensive operations, eg tlb/cache flush, til the last possible moment.

Currently this is a no-op on most platforms, so they should see no difference.

Reviewed by Jason.

Merge Aug 24 -current into the kqueue branch.

remove the uncached idle-loop page zeroing.
(to be replaced by a version that uses the cache...)

Catch up to -current.

replace vm_page_t with struct vm_page *.

replace {simple_,}lock{_data,}_t with struct {simple,}lock {,*}.

Sync with HEAD.

Undo a misguided previous change to the pmap_update() API.

Give pmap_update() an argument (a pmap_t) so that it knows which
pmap it should be updating.

#define away pmap_update() in <machine/pmap.h> so that no function
call overhead is incurred as we start sprinkling pmap_update() calls
throughout the source tree (no pmaps currently defer operations, but
we are adding the infrastructure to allow them to do so).

Sync with HEAD

- fix typos in mips_user_cacheflush() and mips_user_cachectl().
- relocate those function declarations from include/pmap.h.

Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.

Make PMAP_PAGEIDLEZERO() return a boolean value.  FALSE indidcates
that the page being zero'd was not completed and that page zeroing
should be aborted.  This may be used by machine-dependent code doing
slow page access to reduce the latency of running a process that has
become runnable while in the middle of doing a slow page zero.

Zero free pages in the idle loop.

Sync w/ -current.

- Move MachSetPID(1) call to pmap_bootstrap() adajacent to kernel pmap
initialization code.
- Abandon mips_init_proc0() and do the 4 lines straightly in MD mach_init().
- Restore a block of code accidentally lost in prevous commit.
- Change the term 'tlbpid' to a MIPS3 nomenclature 'asid'.
- Hide PTE size exposures by symbolic names in locore.S

Nuke register and remove trailling white space.

MIPS part of fix for PR 6152, sligtly changed from M.Hitch's version

Remove vestiges of cpuarch.h.  Revert to using cpuregs.h instead.

* Create mips_reg_t data type to allow register size to be
  decoupled from long or int or long long.  Define macros in asm.h to facilitate
  choosing these on a port by port basis.

* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
  to be calculated at system build time.

* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
  for the architecture.  For 64-bit oriented systems set the Status Register
  to allow 64-bit instructions.

* Remove UADDR related macros because kernel U structure is now mapped
  normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors

- Complete vm_offset_t purge for mips processor.
- bzero() -> memset() and bcopy() -> memcpy().
- Garbage collection in trap.c and db_interface.c.

pull up 1.21 - PV_REFERENCED

Add PV_REFERENCED and track as for PV_MODIFIED,.

UVM relies on pmap modules keeping track of modified/referenced bits
after a page has been removed from all mappings.  So *dont* clear
PV_REFERENCED or PV_MODIFIED flags in pmap_remove().

- Step forward to MIPS64 support.  Incorporate partially Caster Fu's
patches.  Still some work is missing to satisfy his QED 5230 port.

- More symbolic definitions in genassym.cf which improve possible 64bit-ness
of locore_mips{1,3}.S.

- Fix mips3 L1 cache line size detection logic in cpuarch.h as pointed by
Caster.

- Fix a bug in proc_trampoline() code in locore_mips3.S as pointed by Caster.

- Replace vm_offset_t with vaddr_t/paddr_t entirely.  Note that
NetBSD/newsmips has purged vm_offset_t too.

- Synchronize various files according to recent changes made in main trunk.

sync to trunk (page modified bit handling, needed for UVM)

Change page modification emulation:  don't fiddle with VM flags directly.
Track page modification status in the PV entry like the alpha, and let
pmap_is_modified() return current status back to the VM system.  UVM now
works reliably.

Garbage collect the old pmap_attribute[] stuff.

- cpuregs.h was modifed a bit, then renamed with cpuarch.h.
- mips_cpu.h has gone.
- CPU's register mnemonics in regdef.h is now a part of asm.h.

Fix typo with new poolpage stuff

Provide PMAP_{,UN}MAP_POOLPAGE().

Implement and switch to MACHINE_NEW_NONCONTIG.

Now that all ports have pmap_activate(), and it has an identical interface,
prototype it in <vm/pmap.h>

Update marc-pcmcia branch from trunk.

mips pmap_activate:
 * prototype and definition for pmap_activate(p). Updates the segtab,
   and changes the active ASID if p == curproc.
 * Make reserved fixed-address (UADDR) kernelstack PTEs global,
   so we still have a kernel stack after pmap_activate() on curproc.
 * make KSEG2 mappings for p_addr global (see above.)

Seems to detune contextswitch and NTP resolution (by 60 ms), but
thepmap_activate() interface is mandatory.  Needs more thought.

Resident count in pmap is now valid.  I can now see RSS in ps.

Yet more mips1/mips3 merging:

Move mips-specific pmap definitions (PMAP_PREFER for mips3, declaratin
of pmap_bootstrap() for the system-specific machdep.c) from
arch/pmax/include/pmap.h to arch/mips/include/pmap.h.

Add sys_sysarch() calls for the standard mips userspace cache-control calls.

Eliminate vm_pmap.

Add #define __VM_PMAP_HACK as a temporary measure.

Change "pmax_xxx" macros to "mips_xxx" macros, in preparation
for moving to src/sys/arch/mips/include/pmap.h.

Use _KERNEL, not KERNEL

Bring back pmap_kernel(), for now always inlined as a pointer to
kernel_pmap_store.

KERNEL -> _KERNEL

new RCS ID format.

bsd 4.4-lite pmax port as ported to NetBSD

upgrade to bsd 4.4-lite code base. only mod is rcsids

update from rick, tarfile of Oct 11 10:46

pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>

Initial revision