CVS log for src/sys/arch/mips/include/mipsNN.h

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Keyword substitution: kv
Default branch: MAIN

s/Regiser/Register/ and s/regester/register/ in comments.

Fix tyop in __BITS for the MIPSNN_MTI_CFG7_PREF_MASK macro.

Document the PerfCntCrl registers (CP0 Register 25, Selects 0, 2, 4, 6).

Rename MIPSNN_CFG4_MMU_EXT_DEF_MMU_SIZE_EXT to MIPSNN_CFG4_MMU_SIZE_EXT.

Bit definitions Config4 and Config5 registers.

#define<tab>
Nuke trailing whitespace.

Move MIPSNN_CFG3_ULRI so that it doesn't appear in some random position
among the other config3 register definitions.

Use the correct config3 field name (ULRI) for UserLocal register is
implemented bit.

update from HEAD

Sync with HEAD

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Add CFG6/7 definitions for MIPS 24K/74K/34K/1004K/1074K and RMI XLP.

Add support for the MIPS DSP ASE (as a second PCU).

sync with head

sync with head.

Sync with head.

sync with head - hopefully this will work

sync with head.

Merge 2006-03-28 NetBSD-current into the "peter-altq" branch.

Added support for MIPS architecture revision 2.
Added definitions for various rev 2 CP0 configuration register bits.
Added support for MIPS 4KEc Rev 2 (found in Atheros AR2316, for example).

Update to consistently use Broadcom GPL-compatible license on all SiByte code.

Sync with HEAD.

Add the VI bit in config 0.

Catch up to -current.
(CVS: It's not just a program. It's an adventure!)

Catch up with -current.

file mipsNN.h was added on branch nathanw_sa on 2002-04-01 07:40:59 +0000

file mipsNN.h was added on branch kqueue on 2002-03-16 15:58:35 +0000

Values related to the MIPS32/MIPS64 Privileged Resource Architecture
(from Broadcom Corp).