CVS log for src/sys/arch/mips/include/mips3_pte.h

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Keyword substitution: kv
Default branch: MAIN

change #define to #error for MIPS3_4100i 8KB page size build protection.

port crash(8) to mips.  (most of the kernel side.)

- expose parts of _KERNEL to _KMEMUSER as well
- hide more things for _KERNEL
- avoid DB_MACHINE_COMMANDS in crash(8)
- XXX add mips_label_t for !_KERNEL and use it in the pcb to
  avoid conflicting with the ddb/crash one
- enable dumppcb

some changes to make stack trace fail instead of SEGV and
the userland changes to crash itself not part of this change.

#define<tab>
Nuke trailing whitespace.

update from HEAD

Sync with HEAD

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Base various #defines, etc. on PAGE_SHIFT instead of using separate
ENABLE_MIPS_*_PAGE defines.

Add support for 8KB pages.

support BUS_SPACE_MAP_PREFETCH in order to allow mapping device memory and
DMA buffers with cacheing disabled but things like write combining, relaxed
ordering etc. allowed when the CPU supports it
so far enabled only on Loongson, should work on R1xk and probably newer CPUs

Sync with HEAD.

sync with head

Sync with HEAD

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

Sync with HEAD

Remove clause 3 (UCB advertising clause) from the University of Utah
copyright.  Confirmed by Mike Hibler, mike at cs.utah.edu - thanks!
Also, merge UCB and Utah copyright texts back into one, as they
originally were.

Extra verification by snj@.

sync with head

Revamp pmap.  Add exec page caching logic from powerpc oea pmap.  Shrink struct
vm_page by placing the first pv_entry in it.  Remove pv_flags since nothing
really needed it.  Add pmap counters.  Rework virtual cache alias logic.
Allow pmap_copy_page and pmap_zero_page to deal with non-KSEG0 mappable pages.

Revamp things a bit.  Move of the globals mips uses into either cpu_info,
mips_options, or mips_cache_info.  Make MALT64 be able to boot MULTIPROCESSOR.
(some pmap MP work).

Get rid of most of the studly caps.
First to MULTIPROCESSOR support for pmap: move some pmap globals to cpu_info.
Define per-cpu ASID number spaces.
Remove some mips1/!mips1 difference in db_interface.c
Add mips32/64 knowledge to stacktrace.

Add multiple inclusion protection.

Merge from matt-nb5-mips64
Merge mips-specific arch files.

Add and optimize MIPS_PHYS_TO_XKPHYS_{UN,}CACHED(pa).
Treat like mips3_pg_cached: add mips3_xkphys_cached which contains the
starting address of the cached XKPHYS region.  It also respects SPECIAL_CCA.

Add a MIPS3_PG_TO_CCA() macro to get the CCA out of the saved page attributes.

sync with head.

Add 16KB variants of MIPS3_PG_{ODDPG,HVN,SVN}

sync with HEAD

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Sync with HEAD

sync with head.

Sync with HEAD.

add definitions for non-cached pages

sync with head.

merge ktrace-lwp.

Sync with HEAD. Here we go again...

Make MIPS3_PG_SHIFT a variable and initialize it accordingly
in mips_vector_init() if options MIPS3_4100 is specified
so that kernels which have options MIPS3_4100 also work
on other MIPS3 CPUs.

XXX: now should we rename options MIPS3_4100 to options ENABLE_MIPS_R4100,
XXX: or just make MIPS3_PG_SHIFT always a variable?

Add MI mips3 wired map functions based on patch in port-mips/31915
from Garrett D'Amore of Tadpole Computer Inc.
Please refer discussion filed in the PR for details.

Define MIPS3_PG_SIZE_MASK_TO_SIZE() macro in the MI mips header.

Pull up following revision(s) (requested by tsutsui in ticket #5829):
	sys/arch/mips/include/mips3_pte.h: revision 1.17
Add definitions of Vr41xx specific pagemask values.
It supports 1k-256kbytes/page.

Pull up following revision(s) (requested by tsutsui in ticket #758):
	sys/arch/mips/include/mips3_pte.h: revision 1.17
Add definitions of Vr41xx specific pagemask values.
It supports 1k-256kbytes/page.

Add definitions of Vr41xx specific pagemask values.
It supports 1k-256kbytes/page.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

Move UCB-licensed code from 4-clause to 3-clause licence.

Patches provided by Joel Baker in PR 22364, verified by myself.

sync kqueue branch with HEAD

Catch up to -current.

catch up with -current.

Add 64MB and 256MB tlb page masks.

Catch up to -current.
(CVS: It's not just a program. It's an adventure!)

Catch up with -current.

Add support for MIPS32 and MIPS64 architectures:
  Better cache coherency attribute macros (from Broadcom Corp).

Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.

Sync w/ netbsd-1-5-base.

rename
	vad_to_pfn() -> mips_paddr_to_tlbpfn()
	pfn_to_vad() -> mips_tlbpfn_to_paddr()
as suggested by thorpej on port-mips Mar 27.

make paddr_t 64bit on arc port by introducing _MIPS_PADDR_T_64BIT.

Nuke MIPS_16K_PAGE conditional which should be commited in.  It
was used for debugg'n purposes which only make senses on particular
hardware configurations and has never been intended to extend pagesize
of NetBSD/mips.

Changes for NetBSD/hpcmips.

	Support VR4100.
	Support 16KB page.
	Support CPU without FPU.

Fix virtual alias problem(physio() case).

[new options]

options		MIPS3_4100	/* VR4100 core */
options		MIPS_16K_PAGE	/* enable kernel support for 16k pages  */
options		SOFTFLOAT 	/* No FPU; avoid touching FPU registers */

Sync w/ -current.

- Change a symbolic name of TLB entrylo from 'PG_M' to 'PG_D' to reflect
processor design.  MIPS 'dirty bit' is not the same as i386 'dirty bit'.
There is a growing concern of misuse in NetBSD/mips.

Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>.
Adds (most) support for ARC platform to port-independent mips code.

Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by
comparison to the OpenBSD 2.1 codebase of Soda's ARC port.

Open issues:
 * Still no support for r4600 or mipsIV CPUs with two-way L1 cache.
   Code derived from Per Fogelstrom's OpenBSD source  doesn't work
   on mips3 pmaxes with L2 cache.

 * Still some port-specific  #ifdefs, for interrupt enable and
   pmax L2 cache-size.  Needs more thought, but overlaps with
   work-in-progress by Tohru and Tsubai on spl()s and related stuff.

Changes for configuring both MIPS1 and MIPS3, from a merge of
similar design and code by Jason Thorpe and Jonathan Stone.

NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.

mips/include/cpu.h:
    Add CPUISMIPS3 for run-time tests of what CPU architecture level
    we're running on.

mips/include/locore.h:
    Add declarations of locore cache-size variables for ref/def toolchain.

mips/include/mips1_pte.h:
    mips1 TLB bit definitions.

mips/include/mips3_pte.h:
    mips3 TLB bit definitions.

mips/include/pte.h:
    define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
    that expand to CPU constants if only one CPU arch is configured,
    or to inline functions if both MIPS1 and MIPS3 are configured.

mips/mips/locore_r2000.S:
    Use MIPS1_PG_xxx constants inside mips1-specific code.

mips/mips/locore_r4000.S:
    Use MIPS3_PG_xxx constants inside mips3-specific code.

mips/mips/locore.S:
    Use MIPS1_PG_xxx constants inside mips3-specific code.
    Use MIPS1_PG_xxx constants inside mips1-specific code.
    (Needs more  work!)

mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
    Use MIPS3_PG_xxx constants inside mips3-specific functions,
         and MIPS1_PG_XXX inside mips1-specific code.
    Otherwise, use mips_pg_XXX_bit() macros where they apply,
    and use "if (CPUISMIPS3) { ... } else {... }" where they don't.

mips/mips/mips_machdep.c:
    Import Michael Hitch's fixes from the pmax locore-init code
    into mips_vector_init().

pmax/pmax/machdep.c:
    Use generic mips_vector_init() locore vector-init function.

More merged MIPS1/MIPS3 support.  The pte definitions still need work before
they can be support both MIPS1 and MIPS3.

Add (missing) PAGE_IS_RDONLY() macro to test for readonly pages,
in both mips-I and mips-II versions, and use it in arch/mips/mips/trap.c.

Merge mips1 and mips3 pte/pmap code, pass 0;
    * Move mips-I pte (TLBlo) definitions from pmax/include/pte.h
      to mips/include/mips1_pte.h

    * Move mips-III pte (TLBlo) definitions from  pica/include/pte.h
      to mips/include/mips3_pte.h

    * Add new mips/include/pte.h, which includes exactly one of
      mips1_pte.h or mips3_pte.h (which still have namespace collisions),
      depending on "options MIPS1" or "options MIPS3". (hack).
      Move soft kvtopte(), ptetovk() definitions to mips/include/pte.h

    * Add macro PTE_TO_PADDR() to hide the different hardware TLB formats
      when mapping from pte to physical address.

   * Add macro PTE_READONLY() to hide lack of SW read-only bit in mips-III
     tlb. (mips1 pmap uses a sw bit in the PTE, mips3 looks up RO bit in
     the kernel pmap.)

   * Use macros (not direct TLB frobbing) in mips/trap.c, to make it
     mips-1/mips-III indepenndet.

    * Change {pmax,pica}/include/pte.h to just do #include <mips/pte.h>.

* Apply LOCORE -> _LOCORE change so locore.S doesn't #include struct
  definitions.

* Include <mips/cpuregs.h> in <cpu.h> so kern_clock.c has user/kernel
  status bits in scope.  Still needs  work; r2k/r4k previous-mode bits
  are different.

* Include <mips/mips_param.h> in pica/include/param.h, for locore declarations,
  and definitions of vm and  other constants that should be shared across
  NetBSD/mips  systems to esnsure user-level binary compatibility.

RCS id police.

First commit of Per Fogelstrom's port to the Acer pica r4400/isa machine.

Initial revision