CVS log for src/sys/arch/mips/include/intr.h

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Keyword substitution: kv
Default branch: MAIN

Sync with HEAD.

Add no-profiled attribute for splhigh_noprof() and splx_noprof().

Disable __HAVE_PREEMPTION.  It is currently marked

	#if defined(MULTIPROCESSOR) && defined(__HAVE_FAST_SOFTINTS)

but has no chance of working on OCTEON due to at least the spl functions

#define<tab>
Nuke trailing whitespace.

update from HEAD

Sync with HEAD

Add a IPI for watchdogs.

Rework cavium support in preparation for MULTIPROCESSOR support

Rebase to HEAD as of a few days ago.

Rebase.

Implement MI IPI interface with cross-call support.

sync with head

normalise RCSID handling some.

sync to -current

sync to -current

sync to latest -current.

define IPL_SAFEPRI which will be used by kern_synch.c to initialize safepri.

When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses.  There are exceptions.
bus_space_handles are now register_t instead of intptr_t.  This allows them
to contain XKPHYS addresses.  Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address.  This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs.  If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.

Add IST_EDGE_RISING and IST_EDGE_FALLING.

Sync with HEAD.

sync with head

Add an IPI for xcalls.

sync with head

Sync with HEAD

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

- protect option includes ("opt_multiprocessor.h") with #ifdef _KERNEL_OPT

- include opt_multiprocessor.h for MULTIPROCESSOR dependency
- add IPI tag defines for SUSPEND, HALT, and bump NIPIS

Cleanup definition of __HAVE_PREEMPTION

Add a _IPL_NAMES(pfx) which is a list of strings corresponding to the
IPL names.

Add IPL_DDB.  This is needed for watchdog on sbmips and for IPIs used by DDB.
It's above IPL_SCHED but below IPL_HIGH.

Make sure we have a spare cell at the sr_map to make splintr will stop.

- add IPI_AST variant of IPI_NOP to allow seperate event counting

- if __INTR_PRIVATE is not defined, declare (but do not define) struct splsw

s/IPI_ISYNC/IPI_SYNCICACHE/

Split FPU support into separate file and keep internals private to that file.
Make it MPSAFE.  Change interface to be very similar to what's used on other
architectures.
Add l_md.md_fpcpu to mdlwp (needed for MPSAFE)
Move pridtab from <mips/cpu.h> to <mips/locore.h>
Add initial common IPI dispatcher.
Split cpu_* routines from mips_machdep.c into cpu_subr.c
Add cpu_startup_common which has the code replicated in half-dozen
plus machdep.c files.

Now that we use stubs for the spl* calls, we no longer need to export
struct splsw or struct ipl_sr_map to the world.  So we protect those with
__INTR_PRIVATE.

Instead of a read-only ipl_sr_bits, define a ipl_sr_map struct and fill that
in the interrupt init routine.  There's a default ipl_sr_map will operate
correctly, but isn't performant.

Add initial list of IPIs for MIPS SMP.

Add __HAVE_PREEMPTION support for NetBSD/mips.  Kill IPL_PREEMPT since it
isn't needed.

Completely redo how interrupts and SPL are handled in NetBSD/mips.
[XXX locore_mips1.S still needs to adapted.]

Nested interrupts now work.  Except for MIPS_SOFT_MASK and MIPS_SR_INT_IE,
how interrupts work is completely abstracted.  spl is handled through the
mips_splsw table.  Direct manipulation of the status register is no longer
done (except for MIPS_SR_INT_IE).  A new <mips/intr.h> contains the common
IPL/IST/spl* definitions for all ports.

Interrupt delivery is completely different.  Clock interrupts may interrupt
device interrupts.  ci_idepth is now handled by the caller of cpu_intr as
are softints (both can be optimized/simplified in the case of interrupts of
usermode code).  cpu_intr has new arguments and now get called at IPL_HIGH
with MIPS_SR_INT_IE set and its logic is:

void
cpu_intr(int ppl, vaddr_t pc, uint32_t status)
{
	int ipl;
	uint32_t pending;
	while (ppl < (ipl = splintr(&pending))) {
		splx(ipl);		/* enable interrupts */
		<handle pending interrupts>
		(void)splhigh();	/* disable interrupts */
	}
}

mipsX_subr.S has been reworked.  All user handlers (user_intr, systemcall,
user_gen_exception) now use common return to usermode code in lwp_trampoline.
ast() has changed to void ast(void) since the previous pc argument was never
used.

The playstation IPL_ICU_MASK support has been nuked.
MIPS_DYNAMIC_STATUS_MASK may soon be nuked soon.

A bunch of debugging code was left conditionalized by PARANOIA.  If this
code detects a bug, it will enter an infinite loop.  It is expected that
the kernel will be debugged in a simulator or with a hardware debugger so
that the state at that point can be analyzed.

Remove files that are no longer on the trunck

file intr.h was added on branch matt-nb5-mips64 on 2010-02-15 07:36:03 +0000

Introduce cpu_intr() whose body is now provided by target ports in
their own ways.  Ugly fixup #define in machine/intr.h have gone.
mips_hardware_intr global variable patch work has gone.

Don't `extern' function declarations.  While we're there, remove trailing
blank lines and white space.

* Create /sys/arch/mips/include/intr.h, with   extern declaration of
  interrupt-callout vector from mips locore dispatch code to port code.
* Move branch-emulation declaration to mips/include/trap.h.
* Garbage-collect pmax/pmax/trap.h.
  Not needed now pmax/pmax_trap.c is gone, and after above tidy-up.