Annotation of src/sys/arch/mips/include/cpuregs.h, Revision 1.95.8.1
1.95.8.1! pgoyette 1: /* $NetBSD: cpuregs.h,v 1.96 2017/05/07 04:12:35 skrll Exp $ */
1.86 bouyer 2:
3: /*
4: * Copyright (c) 2009 Miodrag Vallat.
5: *
6: * Permission to use, copy, modify, and distribute this software for any
7: * purpose with or without fee is hereby granted, provided that the above
8: * copyright notice and this permission notice appear in all copies.
9: *
10: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17: */
1.4 cgd 18:
1.1 deraadt 19: /*
1.2 glass 20: * Copyright (c) 1992, 1993
21: * The Regents of the University of California. All rights reserved.
1.1 deraadt 22: *
23: * This code is derived from software contributed to Berkeley by
24: * Ralph Campbell and Rick Macklem.
25: *
26: * Redistribution and use in source and binary forms, with or without
27: * modification, are permitted provided that the following conditions
28: * are met:
29: * 1. Redistributions of source code must retain the above copyright
30: * notice, this list of conditions and the following disclaimer.
31: * 2. Redistributions in binary form must reproduce the above copyright
32: * notice, this list of conditions and the following disclaimer in the
33: * documentation and/or other materials provided with the distribution.
1.62 agc 34: * 3. Neither the name of the University nor the names of its contributors
1.1 deraadt 35: * may be used to endorse or promote products derived from this software
36: * without specific prior written permission.
37: *
38: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
39: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
40: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
41: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
42: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
43: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
44: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
45: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
46: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
47: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
48: * SUCH DAMAGE.
49: *
1.22 nisimura 50: * @(#)machConst.h 8.1 (Berkeley) 6/10/93
1.1 deraadt 51: *
52: * machConst.h --
53: *
54: * Machine dependent constants.
55: *
56: * Copyright (C) 1989 Digital Equipment Corporation.
57: * Permission to use, copy, modify, and distribute this software and
58: * its documentation for any purpose and without fee is hereby granted,
59: * provided that the above copyright notice appears in all copies.
60: * Digital Equipment Corporation makes no representations about the
61: * suitability of this software for any purpose. It is provided "as is"
62: * without express or implied warranty.
63: *
64: * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
1.22 nisimura 65: * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
1.1 deraadt 66: * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
1.22 nisimura 67: * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
1.1 deraadt 68: * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
1.2 glass 69: * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
1.1 deraadt 70: */
71:
1.10 jonathan 72: #ifndef _MIPS_CPUREGS_H_
1.49 simonb 73: #define _MIPS_CPUREGS_H_
1.1 deraadt 74:
1.49 simonb 75: #include <sys/cdefs.h> /* For __CONCAT() */
1.58 simonb 76:
77: #if defined(_KERNEL_OPT)
78: #include "opt_cputype.h"
79: #endif
80:
1.13 jonathan 81: /*
82: * Address space.
83: * 32-bit mips CPUS partition their 32-bit address space into four segments:
84: *
85: * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped
86: * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped
87: * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped
88: * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped
89: *
90: * mips1 physical memory is limited to 512Mbytes, which is
91: * doubly mapped in kseg0 (cached) and kseg1 (uncached.)
92: * Caching of mapped addresses is controlled by bits in the TLB entry.
93: */
94:
1.77 matt 95: #ifdef _LP64
96: #define MIPS_XUSEG_START (0L << 62)
97: #define MIPS_XUSEG_P(x) (((uint64_t)(x) >> 62) == 0)
98: #define MIPS_USEG_P(x) ((uintptr_t)(x) < 0x80000000L)
99: #define MIPS_XSSEG_START (1L << 62)
100: #define MIPS_XSSEG_P(x) (((uint64_t)(x) >> 62) == 1)
101: #endif
102:
103: /*
104: * MIPS addresses are signed and we defining as negative so that
105: * in LP64 kern they get sign-extended correctly.
106: */
107: #ifndef _LOCORE
108: #define MIPS_KSEG0_START (-0x7fffffffL-1) /* 0x80000000 */
109: #define MIPS_KSEG1_START -0x60000000L /* 0xa0000000 */
110: #define MIPS_KSEG2_START -0x40000000L /* 0xc0000000 */
111: #define MIPS_MAX_MEM_ADDR -0x42000000L /* 0xbe000000 */
112: #define MIPS_RESERVED_ADDR -0x40380000L /* 0xbfc80000 */
113: #endif
1.49 simonb 114:
115: #define MIPS_PHYS_MASK 0x1fffffff
116:
1.71 matt 117: #define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK)
1.95 matt 118: #define MIPS_PHYS_TO_KSEG0(x) ((intptr_t)((x) + MIPS_KSEG0_START))
1.71 matt 119: #define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK)
1.95 matt 120: #define MIPS_PHYS_TO_KSEG1(x) ((intptr_t)(x) | (intptr_t)MIPS_KSEG1_START)
1.77 matt 121:
122: #define MIPS_KSEG0_P(x) (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG0_START)
123: #define MIPS_KSEG1_P(x) (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG1_START)
124: #define MIPS_KSEG2_P(x) ((uintptr_t)MIPS_KSEG2_START <= (uintptr_t)(x))
1.13 jonathan 125:
126: /* Map virtual address to index in mips3 r4k virtually-indexed cache */
1.49 simonb 127: #define MIPS3_VA_TO_CINDEX(x) \
1.95.8.1! pgoyette 128: (((intptr_t)(x) & 0xffffff) | MIPS_KSEG0_START)
1.5 jonathan 129:
1.77 matt 130: #ifndef _LOCORE
131: #define MIPS_XSEG_MASK (0x3fffffffffffffffLL)
132: #define MIPS_XKSEG_START (0x3ULL << 62)
133: #define MIPS_XKSEG_P(x) (((uint64_t)(x) >> 62) == 3)
134:
135: #define MIPS_XKPHYS_START (0x2ULL << 62)
136: #define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \
137: (MIPS_XKPHYS_START | ((uint64_t)(CCA_UNCACHED) << 59) | (x))
1.87 macallan 138: #define MIPS_PHYS_TO_XKPHYS_ACC(x) \
139: (MIPS_XKPHYS_START | ((uint64_t)(mips_options.mips3_cca_devmem) << 59) | (x))
1.77 matt 140: #define MIPS_PHYS_TO_XKPHYS_CACHED(x) \
1.80 matt 141: (mips_options.mips3_xkphys_cached | (x))
1.49 simonb 142: #define MIPS_PHYS_TO_XKPHYS(cca,x) \
1.77 matt 143: (MIPS_XKPHYS_START | ((uint64_t)(cca) << 59) | (x))
144: #define MIPS_XKPHYS_TO_PHYS(x) ((uint64_t)(x) & 0x07ffffffffffffffLL)
145: #define MIPS_XKPHYS_TO_CCA(x) (((uint64_t)(x) >> 59) & 7)
146: #define MIPS_XKPHYS_P(x) (((uint64_t)(x) >> 62) == 2)
147: #endif /* _LOCORE */
148:
149: #define CCA_UNCACHED 2
150: #define CCA_CACHEABLE 3 /* cacheable non-coherent */
1.87 macallan 151: #define CCA_ACCEL 7 /* non-cached, write combining */
1.49 simonb 152:
1.47 uch 153: /* CPU dependent mtc0 hazard hook */
1.82 matt 154: #if (MIPS32R2 + MIPS64R2) > 0
155: # if (MIPS1 + MIPS3 + MIPS32 + MIPS64) == 0
156: # define COP0_SYNC sll $0,$0,3 /* EHB */
157: # define JR_HB_RA .set push; .set mips32r2; jr.hb ra; nop; .set pop
158: # else
159: # define COP0_SYNC sll $0,$0,1; sll $0,$0,1; sll $0,$0,3
160: # define JR_HB_RA sll $0,$0,1; sll $0,$0,1; jr ra; sll $0,$0,3
161: # endif
162: #elif (MIPS32 + MIPS64) > 0
163: # define COP0_SYNC sll $0,$0,1; sll $0,$0,1; sll $0,$0,1
164: # define JR_HB_RA sll $0,$0,1; sll $0,$0,1; jr ra; sll $0,$0,1
165: #elif MIPS3 > 0
166: # define COP0_SYNC nop; nop; nop
167: # define JR_HB_RA nop; nop; jr ra; nop
168: #else
169: # define COP0_SYNC nop
170: # define JR_HB_RA jr ra; nop
171: #endif
1.58 simonb 172: #define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;
1.5 jonathan 173:
174: /*
1.1 deraadt 175: * The bits in the cause register.
176: *
1.5 jonathan 177: * Bits common to r3000 and r4000:
178: *
1.13 jonathan 179: * MIPS_CR_BR_DELAY Exception happened in branch delay slot.
180: * MIPS_CR_COP_ERR Coprocessor error.
181: * MIPS_CR_IP Interrupt pending bits defined below.
1.5 jonathan 182: * (same meaning as in CAUSE register).
1.13 jonathan 183: * MIPS_CR_EXC_CODE The exception type (see exception codes below).
1.5 jonathan 184: *
185: * Differences:
1.78 snj 186: * r3k has 4 bits of exception type, r4k has 5 bits.
1.1 deraadt 187: */
1.49 simonb 188: #define MIPS_CR_BR_DELAY 0x80000000
189: #define MIPS_CR_COP_ERR 0x30000000
190: #define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */
191: #define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */
192: #define MIPS_CR_IP 0x0000FF00
193: #define MIPS_CR_EXC_CODE_SHIFT 2
1.1 deraadt 194:
195: /*
196: * The bits in the status register. All bits are active when set to 1.
197: *
1.5 jonathan 198: * R3000 status register fields:
1.52 simonb 199: * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors.
200: * MIPS_SR_TS TLB shutdown.
1.5 jonathan 201: *
202: * MIPS_SR_INT_IE Master (current) interrupt enable bit.
203: *
204: * Differences:
205: * r3k has cache control is via frobbing SR register bits, whereas the
206: * r4k cache control is via explicit instructions.
207: * r3k has a 3-entry stack of kernel/user bits, whereas the
208: * r4k has kernel/supervisor/user.
209: */
1.49 simonb 210: #define MIPS_SR_COP_USABILITY 0xf0000000
211: #define MIPS_SR_COP_0_BIT 0x10000000
212: #define MIPS_SR_COP_1_BIT 0x20000000
1.80 matt 213: #define MIPS_SR_COP_2_BIT 0x40000000
1.5 jonathan 214:
215: /* r4k and r3k differences, see below */
216:
1.52 simonb 217: #define MIPS_SR_MX 0x01000000 /* MIPS64 */
218: #define MIPS_SR_PX 0x00800000 /* MIPS64 */
1.51 simonb 219: #define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */
1.52 simonb 220: #define MIPS_SR_TS 0x00200000
1.5 jonathan 221:
222: /* r4k and r3k differences, see below */
223:
1.49 simonb 224: #define MIPS_SR_INT_IE 0x00000001
1.13 jonathan 225: /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
226: /*#define MIPS_SR_INT_MASK 0x0000ff00*/
1.5 jonathan 227:
228:
229: /*
230: * The R2000/R3000-specific status register bit definitions.
231: * all bits are active when set to 1.
232: *
1.13 jonathan 233: * MIPS_SR_PARITY_ERR Parity error.
234: * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss.
235: * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits.
236: * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache.
237: * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory.
1.1 deraadt 238: * Interrupt enable bits defined below.
1.13 jonathan 239: * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode.
240: * MIPS_SR_INT_ENA_OLD Old interrupt enable bit.
241: * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode.
242: * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit.
243: * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode.
1.1 deraadt 244: */
1.5 jonathan 245:
1.49 simonb 246: #define MIPS1_PARITY_ERR 0x00100000
247: #define MIPS1_CACHE_MISS 0x00080000
248: #define MIPS1_PARITY_ZERO 0x00040000
249: #define MIPS1_SWAP_CACHES 0x00020000
250: #define MIPS1_ISOL_CACHES 0x00010000
251:
252: #define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/
253: #define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/
254: #define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/
255: #define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/
256: #define MIPS1_SR_KU_CUR 0x00000002 /* current KU */
1.5 jonathan 257:
258: /* backwards compatibility */
1.49 simonb 259: #define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR
260: #define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS
261: #define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO
262: #define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES
263: #define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES
264:
265: #define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD
266: #define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD
267: #define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV
268: #define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR
269: #define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV
1.5 jonathan 270:
271: /*
272: * R4000 status register bit definitons,
273: * where different from r2000/r3000.
274: */
1.49 simonb 275: #define MIPS3_SR_XX 0x80000000
276: #define MIPS3_SR_RP 0x08000000
1.61 simonb 277: #define MIPS3_SR_FR 0x04000000
1.49 simonb 278: #define MIPS3_SR_RE 0x02000000
279:
280: #define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */
281: #define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */
1.77 matt 282: #define MIPS3_SR_PX 0x00800000 /* MIPS64 */
1.52 simonb 283: #define MIPS3_SR_SR 0x00100000
284: #define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */
1.49 simonb 285: #define MIPS3_SR_DIAG_CH 0x00040000
286: #define MIPS3_SR_DIAG_CE 0x00020000
287: #define MIPS3_SR_DIAG_PE 0x00010000
288: #define MIPS3_SR_KX 0x00000080
289: #define MIPS3_SR_SX 0x00000040
290: #define MIPS3_SR_UX 0x00000020
291: #define MIPS3_SR_KSU_MASK 0x00000018
292: #define MIPS3_SR_KSU_USER 0x00000010
293: #define MIPS3_SR_KSU_SUPER 0x00000008
294: #define MIPS3_SR_KSU_KERNEL 0x00000000
295: #define MIPS3_SR_ERL 0x00000004
296: #define MIPS3_SR_EXL 0x00000002
297:
298: #define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET
299: #define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH
300: #define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE
301: #define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE
302: #define MIPS_SR_KX MIPS3_SR_KX
303: #define MIPS_SR_SX MIPS3_SR_SX
304: #define MIPS_SR_UX MIPS3_SR_UX
305:
306: #define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK
307: #define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER
308: #define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER
309: #define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL
310: #define MIPS_SR_ERL MIPS3_SR_ERL
311: #define MIPS_SR_EXL MIPS3_SR_EXL
1.5 jonathan 312:
1.1 deraadt 313:
314: /*
315: * The interrupt masks.
316: * If a bit in the mask is 1 then the interrupt is enabled (or pending).
317: */
1.49 simonb 318: #define MIPS_INT_MASK 0xff00
319: #define MIPS_INT_MASK_5 0x8000
320: #define MIPS_INT_MASK_4 0x4000
321: #define MIPS_INT_MASK_3 0x2000
322: #define MIPS_INT_MASK_2 0x1000
323: #define MIPS_INT_MASK_1 0x0800
324: #define MIPS_INT_MASK_0 0x0400
325: #define MIPS_HARD_INT_MASK 0xfc00
326: #define MIPS_SOFT_INT_MASK_1 0x0200
327: #define MIPS_SOFT_INT_MASK_0 0x0100
1.80 matt 328: #define MIPS_SOFT_INT_MASK 0x0300
329: #define MIPS_INT_MASK_SHIFT 8
1.6 jonathan 330:
1.11 jonathan 331: /*
1.35 jeffs 332: * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can
333: * choose to enable this interrupt.
1.11 jonathan 334: */
1.35 jeffs 335: #if defined(MIPS3_ENABLE_CLOCK_INTR)
1.49 simonb 336: #define MIPS3_INT_MASK MIPS_INT_MASK
337: #define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK
1.35 jeffs 338: #else
1.49 simonb 339: #define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
340: #define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
1.35 jeffs 341: #endif
1.5 jonathan 342:
1.1 deraadt 343: /*
344: * The bits in the context register.
345: */
1.49 simonb 346: #define MIPS1_CNTXT_PTE_BASE 0xFFE00000
347: #define MIPS1_CNTXT_BAD_VPN 0x001FFFFC
1.5 jonathan 348:
1.49 simonb 349: #define MIPS3_CNTXT_PTE_BASE 0xFF800000
350: #define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0
1.1 deraadt 351:
352: /*
1.15 jonathan 353: * The bits in the MIPS3 config register.
354: *
355: * bit 0..5: R/W, Bit 6..31: R/O
356: */
357:
358: /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
1.49 simonb 359: #define MIPS3_CONFIG_K0_MASK 0x00000007
1.15 jonathan 360:
361: /*
362: * R/W Update on Store Conditional
363: * 0: Store Conditional uses coherency algorithm specified by TLB
364: * 1: Store Conditional uses cacheable coherent update on write
365: */
1.49 simonb 366: #define MIPS3_CONFIG_CU 0x00000008
1.15 jonathan 367:
1.49 simonb 368: #define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */
369: #define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */
370: #define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \
1.17 nisimura 371: (((config) & (bit)) ? 32 : 16)
1.15 jonathan 372:
1.49 simonb 373: #define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
374: #define MIPS3_CONFIG_DC_SHIFT 6
375: #define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
376: #define MIPS3_CONFIG_IC_SHIFT 9
377: #define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
1.66 tsutsui 378:
379: /* Cache size mode indication: available only on Vr41xx CPUs */
380: #define MIPS3_CONFIG_CS 0x00001000
381: #define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */
1.49 simonb 382: #define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \
1.36 chuck 383: ((base) << (((config) & (mask)) >> (shift)))
1.59 rafal 384:
385: /* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */
386: #define MIPS3_CONFIG_SE 0x00001000
1.15 jonathan 387:
388: /* Block ordering: 0: sequential, 1: sub-block */
1.49 simonb 389: #define MIPS3_CONFIG_EB 0x00002000
1.15 jonathan 390:
391: /* ECC mode - 0: ECC mode, 1: parity mode */
1.49 simonb 392: #define MIPS3_CONFIG_EM 0x00004000
1.15 jonathan 393:
394: /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
1.49 simonb 395: #define MIPS3_CONFIG_BE 0x00008000
1.15 jonathan 396:
397: /* Dirty Shared coherency state - 0: enabled, 1: disabled */
1.49 simonb 398: #define MIPS3_CONFIG_SM 0x00010000
1.15 jonathan 399:
400: /* Secondary Cache - 0: present, 1: not present */
1.49 simonb 401: #define MIPS3_CONFIG_SC 0x00020000
1.15 jonathan 402:
1.26 castor 403: /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */
1.49 simonb 404: #define MIPS3_CONFIG_EW_MASK 0x000c0000
405: #define MIPS3_CONFIG_EW_SHIFT 18
1.15 jonathan 406:
407: /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
1.49 simonb 408: #define MIPS3_CONFIG_SW 0x00100000
1.15 jonathan 409:
410: /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
1.49 simonb 411: #define MIPS3_CONFIG_SS 0x00200000
1.15 jonathan 412:
413: /* Secondary Cache line size */
1.49 simonb 414: #define MIPS3_CONFIG_SB_MASK 0x00c00000
415: #define MIPS3_CONFIG_SB_SHIFT 22
416: #define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \
1.15 jonathan 417: (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT))
418:
1.33 soren 419: /* Write back data rate */
1.49 simonb 420: #define MIPS3_CONFIG_EP_MASK 0x0f000000
421: #define MIPS3_CONFIG_EP_SHIFT 24
1.15 jonathan 422:
423: /* System clock ratio - this value is CPU dependent */
1.49 simonb 424: #define MIPS3_CONFIG_EC_MASK 0x70000000
425: #define MIPS3_CONFIG_EC_SHIFT 28
1.15 jonathan 426:
427: /* Master-Checker Mode - 1: enabled */
1.49 simonb 428: #define MIPS3_CONFIG_CM 0x80000000
1.64 tsutsui 429:
430: /*
431: * The bits in the MIPS4 config register.
432: */
433:
434: /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
435: #define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK
436: #define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */
437: #define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */
438: #define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */
439: #define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */
440: #define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */
441: #define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */
442: #define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */
443: #define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */
444: #define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */
445: #define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */
446: #define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */
447: #define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */
448: #define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */
449:
450: #define MIPS4_CONFIG_DC_SHIFT 26
451: #define MIPS4_CONFIG_IC_SHIFT 29
452:
453: #define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \
454: ((base) << (((config) & (mask)) >> (shift)))
455:
456: #define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \
457: (((config) & MIPS4_CONFIG_SB) ? 128 : 64)
1.15 jonathan 458:
459: /*
1.1 deraadt 460: * Location of exception vectors.
1.5 jonathan 461: *
462: * Common vectors: reset and UTLB miss.
1.1 deraadt 463: */
1.77 matt 464: #define MIPS_RESET_EXC_VEC MIPS_PHYS_TO_KSEG1(0x1FC00000)
465: #define MIPS_UTLB_MISS_EXC_VEC MIPS_PHYS_TO_KSEG0(0)
1.49 simonb 466:
467: /*
468: * MIPS-1 general exception vector (everything else)
469: */
1.77 matt 470: #define MIPS1_GEN_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080)
1.49 simonb 471:
472: /*
473: * MIPS-III exception vectors
474: */
1.77 matt 475: #define MIPS3_XTLB_MISS_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080)
476: #define MIPS3_CACHE_ERR_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0100)
477: #define MIPS3_GEN_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0180)
1.5 jonathan 478:
479: /*
1.49 simonb 480: * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
1.5 jonathan 481: */
1.77 matt 482: #define MIPS3_INTR_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0200)
1.5 jonathan 483:
484: /*
1.1 deraadt 485: * Coprocessor 0 registers:
486: *
1.46 simonb 487: * v--- width for mips I,III,32,64
488: * (3=32bit, 6=64bit, i=impl dep)
489: * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index.
490: * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random.
491: * 2 MIPS_COP_0_TLB_LOW 3... r3k TLB entry low.
492: * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low.
493: * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended.
494: * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context.
1.81 matt 495: * 4/2 MIPS_COP_0_USERLOCAL ..36 UserLocal.
1.46 simonb 496: * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register.
1.92 matt 497: * 5/1 MIPS_COP_0_PG_GRAIN ..33 PageGrain register
1.46 simonb 498: * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number.
1.83 matt 499: * 7 MIPS_COP_0_HWRENA ..33 rdHWR Enable.
1.46 simonb 500: * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address.
501: * 9 MIPS_COP_0_COUNT .333 Count register.
502: * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high.
503: * 11 MIPS_COP_0_COMPARE .333 Compare (against Count).
504: * 12 MIPS_COP_0_STATUS 3333 Status register.
1.83 matt 505: * 12/1 MIPS_COP_0_INTCTL ..33 Interrupt Control.
506: * 12/2 MIPS_COP_0_SRSCTL ..33 Shadow Register Set Selectors.
507: * 12/3 MIPS_COP_0_SRSMAP ..33 Shadow Set Map.
1.46 simonb 508: * 13 MIPS_COP_0_CAUSE 3333 Exception cause register.
509: * 14 MIPS_COP_0_EXC_PC 3636 Exception PC.
510: * 15 MIPS_COP_0_PRID 3333 Processor revision identifier.
1.83 matt 511: * 15/1 MIPS_COP_0_EBASE ..33 Exception Base.
1.46 simonb 512: * 16 MIPS_COP_0_CONFIG 3333 Configuration register.
513: * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1.
514: * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2.
515: * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3.
1.92 matt 516: * 16/4 MIPS_COP_0_CONFIG4 ..33 Configuration register 6.
517: * 16/5 MIPS_COP_0_CONFIG5 ..33 Configuration register 7.
1.83 matt 518: * 16/6 MIPS_COP_0_CONFIG6 ..33 Configuration register 6.
1.81 matt 519: * 16/7 MIPS_COP_0_CONFIG7 ..33 Configuration register 7.
1.46 simonb 520: * 17 MIPS_COP_0_LLADDR .336 Load Linked Address.
521: * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register.
522: * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register.
523: * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register.
1.80 matt 524: * 22 MIPS_COP_0_OSSCRATCH ...6 [RMI] OS Scratch register. (select 0..7)
1.84 matt 525: * 22 MIPS_COP_0_DIAG ...6 [LOONGSON2] Diagnostic register.
1.46 simonb 526: * 23 MIPS_COP_0_DEBUG .... Debug JTAG register.
527: * 24 MIPS_COP_0_DEPC .... DEPC JTAG register.
528: * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register.
529: * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register.
530: * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register.
531: * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr).
532: * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr).
533: * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data).
534: * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data).
535: * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr).
536: * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr).
537: * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data).
538: * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data).
539: * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register.
540: * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register.
1.1 deraadt 541: */
1.49 simonb 542: #ifdef _LOCORE
543: #define _(n) __CONCAT($,n)
544: #else
545: #define _(n) n
546: #endif
547: #define MIPS_COP_0_TLB_INDEX _(0)
548: #define MIPS_COP_0_TLB_RANDOM _(1)
1.22 nisimura 549: /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
1.5 jonathan 550:
1.49 simonb 551: #define MIPS_COP_0_TLB_CONTEXT _(4)
1.5 jonathan 552: /* $5 and $6 new with MIPS-III */
1.49 simonb 553: #define MIPS_COP_0_BAD_VADDR _(8)
554: #define MIPS_COP_0_TLB_HI _(10)
555: #define MIPS_COP_0_STATUS _(12)
556: #define MIPS_COP_0_CAUSE _(13)
557: #define MIPS_COP_0_EXC_PC _(14)
558: #define MIPS_COP_0_PRID _(15)
1.1 deraadt 559:
1.5 jonathan 560:
1.18 nisimura 561: /* MIPS-I */
1.49 simonb 562: #define MIPS_COP_0_TLB_LOW _(2)
1.5 jonathan 563:
1.18 nisimura 564: /* MIPS-III */
1.49 simonb 565: #define MIPS_COP_0_TLB_LO0 _(2)
566: #define MIPS_COP_0_TLB_LO1 _(3)
1.5 jonathan 567:
1.49 simonb 568: #define MIPS_COP_0_TLB_PG_MASK _(5)
569: #define MIPS_COP_0_TLB_WIRED _(6)
1.14 jonathan 570:
1.49 simonb 571: #define MIPS_COP_0_COUNT _(9)
572: #define MIPS_COP_0_COMPARE _(11)
1.5 jonathan 573:
1.49 simonb 574: #define MIPS_COP_0_CONFIG _(16)
575: #define MIPS_COP_0_LLADDR _(17)
576: #define MIPS_COP_0_WATCH_LO _(18)
577: #define MIPS_COP_0_WATCH_HI _(19)
578: #define MIPS_COP_0_TLB_XCONTEXT _(20)
579: #define MIPS_COP_0_ECC _(26)
580: #define MIPS_COP_0_CACHE_ERR _(27)
581: #define MIPS_COP_0_TAG_LO _(28)
582: #define MIPS_COP_0_TAG_HI _(29)
583: #define MIPS_COP_0_ERROR_PC _(30)
1.5 jonathan 584:
1.40 simonb 585: /* MIPS32/64 */
1.92 matt 586: #define MIPS_COP_0_CONTEXT _(4)
587: #define MIPS_COP_0_CTXCONFIG _(4), 1
588: #define MIPS_COP_0_USERLOCAL _(4), 2
589: #define MIPS_COP_0_XCTXCONFIG _(4), 3 /* MIPS64 */
590: #define MIPS_COP_0_PGGRAIN _(5), 1
591: #define MIPS_COP_0_SEGCTL0 _(5), 2
592: #define MIPS_COP_0_SEGCTL1 _(5), 3
593: #define MIPS_COP_0_SEGCTL2 _(5), 4
594: #define MIPS_COP_0_PWBASE _(5), 5
595: #define MIPS_COP_0_PWFIELD _(5), 6
596: #define MIPS_COP_0_PWSIZE _(5), 7
597: #define MIPS_COP_0_PWCTL _(6), 6
1.82 matt 598: #define MIPS_COP_0_HWRENA _(7)
1.92 matt 599: #define MIPS_COP_0_BADINSTR _(8), 1
600: #define MIPS_COP_0_BADINSTRP _(8), 2
601: #define MIPS_COP_0_INTCTL _(12), 1
602: #define MIPS_COP_0_SRSCTL _(12), 2
603: #define MIPS_COP_0_SRSMAP _(12), 3
604: #define MIPS_COP_0_NESTEDEXC _(13), 5
605: #define MIPS_COP_0_NESTED_EPC _(14), 2
606: #define MIPS_COP_0_EBASE _(15), 1
607: #define MIPS_COP_0_CDMMBASE _(15), 2
608: #define MIPS_COP_0_CMGCRBASE _(15), 3
609: #define MIPS_COP_0_CONFIG1 _(16), 1
610: #define MIPS_COP_0_CONFIG2 _(16), 2
611: #define MIPS_COP_0_CONFIG3 _(16), 3
612: #define MIPS_COP_0_CONFIG4 _(16), 4
613: #define MIPS_COP_0_CONFIG5 _(16), 5
614: #define MIPS_COP_0_OSSCRATCH _(22) /* RMI */
1.84 matt 615: #define MIPS_COP_0_DIAG _(22)
1.49 simonb 616: #define MIPS_COP_0_DEBUG _(23)
617: #define MIPS_COP_0_DEPC _(24)
618: #define MIPS_COP_0_PERFCNT _(25)
619: #define MIPS_COP_0_DATA_LO _(28)
620: #define MIPS_COP_0_DATA_HI _(29)
621: #define MIPS_COP_0_DESAVE _(31)
1.5 jonathan 622:
1.85 matt 623: #define MIPS_DIAG_RAS_DISABLE 0x00000001 /* Loongson2 */
624: #define MIPS_DIAG_BTB_CLEAR 0x00000002 /* Loongson2 */
625: #define MIPS_DIAG_ITLB_CLEAR 0x00000004 /* Loongson2 */
626:
1.1 deraadt 627: /*
628: * Values for the code field in a break instruction.
629: */
1.49 simonb 630: #define MIPS_BREAK_INSTR 0x0000000d
631: #define MIPS_BREAK_VAL_MASK 0x03ff0000
632: #define MIPS_BREAK_VAL_SHIFT 16
633: #define MIPS_BREAK_KDB_VAL 512
634: #define MIPS_BREAK_SSTEP_VAL 513
635: #define MIPS_BREAK_BRKPT_VAL 514
636: #define MIPS_BREAK_SOVER_VAL 515
637: #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \
1.13 jonathan 638: (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT))
1.49 simonb 639: #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \
1.13 jonathan 640: (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT))
1.49 simonb 641: #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \
1.13 jonathan 642: (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT))
1.49 simonb 643: #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \
1.13 jonathan 644: (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
1.1 deraadt 645:
646: /*
647: * Mininum and maximum cache sizes.
648: */
1.49 simonb 649: #define MIPS_MIN_CACHE_SIZE (16 * 1024)
650: #define MIPS_MAX_CACHE_SIZE (256 * 1024)
651: #define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */
1.1 deraadt 652:
653: /*
654: * The floating point version and status registers.
655: */
1.49 simonb 656: #define MIPS_FPU_ID $0
657: #define MIPS_FPU_CSR $31
1.1 deraadt 658:
659: /*
660: * The floating point coprocessor status register bits.
661: */
1.49 simonb 662: #define MIPS_FPU_ROUNDING_BITS 0x00000003
663: #define MIPS_FPU_ROUND_RN 0x00000000
664: #define MIPS_FPU_ROUND_RZ 0x00000001
665: #define MIPS_FPU_ROUND_RP 0x00000002
666: #define MIPS_FPU_ROUND_RM 0x00000003
667: #define MIPS_FPU_STICKY_BITS 0x0000007c
668: #define MIPS_FPU_STICKY_INEXACT 0x00000004
669: #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008
670: #define MIPS_FPU_STICKY_OVERFLOW 0x00000010
671: #define MIPS_FPU_STICKY_DIV0 0x00000020
672: #define MIPS_FPU_STICKY_INVALID 0x00000040
673: #define MIPS_FPU_ENABLE_BITS 0x00000f80
674: #define MIPS_FPU_ENABLE_INEXACT 0x00000080
675: #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100
676: #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200
677: #define MIPS_FPU_ENABLE_DIV0 0x00000400
678: #define MIPS_FPU_ENABLE_INVALID 0x00000800
679: #define MIPS_FPU_EXCEPTION_BITS 0x0003f000
680: #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000
681: #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000
682: #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000
683: #define MIPS_FPU_EXCEPTION_DIV0 0x00008000
684: #define MIPS_FPU_EXCEPTION_INVALID 0x00010000
685: #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
686: #define MIPS_FPU_COND_BIT 0x00800000
687: #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
688: #define MIPS1_FPC_MBZ_BITS 0xff7c0000
689: #define MIPS3_FPC_MBZ_BITS 0xfe7c0000
1.5 jonathan 690:
1.1 deraadt 691:
692: /*
693: * Constants to determine if have a floating point instruction.
694: */
1.49 simonb 695: #define MIPS_OPCODE_SHIFT 26
696: #define MIPS_OPCODE_C1 0x11
1.1 deraadt 697:
1.5 jonathan 698:
1.1 deraadt 699: /*
700: * The low part of the TLB entry.
701: */
1.49 simonb 702: #define MIPS1_TLB_PFN 0xfffff000
703: #define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800
704: #define MIPS1_TLB_DIRTY_BIT 0x00000400
705: #define MIPS1_TLB_VALID_BIT 0x00000200
706: #define MIPS1_TLB_GLOBAL_BIT 0x00000100
707:
708: #define MIPS3_TLB_PFN 0x3fffffc0
709: #define MIPS3_TLB_ATTR_MASK 0x00000038
710: #define MIPS3_TLB_ATTR_SHIFT 3
711: #define MIPS3_TLB_DIRTY_BIT 0x00000004
712: #define MIPS3_TLB_VALID_BIT 0x00000002
713: #define MIPS3_TLB_GLOBAL_BIT 0x00000001
714:
715: #define MIPS1_TLB_PHYS_PAGE_SHIFT 12
716: #define MIPS3_TLB_PHYS_PAGE_SHIFT 6
717: #define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN
718: #define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN
719: #define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT
720: #define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT
1.22 nisimura 721:
1.15 jonathan 722: /*
1.80 matt 723: * MIPS3_TLB_ATTR (CCA) values - coherency algorithm:
1.15 jonathan 724: * 0: cacheable, noncoherent, write-through, no write allocate
725: * 1: cacheable, noncoherent, write-through, write allocate
726: * 2: uncached
727: * 3: cacheable, noncoherent, write-back (noncoherent)
728: * 4: cacheable, coherent, write-back, exclusive (exclusive)
729: * 5: cacheable, coherent, write-back, exclusive on write (sharable)
730: * 6: cacheable, coherent, write-back, update on write (update)
1.16 jonathan 731: * 7: uncached, accelerated (gather STORE operations)
1.15 jonathan 732: */
1.49 simonb 733: #define MIPS3_TLB_ATTR_WT 0 /* IDT */
734: #define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */
735: #define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */
736: #define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */
737: #define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */
738: #define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */
739: #define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */
740: #define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */
1.15 jonathan 741:
1.1 deraadt 742:
743: /*
744: * The high part of the TLB entry.
745: */
1.49 simonb 746: #define MIPS1_TLB_VPN 0xfffff000
747: #define MIPS1_TLB_PID 0x00000fc0
748: #define MIPS1_TLB_PID_SHIFT 6
749:
750: #define MIPS3_TLB_VPN2 0xffffe000
1.94 matt 751: #define MIPS3_TLB_EHINV 0x00000400 /* mipsNN R3 */
1.49 simonb 752: #define MIPS3_TLB_ASID 0x000000ff
753:
754: #define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN
755: #define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2
756: #define MIPS3_TLB_PID MIPS3_TLB_ASID
757: #define MIPS_TLB_VIRT_PAGE_SHIFT 12
1.5 jonathan 758:
1.1 deraadt 759: /*
1.5 jonathan 760: * r3000: shift count to put the index in the right spot.
1.1 deraadt 761: */
1.49 simonb 762: #define MIPS1_TLB_INDEX_SHIFT 8
1.1 deraadt 763:
764: /*
1.49 simonb 765: * The first TLB that write random hits.
1.1 deraadt 766: */
1.49 simonb 767: #define MIPS1_TLB_FIRST_RAND_ENTRY 8
768: #define MIPS3_TLB_WIRED_UPAGES 1
1.1 deraadt 769:
770: /*
771: * The number of process id entries.
772: */
1.49 simonb 773: #define MIPS1_TLB_NUM_PIDS 64
774: #define MIPS3_TLB_NUM_ASIDS 256
1.11 jonathan 775:
776: /*
1.22 nisimura 777: * Patch codes to hide CPU design differences between MIPS1 and MIPS3.
1.11 jonathan 778: */
1.5 jonathan 779:
1.49 simonb 780: /* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */
781:
1.82 matt 782: #if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0 && MIPS1 != 0
1.49 simonb 783: #define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT
1.80 matt 784: #define MIPS_TLB_PID MIPS1_TLB_PID
1.49 simonb 785: #define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS
1.12 jonathan 786: #endif
1.11 jonathan 787:
1.82 matt 788: #if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) != 0 && MIPS1 == 0
1.49 simonb 789: #define MIPS_TLB_PID_SHIFT 0
1.80 matt 790: #define MIPS_TLB_PID MIPS3_TLB_PID
1.49 simonb 791: #define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS
1.12 jonathan 792: #endif
793:
794:
1.49 simonb 795: #if !defined(MIPS_TLB_PID_SHIFT)
796: #define MIPS_TLB_PID_SHIFT \
797: ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT)
1.12 jonathan 798:
1.80 matt 799: #define MIPS_TLB_PID \
800: ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_PID : MIPS1_TLB_PID)
801:
1.49 simonb 802: #define MIPS_TLB_NUM_PIDS \
803: ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS)
1.8 mhitch 804: #endif
1.1 deraadt 805:
806: /*
1.91 matt 807: * Bits defined for HWREna (CP0 register 7, select 0).
1.82 matt 808: */
809: #define MIPS_HWRENA_IMPL31 __BIT(31)
810: #define MIPS_HWRENA_IMPL30 __BIT(30)
811: #define MIPS_HWRENA_UL __BIT(29) /* Userlocal */
812: #define MIPS_HWRENA_CCRES __BIT(3)
813: #define MIPS_HWRENA_CC __BIT(2)
814: #define MIPS_HWRENA_SYNCI_STEP __BIT(1)
815: #define MIPS_HWRENA_CPUNUM __BIT(0)
816:
817: /*
1.91 matt 818: * Bits defined for EBASE (CP0 register 15, select 1).
819: */
820: #define MIPS_EBASE_CPUNUM __BITS(9, 0)
821:
822: /*
1.80 matt 823: * Hints for the prefetch instruction
824: */
825:
826: /*
827: * Prefetched data is expected to be read (not modified)
828: */
1.95.8.1! pgoyette 829: #define PREF_LOAD 0
1.80 matt 830: #define PREF_LOAD_STREAMED 4 /* but not reused extensively; it */
831: /* "streams" through cache. */
832: #define PREF_LOAD_RETAINED 6 /* and reused extensively; it should */
833: /* be "retained" in the cache. */
834:
835: /*
836: * Prefetched data is expected to be stored or modified
837: */
1.95.8.1! pgoyette 838: #define PREF_STORE 1
1.80 matt 839: #define PREF_STORE_STREAMED 5 /* but not reused extensively; it */
840: /* "streams" through cache. */
841: #define PREF_STORE_RETAINED 7 /* and reused extensively; it should */
842: /* be "retained" in the cache. */
843:
844: /*
845: * data is no longer expected to be used. For a WB cache, schedule a
846: * writeback of any dirty data and afterwards free the cache lines.
847: */
1.95.8.1! pgoyette 848: #define PREF_WB_INV 25
1.80 matt 849: #define PREF_NUDGE PREF_WB_INV
850:
851: /*
852: * Prepare for writing an entire cache line without the overhead
853: * involved in filling the line from memory.
854: */
1.95.8.1! pgoyette 855: #define PREF_PREPAREFORSTORE 30
1.80 matt 856:
857: /*
1.45 simonb 858: * CPU processor revision IDs for company ID == 0 (non mips32/64 chips)
1.18 nisimura 859: */
1.49 simonb 860: #define MIPS_R2000 0x01 /* MIPS R2000 ISA I */
861: #define MIPS_R3000 0x02 /* MIPS R3000 ISA I */
862: #define MIPS_R6000 0x03 /* MIPS R6000 ISA II */
863: #define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */
864: #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */
865: #define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */
866: #define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */
867: #define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */
868: #define MIPS_R4200 0x0a /* NEC VR4200 ISA III */
869: #define MIPS_R4300 0x0b /* NEC VR4300 ISA III */
870: #define MIPS_R4100 0x0c /* NEC VR4100 ISA III */
871: #define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */
872: #define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */
873: #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
874: #define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */
875: #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
876: #define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
877: #define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */
878: #define MIPS_R4650 0x22 /* QED R4650 ISA III */
879: #define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */
880: #define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */
881: #define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */
882: #define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */
883: #define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */
884: #define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */
885: #define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */
886: #define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */
887: #define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */
1.57 nisimura 888: #define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/
1.49 simonb 889: #define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */
1.57 nisimura 890: #define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */
1.76 matt 891: #define MIPS_LOONGSON2 0x63 /* ICT Loongson-2 ISA III */
1.49 simonb 892:
893: /*
894: * CPU revision IDs for some prehistoric processors.
895: */
896:
897: /* For MIPS_R3000 */
1.72 simonb 898: #define MIPS_REV_R2000A 0x16 /* R2000A uses R3000 proc revision */
1.49 simonb 899: #define MIPS_REV_R3000 0x20
900: #define MIPS_REV_R3000A 0x30
901:
902: /* For MIPS_TX3900 */
903: #define MIPS_REV_TX3912 0x10
904: #define MIPS_REV_TX3922 0x30
905: #define MIPS_REV_TX3927 0x40
906:
907: /* For MIPS_R4000 */
908: #define MIPS_REV_R4000_A 0x00
1.63 tsutsui 909: #define MIPS_REV_R4000_B 0x22
910: #define MIPS_REV_R4000_C 0x30
1.49 simonb 911: #define MIPS_REV_R4400_A 0x40
912: #define MIPS_REV_R4400_B 0x50
1.50 simonb 913: #define MIPS_REV_R4400_C 0x60
1.56 simonb 914:
915: /* For MIPS_TX4900 */
916: #define MIPS_REV_TX4927 0x22
1.44 simonb 917:
1.75 matt 918: /* For MIPS_LOONGSON2 */
919: #define MIPS_REV_LOONGSON2E 0x02
920: #define MIPS_REV_LOONGSON2F 0x03
921:
1.44 simonb 922: /*
1.45 simonb 923: * CPU processor revision IDs for company ID == 1 (MIPS)
1.44 simonb 924: */
1.49 simonb 925: #define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */
926: #define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */
1.53 simonb 927: #define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */
1.65 simonb 928: #define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */
1.49 simonb 929: #define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */
1.65 simonb 930: #define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */
1.49 simonb 931: #define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */
1.65 simonb 932: #define MIPS_M4K 0x87 /* MIPS M4K ISA 32 Rel 2 */
933: #define MIPS_25Kf 0x88 /* MIPS 25Kf ISA 64 */
934: #define MIPS_5KE 0x89 /* MIPS 5KE ISA 64 Rel 2 */
935: #define MIPS_4KEc_R2 0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */
936: #define MIPS_4KEmp_R2 0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */
937: #define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */
1.74 simonb 938: #define MIPS_24K 0x93 /* MIPS 24Kc/24Kf ISA 32 Rel 2 */
939: #define MIPS_34K 0x95 /* MIPS 34K ISA 32 R2 MT */
940: #define MIPS_24KE 0x96 /* MIPS 24KEc ISA 32 Rel 2 */
941: #define MIPS_74K 0x97 /* MIPS 74Kc/74Kf ISA 32 Rel 2 */
1.82 matt 942: #define MIPS_1004K 0x99 /* MIPS 1004Kc/1004Kf ISA 32 Rel 2 */
1.93 matt 943: #define MIPS_1074K 0x9a /* MIPS 1074Kc/1074Kf ISA 32 Rel 2 */
1.94 matt 944: #define MIPS_interAptiv 0xa1 /* MIPS interAptiv ISA 32 R3 MT */
1.44 simonb 945:
946: /*
1.88 jakllsch 947: * CPU processor revision IDs for company ID == 2 (Broadcom)
948: */
949: #define MIPS_BCM3302 0x90 /* MIPS 4KEc_R2-like? ISA 32 Rel 2 */
950:
951: /*
1.55 simonb 952: * Alchemy (company ID 3) use the processor ID field to donote the CPU core
953: * revision and the company options field do donate the SOC chip type.
1.44 simonb 954: */
1.55 simonb 955: /* CPU processor revision IDs */
956: #define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */
957: #define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */
958: /* CPU company options IDs */
959: #define MIPS_AU1000 0x00
960: #define MIPS_AU1500 0x01
961: #define MIPS_AU1100 0x02
1.69 tron 962: #define MIPS_AU1550 0x03
1.44 simonb 963:
964: /*
1.45 simonb 965: * CPU processor revision IDs for company ID == 4 (SiByte)
1.44 simonb 966: */
1.49 simonb 967: #define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */
968:
969: /*
970: * CPU processor revision IDs for company ID == 5 (SandCraft)
971: */
972: #define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */
1.18 nisimura 973:
974: /*
1.80 matt 975: * CPU revision IDs for company ID == 12 (RMI)
976: * note: unlisted Rev values may indicate pre-production silicon
1.79 pooka 977: */
1.80 matt 978: #define MIPS_XLR_B2 0x04 /* RMI XLR Production Rev B2 */
979: #define MIPS_XLR_C4 0x91 /* RMI XLR Production Rev C4 */
1.79 pooka 980:
981: /*
1.80 matt 982: * CPU processor IDs for company ID == 12 (RMI)
1.77 matt 983: */
1.80 matt 984: #define MIPS_XLR308B 0x06 /* RMI XLR308-B ISA 64 */
985: #define MIPS_XLR508B 0x07 /* RMI XLR508-B ISA 64 */
986: #define MIPS_XLR516B 0x08 /* RMI XLR516-B ISA 64 */
987: #define MIPS_XLR532B 0x09 /* RMI XLR532-B ISA 64 */
988: #define MIPS_XLR716B 0x0a /* RMI XLR716-B ISA 64 */
989: #define MIPS_XLR732B 0x0b /* RMI XLR732-B ISA 64 */
990: #define MIPS_XLR732C 0x00 /* RMI XLR732-C ISA 64 */
991: #define MIPS_XLR716C 0x02 /* RMI XLR716-C ISA 64 */
992: #define MIPS_XLR532C 0x08 /* RMI XLR532-C ISA 64 */
993: #define MIPS_XLR516C 0x0a /* RMI XLR516-C ISA 64 */
994: #define MIPS_XLR508C 0x0b /* RMI XLR508-C ISA 64 */
995: #define MIPS_XLR308C 0x0f /* RMI XLR308-C ISA 64 */
1.77 matt 996: #define MIPS_XLS616 0x40 /* RMI XLS616 ISA 64 */
997: #define MIPS_XLS416 0x44 /* RMI XLS416 ISA 64 */
998: #define MIPS_XLS608 0x4A /* RMI XLS608 ISA 64 */
999: #define MIPS_XLS408 0x4E /* RMI XLS406 ISA 64 */
1000: #define MIPS_XLS404 0x4F /* RMI XLS404 ISA 64 */
1001: #define MIPS_XLS408LITE 0x88 /* RMI XLS408-Lite ISA 64 */
1002: #define MIPS_XLS404LITE 0x8C /* RMI XLS404-Lite ISA 64 */
1003: #define MIPS_XLS208 0x8E /* RMI XLS208 ISA 64 */
1004: #define MIPS_XLS204 0x8F /* RMI XLS204 ISA 64 */
1005: #define MIPS_XLS108 0xCE /* RMI XLS108 ISA 64 */
1006: #define MIPS_XLS104 0xCF /* RMI XLS104 ISA 64 */
1007:
1008: /*
1.90 hikaru 1009: * CPU processor IDs for company ID == 13 (Cavium)
1010: */
1011: #define MIPS_CN38XX 0x00 /* Cavium Octeon CN38XX ISA 64 */
1012: #define MIPS_CN31XX 0x01 /* Cavium Octeon CN31XX ISA 64 */
1013: #define MIPS_CN30XX 0x02 /* Cavium Octeon CN30XX ISA 64 */
1014: #define MIPS_CN58XX 0x03 /* Cavium Octeon CN58XX ISA 64 */
1015: #define MIPS_CN56XX 0x04 /* Cavium Octeon CN56XX ISA 64 */
1016: #define MIPS_CN50XX 0x06 /* Cavium Octeon CN50XX ISA 64 */
1017: #define MIPS_CN52XX 0x07 /* Cavium Octeon CN52XX ISA 64 */
1018: #define MIPS_CN63XX 0x90 /* Cavium Octeon CN63XX ISA 64 */
1019: #define MIPS_CN68XX 0x91 /* Cavium Octeon CN68XX ISA 64 */
1020: #define MIPS_CN66XX 0x92 /* Cavium Octeon CN66XX ISA 64 */
1021: #define MIPS_CN61XX 0x93 /* Cavium Octeon CN61XX ISA 64 */
1022: #define MIPS_CNF71XX 0x94 /* Cavium Octeon CNF71XX ISA 64 */
1023: #define MIPS_CN78XX 0x95 /* Cavium Octeon CN78XX ISA 64 */
1024: #define MIPS_CN70XX 0x96 /* Cavium Octeon CN70XX ISA 64 */
1025:
1026: /*
1.80 matt 1027: * CPU processor revision IDs for company ID == 7 (Microsoft)
1028: */
1029: #define MIPS_eMIPS 0x04 /* MSR's eMIPS */
1030:
1031: /*
1.89 macallan 1032: * CPU processor revision IDs for company ID == e1 (Ingenic)
1033: */
1034: #define MIPS_XBURST 0x02 /* Ingenic XBurst */
1035:
1036: /*
1.18 nisimura 1037: * FPU processor revision ID
1038: */
1.49 simonb 1039: #define MIPS_SOFT 0x00 /* Software emulation ISA I */
1040: #define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */
1041: #define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */
1042: #define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */
1043: #define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */
1044: #define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */
1045: #define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
1046: #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
1.24 uch 1047:
1048: #ifdef ENABLE_MIPS_TX3900
1049: #include <mips/r3900regs.h>
1.47 uch 1050: #endif
1.58 simonb 1051: #ifdef MIPS64_SB1
1052: #include <mips/sb1regs.h>
1.24 uch 1053: #endif
1.77 matt 1054: #if defined(MIPS64_XLP) || defined(MIPS64_XLR) || defined(MIPS64_XLS)
1055: #include <mips/rmi/rmixlreg.h>
1056: #endif
1.1 deraadt 1057:
1.86 bouyer 1058: #ifdef MIPS3_LOONGSON2
1059: /*
1060: * Loongson 2E/2F specific defines
1061: */
1062:
1063: /*
1064: * Address Window registers physical addresses
1065: *
1066: * The Loongson 2F processor has an AXI crossbar with four possible bus
1067: * masters, each one having four programmable address windows.
1068: *
1069: * Each window is defined with three 64-bit registers:
1070: * - a base address register, defining the address in the master address
1071: * space (base register).
1072: * - an address mask register, defining which address bits are valid in this
1073: * window. A given address matches a window if (addr & mask) == base.
1074: * - the location of the window base in the target, as well at the target
1075: * number itself (mmap register). The lower 20 bits of the address are
1076: * forced as zeroes regardless of their value in this register.
1077: * The translated address is thus (addr & ~mask) | (mmap & ~0xfffff).
1078: */
1079:
1080: #define LOONGSON_AWR_BASE_ADDRESS 0x3ff00000ULL
1081:
1082: #define LOONGSON_AWR_BASE(master, window) \
1083: (LOONGSON_AWR_BASE_ADDRESS + (window) * 0x08 + (master) * 0x60 + 0x00)
1084: #define LOONGSON_AWR_SIZE(master, window) \
1085: (LOONGSON_AWR_BASE_ADDRESS + (window) * 0x08 + (master) * 0x60 + 0x20)
1086: #define LOONGSON_AWR_MMAP(master, window) \
1087: (LOONGSON_AWR_BASE_ADDRESS + (window) * 0x08 + (master) * 0x60 + 0x40)
1088:
1089: /*
1090: * Bits in the diagnostic register
1091: */
1092:
1093: #define COP_0_DIAG_ITLB_CLEAR 0x04
1094: #define COP_0_DIAG_BTB_CLEAR 0x02
1095: #define COP_0_DIAG_RAS_DISABLE 0x01
1096:
1097: #endif /* MIPS3_LOONGSON2 */
1098:
1.10 jonathan 1099: #endif /* _MIPS_CPUREGS_H_ */
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