Annotation of src/sys/arch/mips/include/cpuregs.h, Revision 1.74.28.8
1.74.28.8! matt 1: /* $NetBSD: cpuregs.h,v 1.74.28.7 2009/09/07 21:34:47 matt Exp $ */
1.4 cgd 2:
1.1 deraadt 3: /*
1.2 glass 4: * Copyright (c) 1992, 1993
5: * The Regents of the University of California. All rights reserved.
1.1 deraadt 6: *
7: * This code is derived from software contributed to Berkeley by
8: * Ralph Campbell and Rick Macklem.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
1.62 agc 18: * 3. Neither the name of the University nor the names of its contributors
1.1 deraadt 19: * may be used to endorse or promote products derived from this software
20: * without specific prior written permission.
21: *
22: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32: * SUCH DAMAGE.
33: *
1.22 nisimura 34: * @(#)machConst.h 8.1 (Berkeley) 6/10/93
1.1 deraadt 35: *
36: * machConst.h --
37: *
38: * Machine dependent constants.
39: *
40: * Copyright (C) 1989 Digital Equipment Corporation.
41: * Permission to use, copy, modify, and distribute this software and
42: * its documentation for any purpose and without fee is hereby granted,
43: * provided that the above copyright notice appears in all copies.
44: * Digital Equipment Corporation makes no representations about the
45: * suitability of this software for any purpose. It is provided "as is"
46: * without express or implied warranty.
47: *
48: * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
1.22 nisimura 49: * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
1.1 deraadt 50: * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
1.22 nisimura 51: * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
1.1 deraadt 52: * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
1.2 glass 53: * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
1.1 deraadt 54: */
55:
1.10 jonathan 56: #ifndef _MIPS_CPUREGS_H_
1.49 simonb 57: #define _MIPS_CPUREGS_H_
1.1 deraadt 58:
1.49 simonb 59: #include <sys/cdefs.h> /* For __CONCAT() */
1.58 simonb 60:
61: #if defined(_KERNEL_OPT)
62: #include "opt_cputype.h"
63: #endif
64:
1.13 jonathan 65: /*
66: * Address space.
67: * 32-bit mips CPUS partition their 32-bit address space into four segments:
68: *
69: * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped
70: * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped
71: * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped
72: * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped
73: *
74: * mips1 physical memory is limited to 512Mbytes, which is
75: * doubly mapped in kseg0 (cached) and kseg1 (uncached.)
76: * Caching of mapped addresses is controlled by bits in the TLB entry.
77: */
78:
1.74.28.6 matt 79: #ifdef _LP64
80: #define MIPS_XUSEG_START (0L << 62)
81: #define MIPS_XUSEG_P(x) (((uint64_t)(x) >> 62) == 0)
82: #define MIPS_USEG_P(x) ((uintptr_t)(x) < 0x80000000L)
83: #define MIPS_XSSEG_START (1L << 62)
84: #define MIPS_XSSEG_P(x) (((uint64_t)(x) >> 62) == 1)
85: #endif
1.74.28.2 matt 86:
87: /*
88: * MIPS addresses are signed and we defining as negative so that
89: * in LP64 kern they get sign-extended correctly.
90: */
1.74.28.5 matt 91: #ifndef _LOCORE
92: #define MIPS_KSEG0_START (-0x7fffffffL-1) /* 0x80000000 */
93: #define MIPS_KSEG1_START -0x60000000L /* 0xa0000000 */
94: #define MIPS_KSEG2_START -0x40000000L /* 0xc0000000 */
95: #define MIPS_MAX_MEM_ADDR -0x42000000L /* 0xbe000000 */
96: #define MIPS_RESERVED_ADDR -0x40380000L /* 0xbfc80000 */
97: #endif
1.49 simonb 98:
99: #define MIPS_PHYS_MASK 0x1fffffff
100:
1.71 matt 101: #define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK)
1.74.28.2 matt 102: #define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | (intptr_t)MIPS_KSEG0_START)
1.71 matt 103: #define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK)
1.74.28.2 matt 104: #define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | (intptr_t)MIPS_KSEG1_START)
1.13 jonathan 105:
1.74.28.7 matt 106: #define MIPS_KSEG0_P(x) (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG0_START)
107: #define MIPS_KSEG1_P(x) (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG1_START)
1.74.28.6 matt 108: #define MIPS_KSEG2_P(x) ((uintptr_t)MIPS_KSEG2_START <= (uintptr_t)(x))
109:
1.13 jonathan 110: /* Map virtual address to index in mips3 r4k virtually-indexed cache */
1.49 simonb 111: #define MIPS3_VA_TO_CINDEX(x) \
1.74.28.2 matt 112: (((intptr_t)(x) & 0xffffff) | MIPS_KSEG0_START)
1.74.28.6 matt 113:
1.74.28.2 matt 114: #define MIPS_XSEG_MASK (0x3fffffffffffffffLL)
115: #define MIPS_XKSEG_START (0x3ULL << 62)
1.74.28.1 matt 116: #define MIPS_XKSEG_P(x) (((uint64_t)(x) >> 62) == 3)
117:
1.74.28.2 matt 118: #define MIPS_XKPHYS_START (0x2ULL << 62)
1.74.28.8! matt 119: #define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \
! 120: (MIPS_XKPHYS_START | ((uint64_t)(CCA_UNCACHED) << 59) | (x))
! 121: #define MIPS_PHYS_TO_XKPHYS_CACHED(x) \
! 122: (mips3_xkphys_cached | (x))
1.49 simonb 123: #define MIPS_PHYS_TO_XKPHYS(cca,x) \
1.74.28.2 matt 124: (MIPS_XKPHYS_START | ((uint64_t)(cca) << 59) | (x))
1.74.28.8! matt 125: #define MIPS_XKPHYS_TO_PHYS(x) ((uint64_t)(x) & 0x07ffffffffffffffLL)
! 126: #define MIPS_XKPHYS_TO_CCA(x) (((uint64_t)(x) >> 59) & 7)
1.74.28.1 matt 127: #define MIPS_XKPHYS_P(x) (((uint64_t)(x) >> 62) == 2)
1.49 simonb 128:
1.74.28.6 matt 129: #define CCA_UNCACHED 2
130: #define CCA_CACHEABLE 3 /* cacheable non-coherent */
131:
1.47 uch 132: /* CPU dependent mtc0 hazard hook */
1.58 simonb 133: #define COP0_SYNC /* nothing */
134: #define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;
1.5 jonathan 135:
136: /*
1.1 deraadt 137: * The bits in the cause register.
138: *
1.5 jonathan 139: * Bits common to r3000 and r4000:
140: *
1.13 jonathan 141: * MIPS_CR_BR_DELAY Exception happened in branch delay slot.
142: * MIPS_CR_COP_ERR Coprocessor error.
143: * MIPS_CR_IP Interrupt pending bits defined below.
1.5 jonathan 144: * (same meaning as in CAUSE register).
1.13 jonathan 145: * MIPS_CR_EXC_CODE The exception type (see exception codes below).
1.5 jonathan 146: *
147: * Differences:
148: * r3k has 4 bits of execption type, r4k has 5 bits.
1.1 deraadt 149: */
1.49 simonb 150: #define MIPS_CR_BR_DELAY 0x80000000
151: #define MIPS_CR_COP_ERR 0x30000000
152: #define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */
153: #define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */
154: #define MIPS_CR_IP 0x0000FF00
155: #define MIPS_CR_EXC_CODE_SHIFT 2
1.1 deraadt 156:
157: /*
158: * The bits in the status register. All bits are active when set to 1.
159: *
1.5 jonathan 160: * R3000 status register fields:
1.52 simonb 161: * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors.
162: * MIPS_SR_TS TLB shutdown.
1.5 jonathan 163: *
164: * MIPS_SR_INT_IE Master (current) interrupt enable bit.
165: *
166: * Differences:
167: * r3k has cache control is via frobbing SR register bits, whereas the
168: * r4k cache control is via explicit instructions.
169: * r3k has a 3-entry stack of kernel/user bits, whereas the
170: * r4k has kernel/supervisor/user.
171: */
1.49 simonb 172: #define MIPS_SR_COP_USABILITY 0xf0000000
173: #define MIPS_SR_COP_0_BIT 0x10000000
174: #define MIPS_SR_COP_1_BIT 0x20000000
1.5 jonathan 175:
176: /* r4k and r3k differences, see below */
177:
1.52 simonb 178: #define MIPS_SR_MX 0x01000000 /* MIPS64 */
179: #define MIPS_SR_PX 0x00800000 /* MIPS64 */
1.51 simonb 180: #define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */
1.52 simonb 181: #define MIPS_SR_TS 0x00200000
1.5 jonathan 182:
183: /* r4k and r3k differences, see below */
184:
1.49 simonb 185: #define MIPS_SR_INT_IE 0x00000001
1.13 jonathan 186: /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
187: /*#define MIPS_SR_INT_MASK 0x0000ff00*/
1.5 jonathan 188:
189:
190: /*
191: * The R2000/R3000-specific status register bit definitions.
192: * all bits are active when set to 1.
193: *
1.13 jonathan 194: * MIPS_SR_PARITY_ERR Parity error.
195: * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss.
196: * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits.
197: * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache.
198: * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory.
1.1 deraadt 199: * Interrupt enable bits defined below.
1.13 jonathan 200: * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode.
201: * MIPS_SR_INT_ENA_OLD Old interrupt enable bit.
202: * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode.
203: * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit.
204: * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode.
1.1 deraadt 205: */
1.5 jonathan 206:
1.49 simonb 207: #define MIPS1_PARITY_ERR 0x00100000
208: #define MIPS1_CACHE_MISS 0x00080000
209: #define MIPS1_PARITY_ZERO 0x00040000
210: #define MIPS1_SWAP_CACHES 0x00020000
211: #define MIPS1_ISOL_CACHES 0x00010000
212:
213: #define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/
214: #define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/
215: #define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/
216: #define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/
217: #define MIPS1_SR_KU_CUR 0x00000002 /* current KU */
1.5 jonathan 218:
219: /* backwards compatibility */
1.49 simonb 220: #define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR
221: #define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS
222: #define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO
223: #define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES
224: #define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES
225:
226: #define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD
227: #define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD
228: #define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV
229: #define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR
230: #define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV
1.5 jonathan 231:
232: /*
233: * R4000 status register bit definitons,
234: * where different from r2000/r3000.
235: */
1.49 simonb 236: #define MIPS3_SR_XX 0x80000000
237: #define MIPS3_SR_RP 0x08000000
1.61 simonb 238: #define MIPS3_SR_FR 0x04000000
1.49 simonb 239: #define MIPS3_SR_RE 0x02000000
240:
241: #define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */
242: #define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */
1.52 simonb 243: #define MIPS3_SR_SR 0x00100000
244: #define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */
1.49 simonb 245: #define MIPS3_SR_DIAG_CH 0x00040000
246: #define MIPS3_SR_DIAG_CE 0x00020000
247: #define MIPS3_SR_DIAG_PE 0x00010000
1.70 simonb 248: #define MIPS3_SR_EIE 0x00010000 /* TX79/R5900 */
1.49 simonb 249: #define MIPS3_SR_KX 0x00000080
250: #define MIPS3_SR_SX 0x00000040
251: #define MIPS3_SR_UX 0x00000020
252: #define MIPS3_SR_KSU_MASK 0x00000018
253: #define MIPS3_SR_KSU_USER 0x00000010
254: #define MIPS3_SR_KSU_SUPER 0x00000008
255: #define MIPS3_SR_KSU_KERNEL 0x00000000
256: #define MIPS3_SR_ERL 0x00000004
257: #define MIPS3_SR_EXL 0x00000002
258:
259: #ifdef MIPS3_5900
260: #undef MIPS_SR_INT_IE
261: #define MIPS_SR_INT_IE 0x00010001 /* XXX */
262: #endif
263:
264: #define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET
265: #define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH
266: #define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE
267: #define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE
268: #define MIPS_SR_KX MIPS3_SR_KX
269: #define MIPS_SR_SX MIPS3_SR_SX
270: #define MIPS_SR_UX MIPS3_SR_UX
271:
272: #define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK
273: #define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER
274: #define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER
275: #define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL
276: #define MIPS_SR_ERL MIPS3_SR_ERL
277: #define MIPS_SR_EXL MIPS3_SR_EXL
1.5 jonathan 278:
1.1 deraadt 279:
280: /*
281: * The interrupt masks.
282: * If a bit in the mask is 1 then the interrupt is enabled (or pending).
283: */
1.49 simonb 284: #define MIPS_INT_MASK 0xff00
285: #define MIPS_INT_MASK_5 0x8000
286: #define MIPS_INT_MASK_4 0x4000
287: #define MIPS_INT_MASK_3 0x2000
288: #define MIPS_INT_MASK_2 0x1000
289: #define MIPS_INT_MASK_1 0x0800
290: #define MIPS_INT_MASK_0 0x0400
291: #define MIPS_HARD_INT_MASK 0xfc00
292: #define MIPS_SOFT_INT_MASK_1 0x0200
293: #define MIPS_SOFT_INT_MASK_0 0x0100
1.6 jonathan 294:
1.11 jonathan 295: /*
1.35 jeffs 296: * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can
297: * choose to enable this interrupt.
1.11 jonathan 298: */
1.35 jeffs 299: #if defined(MIPS3_ENABLE_CLOCK_INTR)
1.49 simonb 300: #define MIPS3_INT_MASK MIPS_INT_MASK
301: #define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK
1.35 jeffs 302: #else
1.49 simonb 303: #define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
304: #define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
1.35 jeffs 305: #endif
1.5 jonathan 306:
1.1 deraadt 307: /*
308: * The bits in the context register.
309: */
1.49 simonb 310: #define MIPS1_CNTXT_PTE_BASE 0xFFE00000
311: #define MIPS1_CNTXT_BAD_VPN 0x001FFFFC
1.5 jonathan 312:
1.49 simonb 313: #define MIPS3_CNTXT_PTE_BASE 0xFF800000
314: #define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0
1.1 deraadt 315:
316: /*
1.15 jonathan 317: * The bits in the MIPS3 config register.
318: *
319: * bit 0..5: R/W, Bit 6..31: R/O
320: */
321:
322: /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
1.49 simonb 323: #define MIPS3_CONFIG_K0_MASK 0x00000007
1.15 jonathan 324:
325: /*
326: * R/W Update on Store Conditional
327: * 0: Store Conditional uses coherency algorithm specified by TLB
328: * 1: Store Conditional uses cacheable coherent update on write
329: */
1.49 simonb 330: #define MIPS3_CONFIG_CU 0x00000008
1.15 jonathan 331:
1.49 simonb 332: #define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */
333: #define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */
334: #define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \
1.17 nisimura 335: (((config) & (bit)) ? 32 : 16)
1.15 jonathan 336:
1.49 simonb 337: #define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
338: #define MIPS3_CONFIG_DC_SHIFT 6
339: #define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
340: #define MIPS3_CONFIG_IC_SHIFT 9
341: #define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
1.66 tsutsui 342:
343: /* Cache size mode indication: available only on Vr41xx CPUs */
344: #define MIPS3_CONFIG_CS 0x00001000
345: #define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */
1.49 simonb 346: #define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \
1.36 chuck 347: ((base) << (((config) & (mask)) >> (shift)))
1.59 rafal 348:
349: /* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */
350: #define MIPS3_CONFIG_SE 0x00001000
1.15 jonathan 351:
352: /* Block ordering: 0: sequential, 1: sub-block */
1.49 simonb 353: #define MIPS3_CONFIG_EB 0x00002000
1.15 jonathan 354:
355: /* ECC mode - 0: ECC mode, 1: parity mode */
1.49 simonb 356: #define MIPS3_CONFIG_EM 0x00004000
1.15 jonathan 357:
358: /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
1.49 simonb 359: #define MIPS3_CONFIG_BE 0x00008000
1.15 jonathan 360:
361: /* Dirty Shared coherency state - 0: enabled, 1: disabled */
1.49 simonb 362: #define MIPS3_CONFIG_SM 0x00010000
1.15 jonathan 363:
364: /* Secondary Cache - 0: present, 1: not present */
1.49 simonb 365: #define MIPS3_CONFIG_SC 0x00020000
1.15 jonathan 366:
1.26 castor 367: /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */
1.49 simonb 368: #define MIPS3_CONFIG_EW_MASK 0x000c0000
369: #define MIPS3_CONFIG_EW_SHIFT 18
1.15 jonathan 370:
371: /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
1.49 simonb 372: #define MIPS3_CONFIG_SW 0x00100000
1.15 jonathan 373:
374: /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
1.49 simonb 375: #define MIPS3_CONFIG_SS 0x00200000
1.15 jonathan 376:
377: /* Secondary Cache line size */
1.49 simonb 378: #define MIPS3_CONFIG_SB_MASK 0x00c00000
379: #define MIPS3_CONFIG_SB_SHIFT 22
380: #define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \
1.15 jonathan 381: (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT))
382:
1.33 soren 383: /* Write back data rate */
1.49 simonb 384: #define MIPS3_CONFIG_EP_MASK 0x0f000000
385: #define MIPS3_CONFIG_EP_SHIFT 24
1.15 jonathan 386:
387: /* System clock ratio - this value is CPU dependent */
1.49 simonb 388: #define MIPS3_CONFIG_EC_MASK 0x70000000
389: #define MIPS3_CONFIG_EC_SHIFT 28
1.15 jonathan 390:
391: /* Master-Checker Mode - 1: enabled */
1.49 simonb 392: #define MIPS3_CONFIG_CM 0x80000000
1.64 tsutsui 393:
394: /*
395: * The bits in the MIPS4 config register.
396: */
397:
398: /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
399: #define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK
400: #define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */
401: #define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */
402: #define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */
403: #define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */
404: #define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */
405: #define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */
406: #define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */
407: #define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */
408: #define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */
409: #define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */
410: #define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */
411: #define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */
412: #define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */
413:
414: #define MIPS4_CONFIG_DC_SHIFT 26
415: #define MIPS4_CONFIG_IC_SHIFT 29
416:
417: #define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \
418: ((base) << (((config) & (mask)) >> (shift)))
419:
420: #define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \
421: (((config) & MIPS4_CONFIG_SB) ? 128 : 64)
1.15 jonathan 422:
423: /*
1.1 deraadt 424: * Location of exception vectors.
1.5 jonathan 425: *
426: * Common vectors: reset and UTLB miss.
1.1 deraadt 427: */
1.74.28.2 matt 428: #define MIPS_RESET_EXC_VEC MIPS_PHYS_TO_KSEG1(0x1FC00000)
429: #define MIPS_UTLB_MISS_EXC_VEC MIPS_PHYS_TO_KSEG0(0)
1.49 simonb 430:
431: /*
432: * MIPS-1 general exception vector (everything else)
433: */
1.74.28.2 matt 434: #define MIPS1_GEN_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080)
1.49 simonb 435:
436: /*
437: * MIPS-III exception vectors
438: */
1.74.28.2 matt 439: #define MIPS3_XTLB_MISS_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080)
440: #define MIPS3_CACHE_ERR_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0100)
441: #define MIPS3_GEN_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0180)
1.5 jonathan 442:
443: /*
1.49 simonb 444: * TX79 (R5900) exception vectors
1.5 jonathan 445: */
1.74.28.2 matt 446: #define MIPS_R5900_COUNTER_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080)
447: #define MIPS_R5900_DEBUG_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0100)
1.5 jonathan 448:
449: /*
1.49 simonb 450: * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
1.5 jonathan 451: */
1.74.28.2 matt 452: #define MIPS3_INTR_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0200)
1.5 jonathan 453:
454: /*
1.1 deraadt 455: * Coprocessor 0 registers:
456: *
1.46 simonb 457: * v--- width for mips I,III,32,64
458: * (3=32bit, 6=64bit, i=impl dep)
459: * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index.
460: * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random.
461: * 2 MIPS_COP_0_TLB_LOW 3... r3k TLB entry low.
462: * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low.
463: * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended.
464: * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context.
465: * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register.
466: * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number.
467: * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address.
468: * 9 MIPS_COP_0_COUNT .333 Count register.
469: * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high.
470: * 11 MIPS_COP_0_COMPARE .333 Compare (against Count).
471: * 12 MIPS_COP_0_STATUS 3333 Status register.
472: * 13 MIPS_COP_0_CAUSE 3333 Exception cause register.
473: * 14 MIPS_COP_0_EXC_PC 3636 Exception PC.
474: * 15 MIPS_COP_0_PRID 3333 Processor revision identifier.
1.74.28.4 simonb 475: * 15/1 MIPS_COP_0_EBASE ..33 Exception Base
1.46 simonb 476: * 16 MIPS_COP_0_CONFIG 3333 Configuration register.
477: * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1.
478: * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2.
479: * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3.
480: * 17 MIPS_COP_0_LLADDR .336 Load Linked Address.
481: * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register.
482: * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register.
483: * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register.
484: * 23 MIPS_COP_0_DEBUG .... Debug JTAG register.
485: * 24 MIPS_COP_0_DEPC .... DEPC JTAG register.
486: * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register.
487: * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register.
488: * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register.
489: * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr).
490: * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr).
491: * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data).
492: * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data).
493: * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr).
494: * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr).
495: * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data).
496: * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data).
497: * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register.
498: * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register.
1.1 deraadt 499: */
1.49 simonb 500: #ifdef _LOCORE
501: #define _(n) __CONCAT($,n)
502: #else
503: #define _(n) n
504: #endif
505: #define MIPS_COP_0_TLB_INDEX _(0)
506: #define MIPS_COP_0_TLB_RANDOM _(1)
1.22 nisimura 507: /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
1.5 jonathan 508:
1.49 simonb 509: #define MIPS_COP_0_TLB_CONTEXT _(4)
1.5 jonathan 510: /* $5 and $6 new with MIPS-III */
1.49 simonb 511: #define MIPS_COP_0_BAD_VADDR _(8)
512: #define MIPS_COP_0_TLB_HI _(10)
513: #define MIPS_COP_0_STATUS _(12)
514: #define MIPS_COP_0_CAUSE _(13)
515: #define MIPS_COP_0_EXC_PC _(14)
516: #define MIPS_COP_0_PRID _(15)
1.1 deraadt 517:
1.5 jonathan 518:
1.18 nisimura 519: /* MIPS-I */
1.49 simonb 520: #define MIPS_COP_0_TLB_LOW _(2)
1.5 jonathan 521:
1.18 nisimura 522: /* MIPS-III */
1.49 simonb 523: #define MIPS_COP_0_TLB_LO0 _(2)
524: #define MIPS_COP_0_TLB_LO1 _(3)
1.5 jonathan 525:
1.49 simonb 526: #define MIPS_COP_0_TLB_PG_MASK _(5)
527: #define MIPS_COP_0_TLB_WIRED _(6)
1.14 jonathan 528:
1.49 simonb 529: #define MIPS_COP_0_COUNT _(9)
530: #define MIPS_COP_0_COMPARE _(11)
1.5 jonathan 531:
1.49 simonb 532: #define MIPS_COP_0_CONFIG _(16)
533: #define MIPS_COP_0_LLADDR _(17)
534: #define MIPS_COP_0_WATCH_LO _(18)
535: #define MIPS_COP_0_WATCH_HI _(19)
536: #define MIPS_COP_0_TLB_XCONTEXT _(20)
537: #define MIPS_COP_0_ECC _(26)
538: #define MIPS_COP_0_CACHE_ERR _(27)
539: #define MIPS_COP_0_TAG_LO _(28)
540: #define MIPS_COP_0_TAG_HI _(29)
541: #define MIPS_COP_0_ERROR_PC _(30)
1.5 jonathan 542:
1.40 simonb 543: /* MIPS32/64 */
1.49 simonb 544: #define MIPS_COP_0_DEBUG _(23)
545: #define MIPS_COP_0_DEPC _(24)
546: #define MIPS_COP_0_PERFCNT _(25)
547: #define MIPS_COP_0_DATA_LO _(28)
548: #define MIPS_COP_0_DATA_HI _(29)
549: #define MIPS_COP_0_DESAVE _(31)
1.5 jonathan 550:
1.1 deraadt 551: /*
552: * Values for the code field in a break instruction.
553: */
1.49 simonb 554: #define MIPS_BREAK_INSTR 0x0000000d
555: #define MIPS_BREAK_VAL_MASK 0x03ff0000
556: #define MIPS_BREAK_VAL_SHIFT 16
557: #define MIPS_BREAK_KDB_VAL 512
558: #define MIPS_BREAK_SSTEP_VAL 513
559: #define MIPS_BREAK_BRKPT_VAL 514
560: #define MIPS_BREAK_SOVER_VAL 515
561: #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \
1.13 jonathan 562: (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT))
1.49 simonb 563: #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \
1.13 jonathan 564: (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT))
1.49 simonb 565: #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \
1.13 jonathan 566: (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT))
1.49 simonb 567: #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \
1.13 jonathan 568: (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
1.1 deraadt 569:
570: /*
571: * Mininum and maximum cache sizes.
572: */
1.49 simonb 573: #define MIPS_MIN_CACHE_SIZE (16 * 1024)
574: #define MIPS_MAX_CACHE_SIZE (256 * 1024)
575: #define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */
1.1 deraadt 576:
577: /*
578: * The floating point version and status registers.
579: */
1.49 simonb 580: #define MIPS_FPU_ID $0
581: #define MIPS_FPU_CSR $31
1.1 deraadt 582:
583: /*
584: * The floating point coprocessor status register bits.
585: */
1.49 simonb 586: #define MIPS_FPU_ROUNDING_BITS 0x00000003
587: #define MIPS_FPU_ROUND_RN 0x00000000
588: #define MIPS_FPU_ROUND_RZ 0x00000001
589: #define MIPS_FPU_ROUND_RP 0x00000002
590: #define MIPS_FPU_ROUND_RM 0x00000003
591: #define MIPS_FPU_STICKY_BITS 0x0000007c
592: #define MIPS_FPU_STICKY_INEXACT 0x00000004
593: #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008
594: #define MIPS_FPU_STICKY_OVERFLOW 0x00000010
595: #define MIPS_FPU_STICKY_DIV0 0x00000020
596: #define MIPS_FPU_STICKY_INVALID 0x00000040
597: #define MIPS_FPU_ENABLE_BITS 0x00000f80
598: #define MIPS_FPU_ENABLE_INEXACT 0x00000080
599: #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100
600: #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200
601: #define MIPS_FPU_ENABLE_DIV0 0x00000400
602: #define MIPS_FPU_ENABLE_INVALID 0x00000800
603: #define MIPS_FPU_EXCEPTION_BITS 0x0003f000
604: #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000
605: #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000
606: #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000
607: #define MIPS_FPU_EXCEPTION_DIV0 0x00008000
608: #define MIPS_FPU_EXCEPTION_INVALID 0x00010000
609: #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
610: #define MIPS_FPU_COND_BIT 0x00800000
611: #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
612: #define MIPS1_FPC_MBZ_BITS 0xff7c0000
613: #define MIPS3_FPC_MBZ_BITS 0xfe7c0000
1.5 jonathan 614:
1.1 deraadt 615:
616: /*
617: * Constants to determine if have a floating point instruction.
618: */
1.49 simonb 619: #define MIPS_OPCODE_SHIFT 26
620: #define MIPS_OPCODE_C1 0x11
1.1 deraadt 621:
1.5 jonathan 622:
1.1 deraadt 623: /*
624: * The low part of the TLB entry.
625: */
1.49 simonb 626: #define MIPS1_TLB_PFN 0xfffff000
627: #define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800
628: #define MIPS1_TLB_DIRTY_BIT 0x00000400
629: #define MIPS1_TLB_VALID_BIT 0x00000200
630: #define MIPS1_TLB_GLOBAL_BIT 0x00000100
631:
632: #define MIPS3_TLB_PFN 0x3fffffc0
633: #define MIPS3_TLB_ATTR_MASK 0x00000038
634: #define MIPS3_TLB_ATTR_SHIFT 3
635: #define MIPS3_TLB_DIRTY_BIT 0x00000004
636: #define MIPS3_TLB_VALID_BIT 0x00000002
637: #define MIPS3_TLB_GLOBAL_BIT 0x00000001
638:
639: #define MIPS1_TLB_PHYS_PAGE_SHIFT 12
640: #define MIPS3_TLB_PHYS_PAGE_SHIFT 6
641: #define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN
642: #define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN
643: #define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT
644: #define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT
1.22 nisimura 645:
1.15 jonathan 646: /*
647: * MIPS3_TLB_ATTR values - coherency algorithm:
648: * 0: cacheable, noncoherent, write-through, no write allocate
649: * 1: cacheable, noncoherent, write-through, write allocate
650: * 2: uncached
651: * 3: cacheable, noncoherent, write-back (noncoherent)
652: * 4: cacheable, coherent, write-back, exclusive (exclusive)
653: * 5: cacheable, coherent, write-back, exclusive on write (sharable)
654: * 6: cacheable, coherent, write-back, update on write (update)
1.16 jonathan 655: * 7: uncached, accelerated (gather STORE operations)
1.15 jonathan 656: */
1.49 simonb 657: #define MIPS3_TLB_ATTR_WT 0 /* IDT */
658: #define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */
659: #define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */
660: #define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */
661: #define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */
662: #define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */
663: #define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */
664: #define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */
1.15 jonathan 665:
1.1 deraadt 666:
667: /*
668: * The high part of the TLB entry.
669: */
1.49 simonb 670: #define MIPS1_TLB_VPN 0xfffff000
671: #define MIPS1_TLB_PID 0x00000fc0
672: #define MIPS1_TLB_PID_SHIFT 6
673:
674: #define MIPS3_TLB_VPN2 0xffffe000
675: #define MIPS3_TLB_ASID 0x000000ff
676:
677: #define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN
678: #define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2
679: #define MIPS3_TLB_PID MIPS3_TLB_ASID
680: #define MIPS_TLB_VIRT_PAGE_SHIFT 12
1.5 jonathan 681:
1.1 deraadt 682: /*
1.5 jonathan 683: * r3000: shift count to put the index in the right spot.
1.1 deraadt 684: */
1.49 simonb 685: #define MIPS1_TLB_INDEX_SHIFT 8
1.1 deraadt 686:
687: /*
1.49 simonb 688: * The first TLB that write random hits.
1.1 deraadt 689: */
1.49 simonb 690: #define MIPS1_TLB_FIRST_RAND_ENTRY 8
691: #define MIPS3_TLB_WIRED_UPAGES 1
1.1 deraadt 692:
693: /*
694: * The number of process id entries.
695: */
1.49 simonb 696: #define MIPS1_TLB_NUM_PIDS 64
697: #define MIPS3_TLB_NUM_ASIDS 256
1.11 jonathan 698:
699: /*
1.22 nisimura 700: * Patch codes to hide CPU design differences between MIPS1 and MIPS3.
1.11 jonathan 701: */
1.5 jonathan 702:
1.49 simonb 703: /* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */
704:
705: #if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
706: && defined(MIPS1) /* XXX simonb must be neater! */
707: #define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT
708: #define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS
1.12 jonathan 709: #endif
1.11 jonathan 710:
1.49 simonb 711: #if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
712: && !defined(MIPS1) /* XXX simonb must be neater! */
713: #define MIPS_TLB_PID_SHIFT 0
714: #define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS
1.12 jonathan 715: #endif
716:
717:
1.49 simonb 718: #if !defined(MIPS_TLB_PID_SHIFT)
719: #define MIPS_TLB_PID_SHIFT \
720: ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT)
1.12 jonathan 721:
1.49 simonb 722: #define MIPS_TLB_NUM_PIDS \
723: ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS)
1.8 mhitch 724: #endif
1.1 deraadt 725:
726: /*
1.45 simonb 727: * CPU processor revision IDs for company ID == 0 (non mips32/64 chips)
1.18 nisimura 728: */
1.49 simonb 729: #define MIPS_R2000 0x01 /* MIPS R2000 ISA I */
730: #define MIPS_R3000 0x02 /* MIPS R3000 ISA I */
731: #define MIPS_R6000 0x03 /* MIPS R6000 ISA II */
732: #define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */
733: #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */
734: #define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */
735: #define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */
736: #define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */
737: #define MIPS_R4200 0x0a /* NEC VR4200 ISA III */
738: #define MIPS_R4300 0x0b /* NEC VR4300 ISA III */
739: #define MIPS_R4100 0x0c /* NEC VR4100 ISA III */
740: #define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */
741: #define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */
742: #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
743: #define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */
744: #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
745: #define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
746: #define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */
747: #define MIPS_R4650 0x22 /* QED R4650 ISA III */
748: #define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */
749: #define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */
750: #define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */
751: #define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */
752: #define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */
753: #define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */
754: #define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */
755: #define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */
756: #define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */
1.57 nisimura 757: #define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/
1.49 simonb 758: #define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */
1.57 nisimura 759: #define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */
1.49 simonb 760:
761: /*
762: * CPU revision IDs for some prehistoric processors.
763: */
764:
765: /* For MIPS_R3000 */
1.72 simonb 766: #define MIPS_REV_R2000A 0x16 /* R2000A uses R3000 proc revision */
1.49 simonb 767: #define MIPS_REV_R3000 0x20
768: #define MIPS_REV_R3000A 0x30
769:
770: /* For MIPS_TX3900 */
771: #define MIPS_REV_TX3912 0x10
772: #define MIPS_REV_TX3922 0x30
773: #define MIPS_REV_TX3927 0x40
774:
775: /* For MIPS_R4000 */
776: #define MIPS_REV_R4000_A 0x00
1.63 tsutsui 777: #define MIPS_REV_R4000_B 0x22
778: #define MIPS_REV_R4000_C 0x30
1.49 simonb 779: #define MIPS_REV_R4400_A 0x40
780: #define MIPS_REV_R4400_B 0x50
1.50 simonb 781: #define MIPS_REV_R4400_C 0x60
1.56 simonb 782:
783: /* For MIPS_TX4900 */
784: #define MIPS_REV_TX4927 0x22
1.44 simonb 785:
786: /*
1.45 simonb 787: * CPU processor revision IDs for company ID == 1 (MIPS)
1.44 simonb 788: */
1.49 simonb 789: #define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */
790: #define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */
1.53 simonb 791: #define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */
1.65 simonb 792: #define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */
1.49 simonb 793: #define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */
1.65 simonb 794: #define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */
1.49 simonb 795: #define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */
1.65 simonb 796: #define MIPS_M4K 0x87 /* MIPS M4K ISA 32 Rel 2 */
797: #define MIPS_25Kf 0x88 /* MIPS 25Kf ISA 64 */
798: #define MIPS_5KE 0x89 /* MIPS 5KE ISA 64 Rel 2 */
799: #define MIPS_4KEc_R2 0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */
800: #define MIPS_4KEmp_R2 0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */
801: #define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */
1.74 simonb 802: #define MIPS_24K 0x93 /* MIPS 24Kc/24Kf ISA 32 Rel 2 */
803: #define MIPS_34K 0x95 /* MIPS 34K ISA 32 R2 MT */
804: #define MIPS_24KE 0x96 /* MIPS 24KEc ISA 32 Rel 2 */
805: #define MIPS_74K 0x97 /* MIPS 74Kc/74Kf ISA 32 Rel 2 */
1.44 simonb 806:
807: /*
1.55 simonb 808: * Alchemy (company ID 3) use the processor ID field to donote the CPU core
809: * revision and the company options field do donate the SOC chip type.
1.44 simonb 810: */
1.55 simonb 811: /* CPU processor revision IDs */
812: #define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */
813: #define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */
814: /* CPU company options IDs */
815: #define MIPS_AU1000 0x00
816: #define MIPS_AU1500 0x01
817: #define MIPS_AU1100 0x02
1.69 tron 818: #define MIPS_AU1550 0x03
1.44 simonb 819:
820: /*
1.45 simonb 821: * CPU processor revision IDs for company ID == 4 (SiByte)
1.44 simonb 822: */
1.49 simonb 823: #define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */
824:
825: /*
826: * CPU processor revision IDs for company ID == 5 (SandCraft)
827: */
828: #define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */
1.18 nisimura 829:
830: /*
1.74.28.3 matt 831: * CPU processor revision IDs for company ID == 12 (RMI)
832: */
833: #define MIPS_XLR732 0x00 /* RMI XLS732-C ISA 64 */
834: #define MIPS_XLR716 0x02 /* RMI XLS716-C ISA 64 */
835: #define MIPS_XLR532 0x08 /* RMI XLS532-C ISA 64 */
836: #define MIPS_XLR516 0x0a /* RMI XLS516-C ISA 64 */
837: #define MIPS_XLR508 0x0b /* RMI XLS508-C ISA 64 */
838: #define MIPS_XLR308 0x0f /* RMI XLS308-C ISA 64 */
839: #define MIPS_XLS616 0x40 /* RMI XLS616 ISA 64 */
840: #define MIPS_XLS416 0x44 /* RMI XLS416 ISA 64 */
841: #define MIPS_XLS608 0x4A /* RMI XLS608 ISA 64 */
842: #define MIPS_XLS408 0x4E /* RMI XLS406 ISA 64 */
843: #define MIPS_XLS404 0x4F /* RMI XLS404 ISA 64 */
844: #define MIPS_XLS408LITE 0x88 /* RMI XLS408-Lite ISA 64 */
845: #define MIPS_XLS404LITE 0x8C /* RMI XLS404-Lite ISA 64 */
846: #define MIPS_XLS208 0x8E /* RMI XLS208 ISA 64 */
847: #define MIPS_XLS204 0x8F /* RMI XLS204 ISA 64 */
848: #define MIPS_XLS108 0xCE /* RMI XLS108 ISA 64 */
849: #define MIPS_XLS104 0xCF /* RMI XLS104 ISA 64 */
850:
851: /*
1.18 nisimura 852: * FPU processor revision ID
853: */
1.49 simonb 854: #define MIPS_SOFT 0x00 /* Software emulation ISA I */
855: #define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */
856: #define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */
857: #define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */
858: #define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */
859: #define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */
860: #define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
861: #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
1.24 uch 862:
863: #ifdef ENABLE_MIPS_TX3900
864: #include <mips/r3900regs.h>
1.47 uch 865: #endif
866: #ifdef MIPS3_5900
1.49 simonb 867: #include <mips/r5900regs.h>
1.58 simonb 868: #endif
869: #ifdef MIPS64_SB1
870: #include <mips/sb1regs.h>
1.24 uch 871: #endif
1.1 deraadt 872:
1.10 jonathan 873: #endif /* _MIPS_CPUREGS_H_ */
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