Annotation of src/sys/arch/mips/include/cpuregs.h, Revision 1.50.4.3
1.50.4.3! gehenna 1: /* $NetBSD: cpuregs.h,v 1.56 2002/08/28 02:09:29 simonb Exp $ */
1.4 cgd 2:
1.1 deraadt 3: /*
1.2 glass 4: * Copyright (c) 1992, 1993
5: * The Regents of the University of California. All rights reserved.
1.1 deraadt 6: *
7: * This code is derived from software contributed to Berkeley by
8: * Ralph Campbell and Rick Macklem.
9: *
10: * Redistribution and use in source and binary forms, with or without
11: * modification, are permitted provided that the following conditions
12: * are met:
13: * 1. Redistributions of source code must retain the above copyright
14: * notice, this list of conditions and the following disclaimer.
15: * 2. Redistributions in binary form must reproduce the above copyright
16: * notice, this list of conditions and the following disclaimer in the
17: * documentation and/or other materials provided with the distribution.
18: * 3. All advertising materials mentioning features or use of this software
19: * must display the following acknowledgement:
20: * This product includes software developed by the University of
21: * California, Berkeley and its contributors.
22: * 4. Neither the name of the University nor the names of its contributors
23: * may be used to endorse or promote products derived from this software
24: * without specific prior written permission.
25: *
26: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36: * SUCH DAMAGE.
37: *
1.22 nisimura 38: * @(#)machConst.h 8.1 (Berkeley) 6/10/93
1.1 deraadt 39: *
40: * machConst.h --
41: *
42: * Machine dependent constants.
43: *
44: * Copyright (C) 1989 Digital Equipment Corporation.
45: * Permission to use, copy, modify, and distribute this software and
46: * its documentation for any purpose and without fee is hereby granted,
47: * provided that the above copyright notice appears in all copies.
48: * Digital Equipment Corporation makes no representations about the
49: * suitability of this software for any purpose. It is provided "as is"
50: * without express or implied warranty.
51: *
52: * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
1.22 nisimura 53: * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
1.1 deraadt 54: * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
1.22 nisimura 55: * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
1.1 deraadt 56: * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
1.2 glass 57: * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
1.1 deraadt 58: */
59:
1.10 jonathan 60: #ifndef _MIPS_CPUREGS_H_
1.49 simonb 61: #define _MIPS_CPUREGS_H_
1.1 deraadt 62:
1.49 simonb 63: #include <sys/cdefs.h> /* For __CONCAT() */
1.13 jonathan 64: /*
65: * Address space.
66: * 32-bit mips CPUS partition their 32-bit address space into four segments:
67: *
68: * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped
69: * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped
70: * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped
71: * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped
72: *
73: * mips1 physical memory is limited to 512Mbytes, which is
74: * doubly mapped in kseg0 (cached) and kseg1 (uncached.)
75: * Caching of mapped addresses is controlled by bits in the TLB entry.
76: */
77:
1.49 simonb 78: #define MIPS_KUSEG_START 0x0
79: #define MIPS_KSEG0_START 0x80000000
80: #define MIPS_KSEG1_START 0xa0000000
81: #define MIPS_KSEG2_START 0xc0000000
82: #define MIPS_MAX_MEM_ADDR 0xbe000000
83: #define MIPS_RESERVED_ADDR 0xbfc80000
84:
85: #define MIPS_PHYS_MASK 0x1fffffff
86:
87: #define MIPS_KSEG0_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK)
88: #define MIPS_PHYS_TO_KSEG0(x) ((unsigned)(x) | MIPS_KSEG0_START)
89: #define MIPS_KSEG1_TO_PHYS(x) ((unsigned)(x) & MIPS_PHYS_MASK)
90: #define MIPS_PHYS_TO_KSEG1(x) ((unsigned)(x) | MIPS_KSEG1_START)
1.13 jonathan 91:
92: /* Map virtual address to index in mips3 r4k virtually-indexed cache */
1.49 simonb 93: #define MIPS3_VA_TO_CINDEX(x) \
1.13 jonathan 94: ((unsigned)(x) & 0xffffff | MIPS_KSEG0_START)
1.5 jonathan 95:
1.49 simonb 96: #define MIPS_PHYS_TO_XKPHYS(cca,x) \
97: ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
98: #define MIPS_XKPHYS_TO_PHYS(x) ((x) & 0x0effffffffffffffULL)
99:
1.47 uch 100: /* CPU dependent mtc0 hazard hook */
1.49 simonb 101: #define COP0_SYNC /* nothing */
1.5 jonathan 102:
103: /*
1.1 deraadt 104: * The bits in the cause register.
105: *
1.5 jonathan 106: * Bits common to r3000 and r4000:
107: *
1.13 jonathan 108: * MIPS_CR_BR_DELAY Exception happened in branch delay slot.
109: * MIPS_CR_COP_ERR Coprocessor error.
110: * MIPS_CR_IP Interrupt pending bits defined below.
1.5 jonathan 111: * (same meaning as in CAUSE register).
1.13 jonathan 112: * MIPS_CR_EXC_CODE The exception type (see exception codes below).
1.5 jonathan 113: *
114: * Differences:
115: * r3k has 4 bits of execption type, r4k has 5 bits.
1.1 deraadt 116: */
1.49 simonb 117: #define MIPS_CR_BR_DELAY 0x80000000
118: #define MIPS_CR_COP_ERR 0x30000000
119: #define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */
120: #define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */
121: #define MIPS_CR_IP 0x0000FF00
122: #define MIPS_CR_EXC_CODE_SHIFT 2
1.1 deraadt 123:
124: /*
125: * The bits in the status register. All bits are active when set to 1.
126: *
1.5 jonathan 127: * R3000 status register fields:
1.50.4.1 gehenna 128: * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors.
129: * MIPS_SR_TS TLB shutdown.
1.5 jonathan 130: *
131: * MIPS_SR_INT_IE Master (current) interrupt enable bit.
132: *
133: * Differences:
134: * r3k has cache control is via frobbing SR register bits, whereas the
135: * r4k cache control is via explicit instructions.
136: * r3k has a 3-entry stack of kernel/user bits, whereas the
137: * r4k has kernel/supervisor/user.
138: */
1.49 simonb 139: #define MIPS_SR_COP_USABILITY 0xf0000000
140: #define MIPS_SR_COP_0_BIT 0x10000000
141: #define MIPS_SR_COP_1_BIT 0x20000000
1.5 jonathan 142:
143: /* r4k and r3k differences, see below */
144:
1.50.4.1 gehenna 145: #define MIPS_SR_MX 0x01000000 /* MIPS64 */
146: #define MIPS_SR_PX 0x00800000 /* MIPS64 */
147: #define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */
148: #define MIPS_SR_TS 0x00200000
1.5 jonathan 149:
150: /* r4k and r3k differences, see below */
151:
1.49 simonb 152: #define MIPS_SR_INT_IE 0x00000001
1.13 jonathan 153: /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
154: /*#define MIPS_SR_INT_MASK 0x0000ff00*/
1.5 jonathan 155:
156:
157: /*
158: * The R2000/R3000-specific status register bit definitions.
159: * all bits are active when set to 1.
160: *
1.13 jonathan 161: * MIPS_SR_PARITY_ERR Parity error.
162: * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss.
163: * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits.
164: * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache.
165: * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory.
1.1 deraadt 166: * Interrupt enable bits defined below.
1.13 jonathan 167: * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode.
168: * MIPS_SR_INT_ENA_OLD Old interrupt enable bit.
169: * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode.
170: * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit.
171: * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode.
1.1 deraadt 172: */
1.5 jonathan 173:
1.49 simonb 174: #define MIPS1_PARITY_ERR 0x00100000
175: #define MIPS1_CACHE_MISS 0x00080000
176: #define MIPS1_PARITY_ZERO 0x00040000
177: #define MIPS1_SWAP_CACHES 0x00020000
178: #define MIPS1_ISOL_CACHES 0x00010000
179:
180: #define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/
181: #define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/
182: #define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/
183: #define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/
184: #define MIPS1_SR_KU_CUR 0x00000002 /* current KU */
1.5 jonathan 185:
186: /* backwards compatibility */
1.49 simonb 187: #define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR
188: #define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS
189: #define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO
190: #define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES
191: #define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES
192:
193: #define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD
194: #define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD
195: #define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV
196: #define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR
197: #define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV
1.5 jonathan 198:
199: /*
200: * R4000 status register bit definitons,
201: * where different from r2000/r3000.
202: */
1.49 simonb 203: #define MIPS3_SR_XX 0x80000000
204: #define MIPS3_SR_RP 0x08000000
205: #define MIPS3_SR_FR_32 0x04000000
206: #define MIPS3_SR_RE 0x02000000
207:
208: #define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */
209: #define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */
1.50.4.1 gehenna 210: #define MIPS3_SR_SR 0x00100000
1.49 simonb 211: #define MIPS3_SR_EIE 0x00100000 /* TX79/R5900 */
1.50.4.1 gehenna 212: #define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */
1.49 simonb 213: #define MIPS3_SR_DIAG_CH 0x00040000
214: #define MIPS3_SR_DIAG_CE 0x00020000
215: #define MIPS3_SR_DIAG_PE 0x00010000
216: #define MIPS3_SR_KX 0x00000080
217: #define MIPS3_SR_SX 0x00000040
218: #define MIPS3_SR_UX 0x00000020
219: #define MIPS3_SR_KSU_MASK 0x00000018
220: #define MIPS3_SR_KSU_USER 0x00000010
221: #define MIPS3_SR_KSU_SUPER 0x00000008
222: #define MIPS3_SR_KSU_KERNEL 0x00000000
223: #define MIPS3_SR_ERL 0x00000004
224: #define MIPS3_SR_EXL 0x00000002
225:
226: #ifdef MIPS3_5900
227: #undef MIPS_SR_INT_IE
228: #define MIPS_SR_INT_IE 0x00010001 /* XXX */
229: #endif
230:
231: #define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET
232: #define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH
233: #define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE
234: #define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE
235: #define MIPS_SR_KX MIPS3_SR_KX
236: #define MIPS_SR_SX MIPS3_SR_SX
237: #define MIPS_SR_UX MIPS3_SR_UX
238:
239: #define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK
240: #define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER
241: #define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER
242: #define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL
243: #define MIPS_SR_ERL MIPS3_SR_ERL
244: #define MIPS_SR_EXL MIPS3_SR_EXL
1.5 jonathan 245:
1.1 deraadt 246:
247: /*
248: * The interrupt masks.
249: * If a bit in the mask is 1 then the interrupt is enabled (or pending).
250: */
1.49 simonb 251: #define MIPS_INT_MASK 0xff00
252: #define MIPS_INT_MASK_5 0x8000
253: #define MIPS_INT_MASK_4 0x4000
254: #define MIPS_INT_MASK_3 0x2000
255: #define MIPS_INT_MASK_2 0x1000
256: #define MIPS_INT_MASK_1 0x0800
257: #define MIPS_INT_MASK_0 0x0400
258: #define MIPS_HARD_INT_MASK 0xfc00
259: #define MIPS_SOFT_INT_MASK_1 0x0200
260: #define MIPS_SOFT_INT_MASK_0 0x0100
1.6 jonathan 261:
1.11 jonathan 262: /*
1.35 jeffs 263: * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can
264: * choose to enable this interrupt.
1.11 jonathan 265: */
1.35 jeffs 266: #if defined(MIPS3_ENABLE_CLOCK_INTR)
1.49 simonb 267: #define MIPS3_INT_MASK MIPS_INT_MASK
268: #define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK
1.35 jeffs 269: #else
1.49 simonb 270: #define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
271: #define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
1.35 jeffs 272: #endif
1.5 jonathan 273:
1.1 deraadt 274: /*
275: * The bits in the context register.
276: */
1.49 simonb 277: #define MIPS1_CNTXT_PTE_BASE 0xFFE00000
278: #define MIPS1_CNTXT_BAD_VPN 0x001FFFFC
1.5 jonathan 279:
1.49 simonb 280: #define MIPS3_CNTXT_PTE_BASE 0xFF800000
281: #define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0
1.1 deraadt 282:
283: /*
1.15 jonathan 284: * The bits in the MIPS3 config register.
285: *
286: * bit 0..5: R/W, Bit 6..31: R/O
287: */
288:
289: /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
1.49 simonb 290: #define MIPS3_CONFIG_K0_MASK 0x00000007
1.15 jonathan 291:
292: /*
293: * R/W Update on Store Conditional
294: * 0: Store Conditional uses coherency algorithm specified by TLB
295: * 1: Store Conditional uses cacheable coherent update on write
296: */
1.49 simonb 297: #define MIPS3_CONFIG_CU 0x00000008
1.15 jonathan 298:
1.49 simonb 299: #define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */
300: #define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */
301: #define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \
1.17 nisimura 302: (((config) & (bit)) ? 32 : 16)
1.15 jonathan 303:
1.49 simonb 304: #define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
305: #define MIPS3_CONFIG_DC_SHIFT 6
306: #define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
307: #define MIPS3_CONFIG_IC_SHIFT 9
308: #define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
1.23 shin 309: #ifdef MIPS3_4100 /* VR4100 core */
1.36 chuck 310: /* XXXCDC: THIS MIPS3_4100 SPECIAL CASE SHOULD GO AWAY */
1.49 simonb 311: #define MIPS3_CONFIG_CS 0x00001000 /* cache size mode indication*/
312: #define MIPS3_CONFIG_CACHE_SIZE(config, mask, dummy, shift) \
1.23 shin 313: ((((config)&MIPS3_CONFIG_CS)?0x400:0x1000) << (((config) & (mask)) >> (shift)))
314: #else
1.49 simonb 315: #define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \
1.36 chuck 316: ((base) << (((config) & (mask)) >> (shift)))
1.23 shin 317: #endif
1.15 jonathan 318:
319: /* Block ordering: 0: sequential, 1: sub-block */
1.49 simonb 320: #define MIPS3_CONFIG_EB 0x00002000
1.15 jonathan 321:
322: /* ECC mode - 0: ECC mode, 1: parity mode */
1.49 simonb 323: #define MIPS3_CONFIG_EM 0x00004000
1.15 jonathan 324:
325: /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
1.49 simonb 326: #define MIPS3_CONFIG_BE 0x00008000
1.15 jonathan 327:
328: /* Dirty Shared coherency state - 0: enabled, 1: disabled */
1.49 simonb 329: #define MIPS3_CONFIG_SM 0x00010000
1.15 jonathan 330:
331: /* Secondary Cache - 0: present, 1: not present */
1.49 simonb 332: #define MIPS3_CONFIG_SC 0x00020000
1.15 jonathan 333:
1.26 castor 334: /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */
1.49 simonb 335: #define MIPS3_CONFIG_EW_MASK 0x000c0000
336: #define MIPS3_CONFIG_EW_SHIFT 18
1.15 jonathan 337:
338: /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
1.49 simonb 339: #define MIPS3_CONFIG_SW 0x00100000
1.15 jonathan 340:
341: /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
1.49 simonb 342: #define MIPS3_CONFIG_SS 0x00200000
1.15 jonathan 343:
344: /* Secondary Cache line size */
1.49 simonb 345: #define MIPS3_CONFIG_SB_MASK 0x00c00000
346: #define MIPS3_CONFIG_SB_SHIFT 22
347: #define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \
1.15 jonathan 348: (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT))
349:
1.33 soren 350: /* Write back data rate */
1.49 simonb 351: #define MIPS3_CONFIG_EP_MASK 0x0f000000
352: #define MIPS3_CONFIG_EP_SHIFT 24
1.15 jonathan 353:
354: /* System clock ratio - this value is CPU dependent */
1.49 simonb 355: #define MIPS3_CONFIG_EC_MASK 0x70000000
356: #define MIPS3_CONFIG_EC_SHIFT 28
1.15 jonathan 357:
358: /* Master-Checker Mode - 1: enabled */
1.49 simonb 359: #define MIPS3_CONFIG_CM 0x80000000
1.15 jonathan 360:
361: /*
1.1 deraadt 362: * Location of exception vectors.
1.5 jonathan 363: *
364: * Common vectors: reset and UTLB miss.
1.1 deraadt 365: */
1.49 simonb 366: #define MIPS_RESET_EXC_VEC 0xBFC00000
367: #define MIPS_UTLB_MISS_EXC_VEC 0x80000000
368:
369: /*
370: * MIPS-1 general exception vector (everything else)
371: */
372: #define MIPS1_GEN_EXC_VEC 0x80000080
373:
374: /*
375: * MIPS-III exception vectors
376: */
377: #define MIPS3_XTLB_MISS_EXC_VEC 0x80000080
378: #define MIPS3_CACHE_ERR_EXC_VEC 0x80000100
379: #define MIPS3_GEN_EXC_VEC 0x80000180
1.5 jonathan 380:
381: /*
1.49 simonb 382: * TX79 (R5900) exception vectors
1.5 jonathan 383: */
1.49 simonb 384: #define MIPS_R5900_COUNTER_EXC_VEC 0x80000080
385: #define MIPS_R5900_DEBUG_EXC_VEC 0x80000100
1.5 jonathan 386:
387: /*
1.49 simonb 388: * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
1.5 jonathan 389: */
1.49 simonb 390: #define MIPS3_INTR_EXC_VEC 0x80000200
1.5 jonathan 391:
392: /*
1.1 deraadt 393: * Coprocessor 0 registers:
394: *
1.46 simonb 395: * v--- width for mips I,III,32,64
396: * (3=32bit, 6=64bit, i=impl dep)
397: * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index.
398: * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random.
399: * 2 MIPS_COP_0_TLB_LOW 3... r3k TLB entry low.
400: * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low.
401: * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended.
402: * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context.
403: * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register.
404: * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number.
405: * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address.
406: * 9 MIPS_COP_0_COUNT .333 Count register.
407: * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high.
408: * 11 MIPS_COP_0_COMPARE .333 Compare (against Count).
409: * 12 MIPS_COP_0_STATUS 3333 Status register.
410: * 13 MIPS_COP_0_CAUSE 3333 Exception cause register.
411: * 14 MIPS_COP_0_EXC_PC 3636 Exception PC.
412: * 15 MIPS_COP_0_PRID 3333 Processor revision identifier.
413: * 16 MIPS_COP_0_CONFIG 3333 Configuration register.
414: * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1.
415: * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2.
416: * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3.
417: * 17 MIPS_COP_0_LLADDR .336 Load Linked Address.
418: * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register.
419: * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register.
420: * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register.
421: * 23 MIPS_COP_0_DEBUG .... Debug JTAG register.
422: * 24 MIPS_COP_0_DEPC .... DEPC JTAG register.
423: * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register.
424: * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register.
425: * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register.
426: * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr).
427: * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr).
428: * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data).
429: * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data).
430: * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr).
431: * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr).
432: * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data).
433: * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data).
434: * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register.
435: * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register.
1.1 deraadt 436: */
1.49 simonb 437: #ifdef _LOCORE
438: #define _(n) __CONCAT($,n)
439: #else
440: #define _(n) n
441: #endif
442: #define MIPS_COP_0_TLB_INDEX _(0)
443: #define MIPS_COP_0_TLB_RANDOM _(1)
1.22 nisimura 444: /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
1.5 jonathan 445:
1.49 simonb 446: #define MIPS_COP_0_TLB_CONTEXT _(4)
1.5 jonathan 447: /* $5 and $6 new with MIPS-III */
1.49 simonb 448: #define MIPS_COP_0_BAD_VADDR _(8)
449: #define MIPS_COP_0_TLB_HI _(10)
450: #define MIPS_COP_0_STATUS_REG _(12)
451: #define MIPS_COP_0_CAUSE_REG _(13)
452: #define MIPS_COP_0_STATUS _(12)
453: #define MIPS_COP_0_CAUSE _(13)
454: #define MIPS_COP_0_EXC_PC _(14)
455: #define MIPS_COP_0_PRID _(15)
1.1 deraadt 456:
1.5 jonathan 457:
1.18 nisimura 458: /* MIPS-I */
1.49 simonb 459: #define MIPS_COP_0_TLB_LOW _(2)
1.5 jonathan 460:
1.18 nisimura 461: /* MIPS-III */
1.49 simonb 462: #define MIPS_COP_0_TLB_LO0 _(2)
463: #define MIPS_COP_0_TLB_LO1 _(3)
1.5 jonathan 464:
1.49 simonb 465: #define MIPS_COP_0_TLB_PG_MASK _(5)
466: #define MIPS_COP_0_TLB_WIRED _(6)
1.14 jonathan 467:
1.49 simonb 468: #define MIPS_COP_0_COUNT _(9)
469: #define MIPS_COP_0_COMPARE _(11)
1.5 jonathan 470:
1.49 simonb 471: #define MIPS_COP_0_CONFIG _(16)
472: #define MIPS_COP_0_LLADDR _(17)
473: #define MIPS_COP_0_WATCH_LO _(18)
474: #define MIPS_COP_0_WATCH_HI _(19)
475: #define MIPS_COP_0_TLB_XCONTEXT _(20)
476: #define MIPS_COP_0_ECC _(26)
477: #define MIPS_COP_0_CACHE_ERR _(27)
478: #define MIPS_COP_0_TAG_LO _(28)
479: #define MIPS_COP_0_TAG_HI _(29)
480: #define MIPS_COP_0_ERROR_PC _(30)
1.5 jonathan 481:
1.40 simonb 482: /* MIPS32/64 */
1.49 simonb 483: #define MIPS_COP_0_DEBUG _(23)
484: #define MIPS_COP_0_DEPC _(24)
485: #define MIPS_COP_0_PERFCNT _(25)
486: #define MIPS_COP_0_DATA_LO _(28)
487: #define MIPS_COP_0_DATA_HI _(29)
488: #define MIPS_COP_0_DESAVE _(31)
1.5 jonathan 489:
1.1 deraadt 490: /*
491: * Values for the code field in a break instruction.
492: */
1.49 simonb 493: #define MIPS_BREAK_INSTR 0x0000000d
494: #define MIPS_BREAK_VAL_MASK 0x03ff0000
495: #define MIPS_BREAK_VAL_SHIFT 16
496: #define MIPS_BREAK_KDB_VAL 512
497: #define MIPS_BREAK_SSTEP_VAL 513
498: #define MIPS_BREAK_BRKPT_VAL 514
499: #define MIPS_BREAK_SOVER_VAL 515
500: #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \
1.13 jonathan 501: (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT))
1.49 simonb 502: #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \
1.13 jonathan 503: (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT))
1.49 simonb 504: #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \
1.13 jonathan 505: (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT))
1.49 simonb 506: #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \
1.13 jonathan 507: (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
1.1 deraadt 508:
509: /*
510: * Mininum and maximum cache sizes.
511: */
1.49 simonb 512: #define MIPS_MIN_CACHE_SIZE (16 * 1024)
513: #define MIPS_MAX_CACHE_SIZE (256 * 1024)
514: #define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */
1.1 deraadt 515:
516: /*
517: * The floating point version and status registers.
518: */
1.49 simonb 519: #define MIPS_FPU_ID $0
520: #define MIPS_FPU_CSR $31
1.1 deraadt 521:
522: /*
523: * The floating point coprocessor status register bits.
524: */
1.49 simonb 525: #define MIPS_FPU_ROUNDING_BITS 0x00000003
526: #define MIPS_FPU_ROUND_RN 0x00000000
527: #define MIPS_FPU_ROUND_RZ 0x00000001
528: #define MIPS_FPU_ROUND_RP 0x00000002
529: #define MIPS_FPU_ROUND_RM 0x00000003
530: #define MIPS_FPU_STICKY_BITS 0x0000007c
531: #define MIPS_FPU_STICKY_INEXACT 0x00000004
532: #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008
533: #define MIPS_FPU_STICKY_OVERFLOW 0x00000010
534: #define MIPS_FPU_STICKY_DIV0 0x00000020
535: #define MIPS_FPU_STICKY_INVALID 0x00000040
536: #define MIPS_FPU_ENABLE_BITS 0x00000f80
537: #define MIPS_FPU_ENABLE_INEXACT 0x00000080
538: #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100
539: #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200
540: #define MIPS_FPU_ENABLE_DIV0 0x00000400
541: #define MIPS_FPU_ENABLE_INVALID 0x00000800
542: #define MIPS_FPU_EXCEPTION_BITS 0x0003f000
543: #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000
544: #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000
545: #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000
546: #define MIPS_FPU_EXCEPTION_DIV0 0x00008000
547: #define MIPS_FPU_EXCEPTION_INVALID 0x00010000
548: #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
549: #define MIPS_FPU_COND_BIT 0x00800000
550: #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
551: #define MIPS1_FPC_MBZ_BITS 0xff7c0000
552: #define MIPS3_FPC_MBZ_BITS 0xfe7c0000
1.5 jonathan 553:
1.1 deraadt 554:
555: /*
556: * Constants to determine if have a floating point instruction.
557: */
1.49 simonb 558: #define MIPS_OPCODE_SHIFT 26
559: #define MIPS_OPCODE_C1 0x11
1.1 deraadt 560:
1.5 jonathan 561:
1.1 deraadt 562: /*
563: * The low part of the TLB entry.
564: */
1.49 simonb 565: #define MIPS1_TLB_PFN 0xfffff000
566: #define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800
567: #define MIPS1_TLB_DIRTY_BIT 0x00000400
568: #define MIPS1_TLB_VALID_BIT 0x00000200
569: #define MIPS1_TLB_GLOBAL_BIT 0x00000100
570:
571: #define MIPS3_TLB_PFN 0x3fffffc0
572: #define MIPS3_TLB_ATTR_MASK 0x00000038
573: #define MIPS3_TLB_ATTR_SHIFT 3
574: #define MIPS3_TLB_DIRTY_BIT 0x00000004
575: #define MIPS3_TLB_VALID_BIT 0x00000002
576: #define MIPS3_TLB_GLOBAL_BIT 0x00000001
577:
578: #define MIPS1_TLB_PHYS_PAGE_SHIFT 12
579: #define MIPS3_TLB_PHYS_PAGE_SHIFT 6
580: #define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN
581: #define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN
582: #define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT
583: #define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT
1.22 nisimura 584:
1.15 jonathan 585: /*
586: * MIPS3_TLB_ATTR values - coherency algorithm:
587: * 0: cacheable, noncoherent, write-through, no write allocate
588: * 1: cacheable, noncoherent, write-through, write allocate
589: * 2: uncached
590: * 3: cacheable, noncoherent, write-back (noncoherent)
591: * 4: cacheable, coherent, write-back, exclusive (exclusive)
592: * 5: cacheable, coherent, write-back, exclusive on write (sharable)
593: * 6: cacheable, coherent, write-back, update on write (update)
1.16 jonathan 594: * 7: uncached, accelerated (gather STORE operations)
1.15 jonathan 595: */
1.49 simonb 596: #define MIPS3_TLB_ATTR_WT 0 /* IDT */
597: #define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */
598: #define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */
599: #define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */
600: #define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */
601: #define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */
602: #define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */
603: #define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */
1.15 jonathan 604:
1.1 deraadt 605:
606: /*
607: * The high part of the TLB entry.
608: */
1.49 simonb 609: #define MIPS1_TLB_VPN 0xfffff000
610: #define MIPS1_TLB_PID 0x00000fc0
611: #define MIPS1_TLB_PID_SHIFT 6
612:
613: #define MIPS3_TLB_VPN2 0xffffe000
614: #define MIPS3_TLB_ASID 0x000000ff
615:
616: #define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN
617: #define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2
618: #define MIPS3_TLB_PID MIPS3_TLB_ASID
619: #define MIPS_TLB_VIRT_PAGE_SHIFT 12
1.5 jonathan 620:
1.1 deraadt 621: /*
1.5 jonathan 622: * r3000: shift count to put the index in the right spot.
1.1 deraadt 623: */
1.49 simonb 624: #define MIPS1_TLB_INDEX_SHIFT 8
1.1 deraadt 625:
626: /*
1.49 simonb 627: * The first TLB that write random hits.
1.1 deraadt 628: */
1.49 simonb 629: #define MIPS1_TLB_FIRST_RAND_ENTRY 8
630: #define MIPS3_TLB_WIRED_UPAGES 1
1.1 deraadt 631:
632: /*
633: * The number of process id entries.
634: */
1.49 simonb 635: #define MIPS1_TLB_NUM_PIDS 64
636: #define MIPS3_TLB_NUM_ASIDS 256
1.11 jonathan 637:
638: /*
1.22 nisimura 639: * Patch codes to hide CPU design differences between MIPS1 and MIPS3.
1.11 jonathan 640: */
1.5 jonathan 641:
1.49 simonb 642: /* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */
643:
644: #if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
645: && defined(MIPS1) /* XXX simonb must be neater! */
646: #define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT
647: #define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS
1.12 jonathan 648: #endif
1.11 jonathan 649:
1.49 simonb 650: #if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
651: && !defined(MIPS1) /* XXX simonb must be neater! */
652: #define MIPS_TLB_PID_SHIFT 0
653: #define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS
1.12 jonathan 654: #endif
655:
656:
1.49 simonb 657: #if !defined(MIPS_TLB_PID_SHIFT)
658: #define MIPS_TLB_PID_SHIFT \
659: ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT)
1.12 jonathan 660:
1.49 simonb 661: #define MIPS_TLB_NUM_PIDS \
662: ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS)
1.8 mhitch 663: #endif
1.1 deraadt 664:
665: /*
1.45 simonb 666: * CPU processor revision IDs for company ID == 0 (non mips32/64 chips)
1.18 nisimura 667: */
1.49 simonb 668: #define MIPS_R2000 0x01 /* MIPS R2000 ISA I */
669: #define MIPS_R3000 0x02 /* MIPS R3000 ISA I */
670: #define MIPS_R6000 0x03 /* MIPS R6000 ISA II */
671: #define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */
672: #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */
673: #define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */
674: #define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */
675: #define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */
676: #define MIPS_R4200 0x0a /* NEC VR4200 ISA III */
677: #define MIPS_R4300 0x0b /* NEC VR4300 ISA III */
678: #define MIPS_R4100 0x0c /* NEC VR4100 ISA III */
679: #define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */
680: #define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */
681: #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
682: #define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */
683: #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
684: #define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
685: #define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */
686: #define MIPS_R4650 0x22 /* QED R4650 ISA III */
687: #define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */
688: #define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */
689: #define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */
690: #define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */
691: #define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */
692: #define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */
693: #define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */
694: #define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */
695: #define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */
696: #define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */
697:
698: /*
699: * CPU revision IDs for some prehistoric processors.
700: */
701:
702: /* For MIPS_R3000 */
703: #define MIPS_REV_R3000 0x20
704: #define MIPS_REV_R3000A 0x30
705:
706: /* For MIPS_TX3900 */
707: #define MIPS_REV_TX3912 0x10
708: #define MIPS_REV_TX3922 0x30
709: #define MIPS_REV_TX3927 0x40
710:
711: /* For MIPS_R4000 */
712: #define MIPS_REV_R4000_A 0x00
713: #define MIPS_REV_R4000_B 0x30
714: #define MIPS_REV_R4400_A 0x40
715: #define MIPS_REV_R4400_B 0x50
1.50 simonb 716: #define MIPS_REV_R4400_C 0x60
1.44 simonb 717:
1.50.4.3! gehenna 718: /* For MIPS_TX4900 */
! 719: #define MIPS_REV_TX4927 0x22
! 720:
1.44 simonb 721: /*
1.45 simonb 722: * CPU processor revision IDs for company ID == 1 (MIPS)
1.44 simonb 723: */
1.49 simonb 724: #define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */
725: #define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */
1.50.4.2 gehenna 726: #define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */
1.49 simonb 727: #define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */
728: #define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */
1.44 simonb 729:
730: /*
1.50.4.3! gehenna 731: * Alchemy (company ID 3) use the processor ID field to donote the CPU core
! 732: * revision and the company options field do donate the SOC chip type.
1.44 simonb 733: */
1.50.4.3! gehenna 734: /* CPU processor revision IDs */
! 735: #define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */
! 736: #define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */
! 737: /* CPU company options IDs */
! 738: #define MIPS_AU1000 0x00
! 739: #define MIPS_AU1500 0x01
! 740: #define MIPS_AU1100 0x02
1.44 simonb 741:
742: /*
1.45 simonb 743: * CPU processor revision IDs for company ID == 4 (SiByte)
1.44 simonb 744: */
1.49 simonb 745: #define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */
746:
747: /*
748: * CPU processor revision IDs for company ID == 5 (SandCraft)
749: */
750: #define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */
1.18 nisimura 751:
752: /*
753: * FPU processor revision ID
754: */
1.49 simonb 755: #define MIPS_SOFT 0x00 /* Software emulation ISA I */
756: #define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */
757: #define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */
758: #define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */
759: #define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */
760: #define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */
761: #define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
762: #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
1.24 uch 763:
764: #ifdef ENABLE_MIPS_TX3900
765: #include <mips/r3900regs.h>
1.47 uch 766: #endif
767: #ifdef MIPS3_5900
1.49 simonb 768: #include <mips/r5900regs.h>
1.24 uch 769: #endif
1.1 deraadt 770:
1.10 jonathan 771: #endif /* _MIPS_CPUREGS_H_ */
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