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Diff for /src/sys/arch/mips/include/cpuregs.h between version 1.74 and 1.74.28.16

version 1.74, 2008/02/19 11:26:40 version 1.74.28.16, 2010/03/21 18:18:51
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  * Caching of mapped addresses is controlled by bits in the TLB entry.   * Caching of mapped addresses is controlled by bits in the TLB entry.
  */   */
   
 #define MIPS_KUSEG_START                0x0  #ifdef _LP64
 #define MIPS_KSEG0_START                0x80000000  #define MIPS_XUSEG_START                (0L << 62)
 #define MIPS_KSEG1_START                0xa0000000  #define MIPS_XUSEG_P(x)                 (((uint64_t)(x) >> 62) == 0)
 #define MIPS_KSEG2_START                0xc0000000  #define MIPS_USEG_P(x)                  ((uintptr_t)(x) < 0x80000000L)
 #define MIPS_MAX_MEM_ADDR               0xbe000000  #define MIPS_XSSEG_START                (1L << 62)
 #define MIPS_RESERVED_ADDR              0xbfc80000  #define MIPS_XSSEG_P(x)                 (((uint64_t)(x) >> 62) == 1)
   #endif
   
   /*
    * MIPS addresses are signed and we defining as negative so that
    * in LP64 kern they get sign-extended correctly.
    */
   #ifndef _LOCORE
   #define MIPS_KSEG0_START                (-0x7fffffffL-1) /* 0x80000000 */
   #define MIPS_KSEG1_START                -0x60000000L    /* 0xa0000000 */
   #define MIPS_KSEG2_START                -0x40000000L    /* 0xc0000000 */
   #define MIPS_MAX_MEM_ADDR               -0x42000000L    /* 0xbe000000 */
   #define MIPS_RESERVED_ADDR              -0x40380000L    /* 0xbfc80000 */
   #endif
   
 #define MIPS_PHYS_MASK                  0x1fffffff  #define MIPS_PHYS_MASK                  0x1fffffff
   
 #define MIPS_KSEG0_TO_PHYS(x)   ((uintptr_t)(x) & MIPS_PHYS_MASK)  #define MIPS_KSEG0_TO_PHYS(x)   ((uintptr_t)(x) & MIPS_PHYS_MASK)
 #define MIPS_PHYS_TO_KSEG0(x)   ((uintptr_t)(x) | MIPS_KSEG0_START)  #define MIPS_PHYS_TO_KSEG0(x)   ((uintptr_t)(x) | (intptr_t)MIPS_KSEG0_START)
 #define MIPS_KSEG1_TO_PHYS(x)   ((uintptr_t)(x) & MIPS_PHYS_MASK)  #define MIPS_KSEG1_TO_PHYS(x)   ((uintptr_t)(x) & MIPS_PHYS_MASK)
 #define MIPS_PHYS_TO_KSEG1(x)   ((uintptr_t)(x) | MIPS_KSEG1_START)  #define MIPS_PHYS_TO_KSEG1(x)   ((uintptr_t)(x) | (intptr_t)MIPS_KSEG1_START)
   
   #define MIPS_KSEG0_P(x)         (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG0_START)
   #define MIPS_KSEG1_P(x)         (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG1_START)
   #define MIPS_KSEG2_P(x)         ((uintptr_t)MIPS_KSEG2_START <= (uintptr_t)(x))
   
 /* Map virtual address to index in mips3 r4k virtually-indexed cache */  /* Map virtual address to index in mips3 r4k virtually-indexed cache */
 #define MIPS3_VA_TO_CINDEX(x) \  #define MIPS3_VA_TO_CINDEX(x) \
                 ((uintptr_t)(x) & 0xffffff | MIPS_KSEG0_START)                  (((intptr_t)(x) & 0xffffff) | MIPS_KSEG0_START)
   
   #ifndef _LOCORE
   #define MIPS_XSEG_MASK          (0x3fffffffffffffffLL)
   #define MIPS_XKSEG_START        (0x3ULL << 62)
   #define MIPS_XKSEG_P(x)         (((uint64_t)(x) >> 62) == 3)
   
   #define MIPS_XKPHYS_START       (0x2ULL << 62)
   #define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \
           (MIPS_XKPHYS_START | ((uint64_t)(CCA_UNCACHED) << 59) | (x))
   #define MIPS_PHYS_TO_XKPHYS_CACHED(x) \
           (mips_options.mips3_xkphys_cached | (x))
 #define MIPS_PHYS_TO_XKPHYS(cca,x) \  #define MIPS_PHYS_TO_XKPHYS(cca,x) \
         ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))          (MIPS_XKPHYS_START | ((uint64_t)(cca) << 59) | (x))
 #define MIPS_XKPHYS_TO_PHYS(x)  ((x) & 0x0effffffffffffffULL)  #define MIPS_XKPHYS_TO_PHYS(x)  ((uint64_t)(x) & 0x07ffffffffffffffLL)
   #define MIPS_XKPHYS_TO_CCA(x)   (((uint64_t)(x) >> 59) & 7)
   #define MIPS_XKPHYS_P(x)        (((uint64_t)(x) >> 62) == 2)
   #endif  /* _LOCORE */
   
   #define CCA_UNCACHED            2
   #define CCA_CACHEABLE           3       /* cacheable non-coherent */
   
 /* CPU dependent mtc0 hazard hook */  /* CPU dependent mtc0 hazard hook */
 #define COP0_SYNC               /* nothing */  #define COP0_SYNC               /* nothing */
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 #define MIPS_SR_COP_USABILITY   0xf0000000  #define MIPS_SR_COP_USABILITY   0xf0000000
 #define MIPS_SR_COP_0_BIT       0x10000000  #define MIPS_SR_COP_0_BIT       0x10000000
 #define MIPS_SR_COP_1_BIT       0x20000000  #define MIPS_SR_COP_1_BIT       0x20000000
   #define MIPS_SR_COP_2_BIT       0x40000000
   
         /* r4k and r3k differences, see below */          /* r4k and r3k differences, see below */
   
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 #define MIPS3_SR_DIAG_DL        0x01000000              /* QED 52xx */  #define MIPS3_SR_DIAG_DL        0x01000000              /* QED 52xx */
 #define MIPS3_SR_DIAG_IL        0x00800000              /* QED 52xx */  #define MIPS3_SR_DIAG_IL        0x00800000              /* QED 52xx */
   #define MIPS3_SR_PX             0x00800000              /* MIPS64 */
 #define MIPS3_SR_SR             0x00100000  #define MIPS3_SR_SR             0x00100000
 #define MIPS3_SR_NMI            0x00080000              /* MIPS32/64 */  #define MIPS3_SR_NMI            0x00080000              /* MIPS32/64 */
 #define MIPS3_SR_DIAG_CH        0x00040000  #define MIPS3_SR_DIAG_CH        0x00040000
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 #define MIPS_HARD_INT_MASK      0xfc00  #define MIPS_HARD_INT_MASK      0xfc00
 #define MIPS_SOFT_INT_MASK_1    0x0200  #define MIPS_SOFT_INT_MASK_1    0x0200
 #define MIPS_SOFT_INT_MASK_0    0x0100  #define MIPS_SOFT_INT_MASK_0    0x0100
   #define MIPS_SOFT_INT_MASK      0x0300
   #define MIPS_INT_MASK_SHIFT     8
   
 /*  /*
  * mips3 CPUs have on-chip timer at INT_MASK_5.  Each platform can   * mips3 CPUs have on-chip timer at INT_MASK_5.  Each platform can
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  *   *
  * Common vectors:  reset and UTLB miss.   * Common vectors:  reset and UTLB miss.
  */   */
 #define MIPS_RESET_EXC_VEC      0xBFC00000  #define MIPS_RESET_EXC_VEC      MIPS_PHYS_TO_KSEG1(0x1FC00000)
 #define MIPS_UTLB_MISS_EXC_VEC  0x80000000  #define MIPS_UTLB_MISS_EXC_VEC  MIPS_PHYS_TO_KSEG0(0)
   
 /*  /*
  * MIPS-1 general exception vector (everything else)   * MIPS-1 general exception vector (everything else)
  */   */
 #define MIPS1_GEN_EXC_VEC       0x80000080  #define MIPS1_GEN_EXC_VEC       MIPS_PHYS_TO_KSEG0(0x0080)
   
 /*  /*
  * MIPS-III exception vectors   * MIPS-III exception vectors
  */   */
 #define MIPS3_XTLB_MISS_EXC_VEC 0x80000080  #define MIPS3_XTLB_MISS_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080)
 #define MIPS3_CACHE_ERR_EXC_VEC 0x80000100  #define MIPS3_CACHE_ERR_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0100)
 #define MIPS3_GEN_EXC_VEC       0x80000180  #define MIPS3_GEN_EXC_VEC       MIPS_PHYS_TO_KSEG0(0x0180)
   
 /*  /*
  * TX79 (R5900) exception vectors   * TX79 (R5900) exception vectors
  */   */
 #define MIPS_R5900_COUNTER_EXC_VEC              0x80000080  #define MIPS_R5900_COUNTER_EXC_VEC      MIPS_PHYS_TO_KSEG0(0x0080)
 #define MIPS_R5900_DEBUG_EXC_VEC                0x80000100  #define MIPS_R5900_DEBUG_EXC_VEC        MIPS_PHYS_TO_KSEG0(0x0100)
   
 /*  /*
  * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.   * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
  */   */
 #define MIPS3_INTR_EXC_VEC      0x80000200  #define MIPS3_INTR_EXC_VEC      MIPS_PHYS_TO_KSEG0(0x0200)
   
 /*  /*
  * Coprocessor 0 registers:   * Coprocessor 0 registers:
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  * 13   MIPS_COP_0_CAUSE        3333 Exception cause register.   * 13   MIPS_COP_0_CAUSE        3333 Exception cause register.
  * 14   MIPS_COP_0_EXC_PC       3636 Exception PC.   * 14   MIPS_COP_0_EXC_PC       3636 Exception PC.
  * 15   MIPS_COP_0_PRID         3333 Processor revision identifier.   * 15   MIPS_COP_0_PRID         3333 Processor revision identifier.
    * 15/1 MIPS_COP_0_EBASE        ..33 Exception Base
  * 16   MIPS_COP_0_CONFIG       3333 Configuration register.   * 16   MIPS_COP_0_CONFIG       3333 Configuration register.
  * 16/1 MIPS_COP_0_CONFIG1      ..33 Configuration register 1.   * 16/1 MIPS_COP_0_CONFIG1      ..33 Configuration register 1.
  * 16/2 MIPS_COP_0_CONFIG2      ..33 Configuration register 2.   * 16/2 MIPS_COP_0_CONFIG2      ..33 Configuration register 2.
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  * 18   MIPS_COP_0_WATCH_LO     .336 WatchLo register.   * 18   MIPS_COP_0_WATCH_LO     .336 WatchLo register.
  * 19   MIPS_COP_0_WATCH_HI     .333 WatchHi register.   * 19   MIPS_COP_0_WATCH_HI     .333 WatchHi register.
  * 20   MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register.   * 20   MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register.
    * 22   MIPS_COP_0_OSSCRATCH    ...6 [RMI] OS Scratch register. (select 0..7)
  * 23   MIPS_COP_0_DEBUG        .... Debug JTAG register.   * 23   MIPS_COP_0_DEBUG        .... Debug JTAG register.
  * 24   MIPS_COP_0_DEPC         .... DEPC JTAG register.   * 24   MIPS_COP_0_DEPC         .... DEPC JTAG register.
  * 25   MIPS_COP_0_PERFCNT      ..36 Performance Counter register.   * 25   MIPS_COP_0_PERFCNT      ..36 Performance Counter register.
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 #define MIPS_COP_0_ERROR_PC     _(30)  #define MIPS_COP_0_ERROR_PC     _(30)
   
 /* MIPS32/64 */  /* MIPS32/64 */
   #define MIPS_COP_0_OSSCRATCH    _(22)
 #define MIPS_COP_0_DEBUG        _(23)  #define MIPS_COP_0_DEBUG        _(23)
 #define MIPS_COP_0_DEPC         _(24)  #define MIPS_COP_0_DEPC         _(24)
 #define MIPS_COP_0_PERFCNT      _(25)  #define MIPS_COP_0_PERFCNT      _(25)
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 #define MIPS3_TLB_MOD_BIT               MIPS3_TLB_DIRTY_BIT  #define MIPS3_TLB_MOD_BIT               MIPS3_TLB_DIRTY_BIT
   
 /*  /*
  * MIPS3_TLB_ATTR values - coherency algorithm:   * MIPS3_TLB_ATTR (CCA) values - coherency algorithm:
  * 0: cacheable, noncoherent, write-through, no write allocate   * 0: cacheable, noncoherent, write-through, no write allocate
  * 1: cacheable, noncoherent, write-through, write allocate   * 1: cacheable, noncoherent, write-through, write allocate
  * 2: uncached   * 2: uncached
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 #endif  #endif
   
 /*  /*
    * Hints for the prefetch instruction
    */
   
   /*
    * Prefetched data is expected to be read (not modified)
    */
   #define PREF_LOAD               0
   #define PREF_LOAD_STREAMED      4       /* but not reused extensively; it */
                                           /* "streams" through cache.  */
   #define PREF_LOAD_RETAINED      6       /* and reused extensively; it should */
                                           /* be "retained" in the cache.  */
   
   /*
    * Prefetched data is expected to be stored or modified
    */
   #define PREF_STORE              1
   #define PREF_STORE_STREAMED     5       /* but not reused extensively; it */
                                           /* "streams" through cache.  */
   #define PREF_STORE_RETAINED     7       /* and reused extensively; it should */
                                           /* be "retained" in the cache.  */
   
   /*
    * data is no longer expected to be used.  For a WB cache, schedule a
    * writeback of any dirty data and afterwards free the cache lines.
    */
   #define PREF_WB_INV             25
   #define PREF_NUDGE              PREF_WB_INV
   
   /*
    * Prepare for writing an entire cache line without the overhead
    * involved in filling the line from memory.
    */
   #define PREF_PREPAREFORSTORE    30
   
   /*
  * CPU processor revision IDs for company ID == 0 (non mips32/64 chips)   * CPU processor revision IDs for company ID == 0 (non mips32/64 chips)
  */   */
 #define MIPS_R2000      0x01    /* MIPS R2000                   ISA I   */  #define MIPS_R2000      0x01    /* MIPS R2000                   ISA I   */
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 #define MIPS_SR7100     0x04    /* SandCraft SR7100             ISA 64  */  #define MIPS_SR7100     0x04    /* SandCraft SR7100             ISA 64  */
   
 /*  /*
    * CPU processor revision IDs for company ID == 12 (RMI)
    */
   #define MIPS_XLR732     0x00    /* RMI XLR732-C                 ISA 64  */
   #define MIPS_XLR716     0x02    /* RMI XLR716-C                 ISA 64  */
   #define MIPS_XLR532     0x08    /* RMI XLR532-C                 ISA 64  */
   #define MIPS_XLR516     0x0a    /* RMI XLR516-C                 ISA 64  */
   #define MIPS_XLR508     0x0b    /* RMI XLR508-C                 ISA 64  */
   #define MIPS_XLR308     0x0f    /* RMI XLR308-C                 ISA 64  */
   #define MIPS_XLS616     0x40    /* RMI XLS616                   ISA 64  */
   #define MIPS_XLS416     0x44    /* RMI XLS416                   ISA 64  */
   #define MIPS_XLS608     0x4A    /* RMI XLS608                   ISA 64  */
   #define MIPS_XLS408     0x4E    /* RMI XLS406                   ISA 64  */
   #define MIPS_XLS404     0x4F    /* RMI XLS404                   ISA 64  */
   #define MIPS_XLS408LITE 0x88    /* RMI XLS408-Lite              ISA 64  */
   #define MIPS_XLS404LITE 0x8C    /* RMI XLS404-Lite              ISA 64  */
   #define MIPS_XLS208     0x8E    /* RMI XLS208                   ISA 64  */
   #define MIPS_XLS204     0x8F    /* RMI XLS204                   ISA 64  */
   #define MIPS_XLS108     0xCE    /* RMI XLS108                   ISA 64  */
   #define MIPS_XLS104     0xCF    /* RMI XLS104                   ISA 64  */
   
   /*
  * FPU processor revision ID   * FPU processor revision ID
  */   */
 #define MIPS_SOFT       0x00    /* Software emulation           ISA I   */  #define MIPS_SOFT       0x00    /* Software emulation           ISA I   */
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 #ifdef MIPS64_SB1  #ifdef MIPS64_SB1
 #include <mips/sb1regs.h>  #include <mips/sb1regs.h>
 #endif  #endif
   #if defined(MIPS64_XLP) || defined(MIPS64_XLR) || defined(MIPS64_XLS)
   #include <mips/rmi/rmixlreg.h>
   #endif
   
 #endif /* _MIPS_CPUREGS_H_ */  #endif /* _MIPS_CPUREGS_H_ */

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