Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

===================================================================
RCS file: /ftp/cvs/cvsroot/src/sys/arch/mips/include/cpuregs.h,v
rcsdiff: /ftp/cvs/cvsroot/src/sys/arch/mips/include/cpuregs.h,v: warning: Unknown phrases like `commitid ...;' are present.
retrieving revision 1.50
retrieving revision 1.50.4.1
diff -u -p -r1.50 -r1.50.4.1
--- src/sys/arch/mips/include/cpuregs.h	2002/03/13 13:18:58	1.50
+++ src/sys/arch/mips/include/cpuregs.h	2002/07/14 18:37:13	1.50.4.1
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpuregs.h,v 1.50 2002/03/13 13:18:58 simonb Exp $	*/
+/*	$NetBSD: cpuregs.h,v 1.50.4.1 2002/07/14 18:37:13 gehenna Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -125,9 +125,8 @@
  * The bits in the status register.  All bits are active when set to 1.
  *
  *	R3000 status register fields:
- *	MIPS_SR_CO_USABILITY	Control the usability of the four coprocessors.
- *	MIPS_SR_BOOT_EXC_VEC	Use alternate exception vectors.
- *	MIPS_SR_TLB_SHUTDOWN	TLB disabled.
+ *	MIPS_SR_COP_USABILITY	Control the usability of the four coprocessors.
+ *	MIPS_SR_TS		TLB shutdown.
  *
  *	MIPS_SR_INT_IE		Master (current) interrupt enable bit.
  *
@@ -143,8 +142,10 @@
 
 	/* r4k and r3k differences, see below */
 
-#define	MIPS_SR_BOOT_EXC_VEC	0x00400000
-#define	MIPS_SR_TLB_SHUTDOWN	0x00200000
+#define	MIPS_SR_MX		0x01000000	/* MIPS64 */
+#define	MIPS_SR_PX		0x00800000	/* MIPS64 */
+#define	MIPS_SR_BEV		0x00400000	/* Use boot exception vector */
+#define	MIPS_SR_TS		0x00200000
 
 	/* r4k and r3k differences, see below */
 
@@ -206,9 +207,9 @@
 
 #define	MIPS3_SR_DIAG_DL	0x01000000		/* QED 52xx */
 #define	MIPS3_SR_DIAG_IL	0x00800000		/* QED 52xx */
-#define	MIPS3_SR_DIAG_BEV	0x00400000
-#define	MIPS3_SR_SOFT_RESET	0x00100000
+#define	MIPS3_SR_SR		0x00100000
 #define	MIPS3_SR_EIE		0x00100000		/* TX79/R5900 */
+#define	MIPS3_SR_NMI		0x00080000		/* MIPS32/64 */
 #define	MIPS3_SR_DIAG_CH	0x00040000
 #define	MIPS3_SR_DIAG_CE	0x00020000
 #define	MIPS3_SR_DIAG_PE	0x00010000