CVS log for src/sys/arch/mips/include/cache_r5k.h

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Pull up following revision(s) (requested by tsutsui in ticket #965):

	sys/arch/mips/include/cache_r5k.h: revision 1.5
	sys/arch/mips/mips/cache_r5k_subr.S: revision 1.4
	sys/arch/mips/mips/cache_r5k.c: revision 1.21

Use proper "page" alignments for R5k Page Invalidate(S) op.  PR/55139

According to NEC "User's Manual VR5000, VR1000 64-BIT MICROPROCESSOR
INSTRUCTION" (U12754EJ1V0UMJ1), R5000 Page Invalidate (S) op does
"a page invalidate by doing a burst of 128 line invalidates to
the secondary cache at the page specified by the effective address
generated by the CACHE instruction, which must be page aligned."

This description looks a bit confusing, but "page" used here
implies fixed 32 byte cacheline * 128 lines == 4096 bytes,
not our variable "PAGE_SIZE" used in VM paging ops.  Note
the current default PAGE_SIZE for MIPS3 has been changed to 8192.

While here, also define and use proper macro for the "page" and CACHEOP
arg for the R5k Page_Invalidate_S op, as the manual also describes
the cache op field 10111 as "Page Invalidate" for the secondary cache.

No visible regression on Cobalt Qube 2700 (Rm5230) through
whole installation using netbsd-9 based Cobalt RestoreCD/USB.

Use proper "page" alignments for R5k Page Invalidate(S) op.  PR/55139

According to NEC "User's Manual VR5000, VR1000 64-BIT MICROPROCESSOR
INSTRUCTION" (U12754EJ1V0UMJ1), R5000 Page Invalidate (S) op does
"a page invalidate by doing a burst of 128 line invalidates to
the secondary cache at the page specified by the effective address
generated by the CACHE instruction, which must be page aligned."

This description looks a bit confusing, but "page" used here
implies fixed 32 byte cacheline * 128 lines == 4096 bytes,
not our variable "PAGE_SIZE" used in VM paging ops.  Note
the current default PAGE_SIZE for MIPS3 has been changed to 8192.

While here, also define and use proper macro for the "page" and CACHEOP
arg for the R5k Page_Invalidate_S op, as the manual also describes
the cache op field 10111 as "Page Invalidate" for the secondary cache.

No visible regression on Cobalt Qube 2700 (Rm5230) through
whole installation using netbsd-9 based Cobalt RestoreCD/USB.

update from HEAD

Sync with HEAD

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

When running an N32 kernel, run it with 64-bit addresses even though the
kernel itself will only use 32-bit addresses.  There are exceptions.
bus_space_handles are now register_t instead of intptr_t.  This allows them
to contain XKPHYS addresses.  Now bus_space can use XKPHYS addresses and
not required non-KSEG1 devices to be mapped in KSEG2 thereby leaving more
KSEG2 space for the kernel to use.

The cache range routines (but not index routines) now take a register_t
instead of vaddr_t so they can too take a XKPHYS address.  This allows the
pmap to use a page's XKPHYS address to clean sync the icache thereby avoiding
massive icache invalidations.

Since "cache" instruction effects are global to all CPUs and their caches, we
can use the above to greatly simplify MP page isyncs.  If using an O32 kernel
with pages outside KSEG0, index ops still need to be performed since there
isn't an a quick way of mapping the page.

merge ktrace-lwp.

Sync with HEAD.

Add prototype for r5k_sdcache_wbinv_range_index()

Add support for R5k secondary caches, from code Chris Sekiya sent me a long
time ago, with small tweaks by me.  Since the R5k doesn't do VCE, the pmap
still needs to be whacked for R5kSC CPUs to work correctly, but this is a
start.