File: [cvs.NetBSD.org] / src / sys / arch / mips / include / Attic / rnd.h (download)
Revision 1.2, Fri Jun 9 04:24:22 2000 UTC (23 years, 9 months ago) by soda
Branch: MAIN
CVS Tags: netbsd-1-5-base, netbsd-1-5-RELEASE, netbsd-1-5-PATCH003, netbsd-1-5-PATCH002, netbsd-1-5-PATCH001, netbsd-1-5-BETA2, netbsd-1-5-BETA, netbsd-1-5-ALPHA2, netbsd-1-5 Branch point for: minoura-xpg4dl
Changes since 1.1: +2 -2
lines
this header don't have to include <machine/locore.h>,
include <mips/locore.h> instead.
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/* $NetBSD: rnd.h,v 1.2 2000/06/09 04:24:22 soda Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MIPS_RND_H_
#define _MIPS_RND_H_
/*
* Machine-specific support for rnd(4)
*/
#include <machine/cpu.h>
#include <mips/locore.h>
#ifdef _KERNEL
#ifdef MIPS3
static __inline int
cpu_hascounter(void)
{
/*
* MIPS III and MIPS IV CPU's have a cycle counter
* running at half the internal pipeline rate.
*/
return (CPUISMIPS3);
}
static __inline u_int32_t
cpu_counter(void)
{
return mips3_cycle_count();
}
#endif
#endif /* _KERNEL */
#endif /* !_MIPS_RND_H_ */