CVS log for src/sys/arch/mips/conf/files.mips

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Default branch: MAIN

Sync w/ HEAD.

sync with head

Alignment nit.

Sync with HEAD.

Sync with HEAD.

Work in progress for MIPS modules.  Only tested on mipseb64, not yet
enabled anywhere.

Remove duplicate out-of-place comment.

make process_machdep.c included always since it provides register i/o used by
sys_process_getlwpstatus.c which is always included.

harmonize process_machdep.c inclusion.

move stacktrace_subr() from trap.c into new mips_stacktrace.c so
it can be shared between ddb, other mips kernel components (see
locore), and an upcoming crash(8) port.

remove second copy of kdbpeek() (hidden by old DDB_TRACE
option, but they're functionally equivalent.)

tested on octeon.

ok simonb@

More whitespace

defflag foo on each line to make searching easier.

sort some lines and fix some indentation while I'm here.

Sync with HEAD

Merge the [pgoyette-compat] branch

Add glue for netbsd32 compat_13 and _16 modules

update from HEAD

Sync with HEAD

Use sdcache routines.
Remove old cache support.
Switch to new cache routines.

Change MIPS to use the common pmap code.
Switch to 8KB pages on CPUs with a R4K MMU.
Simplify cache code.
Merge in most of changes from matt-mips64 branch

Sync with HEAD

Initial import of Cavium Octeon and Octeon Plus SoC and
specifically Ubiquiti Networks EdgeRouter LITE support.
Currently the ethernet and uart are worked.
This support was contributed by Internet Initiative Japan Inc.

Add option NOMIPSEMUL so disable (almost) all emulation.

Add core_r4k_pcache*.S files.

Split syncicache functions into separate file: pmap_syncicache.
Support up to 1024 ASIDs.
Always use atomic ops for manipulating pm_shootdown_pending
Nuke PMAP_POOLPAGE_DEBUG
defparam MIPS_PAGE_SHIFT
Track colors of execpages.

Add support for 8KB pages.

Take part of the KSEG2 space and use it to "almost" direct another 256MB
of memory so that N32 kernels can make use of ram outside of KSEG0.  This
allows N32 kernels to be useful on systems with 4GB of RAM or more.

Add support for the MIPS DSP ASE (as a second PCU).

Add support for a loongson2_subr.S.  This is needed since that chip needs
special handling to manually flush the ITLB on TLB updates.

Catchup with rmind-uvmplock merge.

Welcome to 5.99.53!  Merge rmind-uvmplock branch:

- Reorganize locking in UVM and provide extra serialisation for pmap(9).
  New lock order: [vmpage-owner-lock] -> pmap-lock.

- Simplify locking in some pmap(9) modules by removing P->V locking.

- Use lock object on vmobjlock (and thus vnode_t::v_interlock) to share
  the locks amongst UVM objects where necessary (tmpfs, layerfs, unionfs).

- Rewrite and optimise x86 TLB shootdown code, make it simpler and cleaner.
  Add TLBSTATS option for x86 to collect statistics about TLB shootdowns.

- Unify /dev/mem et al in MI code and provide required locking (removes
  kernel-lock on some ports).  Also, avoid cache-aliasing issues.

Thanks to Andrew Doran and Joerg Sonnenberger, as their initial patches
formed the core changes of this branch.

Sync with HEAD.

sync with head

Add MIPS64_RMIXL (XLR/XLS) and MIPS64R2_RMIXL (XLP).  This allows the kernel
to treat this special which is needed for MP support. When accessing the TLB,
always lock the TLB before hand.  If in the miss handlers, the TLB is already
locked let trap deal with the exeception.

Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code.  (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.

Remove IRIX emulation

sync with head

- option MIPS_DDB_WATCH is deprecated, removed

slight reordering.  no functional change.

Add separate support for MIPS32R2 and MIPS64R2.
Use EHB/SSNOP and jr.hb ra as appropriate (COP0_SYNC now uses them).
Add support for COP_0_HWRENA and COP_0_USERLOCAL (use by rdhwr $3,$29
instruction for TLS support).
Add mips3+ reserved instruction handler to emulate rdhwr is many fewer
instructions.

sync with head

Sync with HEAD

Major merge forward from matt-nb5-mips64.
New fixup code.
New common SPL code.
New common interrupt code.
Move related variables into structures.
Cleanup locore (move MD variable into it).
Kill StudlyCaps
Use PCU for FPU

- define config options flag MIPS_DDB_WATCH, enables COP0 watchpoint support in ddb

Break out break slot instruction emualtion into its own .S file.
Redo that and simplify

Implement pmap_physload_device(9) to replace xmd(4) MD backend.
Implement pmap_mmap(9) and use it from mem(4) and xmd(4).

xmd(4) glue for mips.  Not tested.

Unify /dev/{mem,kmem,zero,null} implementations in MI code.  Based on patch
from Joerg Sonnenberger, proposed on tech-kern@, in February 2008.

Work and depression still in progress.

sync with head

Split FPU support into separate file and keep internals private to that file.
Make it MPSAFE.  Change interface to be very similar to what's used on other
architectures.
Add l_md.md_fpcpu to mdlwp (needed for MPSAFE)
Move pridtab from <mips/cpu.h> to <mips/locore.h>
Add initial common IPI dispatcher.
Split cpu_* routines from mips_machdep.c into cpu_subr.c
Add cpu_startup_common which has the code replicated in half-dozen
plus machdep.c files.

Add spl_stubs.c

Add mipsXX_tlb_enter which modifies/sets a specific TLB entry with a new
mapping (useful for wired TLB entries).
Add mips_fixup_exceptions which will walk through the exception vectors
and allows the fixup of any cpu_info references to be changed to a more
MP-friendly incarnation.
Define a common fixup method to use a wired TLB entry at -PAGE_SIZE allowing
direct loads using a negative based from the zero register.
Change varible pmap_tlb_info t pmap_tlb0_info.

add entry for mips/spl.S so kernel can compile

Add __HAVE_FAST_SOFTINTS support.
Add routine to remap an uarea via a direct-mapped address.  This avoids
TLB machinations when swtching to/from the softint thread.  This can only
be done for lwp which won't exit.

Change mips kernel options SOFTFLOAT to FPEMUL.  Allow a kernel to have
no FP emulation code.  Fix insufficient SYMTAB_SPACE.  When a kernel without
an FPU and with FPEMUL code, the application will trap with a SIGILL/ILL_ILLOPC
signal, not SIGSEGV/SEGV_MAPERR.

Seperate the pmap TLB functions into their own file.
For 32 bit kernels, make sure that mips_virtual_end doesn't go past
VM_MAX_KERNEL_ADDRESS.

Please segtab lookups into separate file.
Add mips_add_physload
Add mips_init_lwp0_uarea
cleanup lwp0/cpu_info_store initialization.

Merge from matt-nb5-mips64
Merge mips-specific arch files.

add MIPS64_XLP MIPS64_XLR MIPS64_XLS to list of flags in opt_cputype.h

Add COMPAT_NETBSD32 support

Make ddb(4) trace work on 64-bit ABIs.

For now:

- Values are shown in 32-bit.
- Only 4 arguments are shown.
- DDB_TRACE (heuristic version) is left as is.


Reviewed By:	matt

sync with head.

Add latent ENABLE_MIPS_16KB_PAGE option.

Add loongson2 specific cache ops

Change MIPS64_LOONGSON2 to MIP3_LOONGSON2 since it's a MIPS3 and not MIPS64.

Add MIPS64_LOONGSON2F since it needs some special help in various places.

sync with head.

Sync with HEAD.

Sync with HEAD.

Update haad-dm branch to haad-dm-base2.

Make the emulations, exec formats, coredump, NFS, and the NFS server
into modules. By and large this commit:

- shuffles header files and ifdefs
- splits code out where necessary to be modular
- adds module glue for each of the components
- adds/replaces hooks for things that can be installed at runtime

sync with HEAD

Sync with HEAD.

sync with head.

Refactor in_cksum/in4_cksum/in6_cksum implementations:
- All three functions are included in the kernel by default.
  They call a backend function cpu_in_cksum after possibly
  computing the checksum of the pseudo header.
- cpu_in_cksum is the core to implement the one-complement sum.
  The default implementation is moderate fast on most platforms
  and provides a 32bit accumulator with 16bit addends for L32 platforms
  and a 64bit accumulator with 32bit addends for L64 platforms.
  It handles edge cases like very large mbuf chains (could happen with
  native IPv6 in the future) and provides a good base for new native
  implementations.
- Modify i386 and amd64 assembly to use the new interface.

This disables the MD implementations on !x86 until the conversion is
done. For Alpha, the portable version is faster.

sync with HEAD

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Sync with HEAD

sync with head.

Add netbsd32 entry

Sync with head.

Sync with head.

Remove leftover netns stuff.

sync with head.

Merge newlock2 to head.

Checkpoint work in progress.

sync with head

sync with head.

Sync with head.

Pull up following revision(s) (requested by tsutsui in ticket #1260):
	sys/arch/mips/mips/fp.S: revision 1.31
	sys/arch/mips/mips/mips_fputrap.c: revision 1.3
	sys/arch/mips/conf/files.mips: revision 1.54
Update FPE trapsignal functions for new siginfo,
based on a patch provided by Matthias Drochner.
Ok'ed by christos, and fixes PR port-mips/26410.

Pull up following revision(s) (requested by tsutsui in ticket #1260):
	sys/arch/mips/mips/fp.S: revision 1.31
	sys/arch/mips/mips/mips_fputrap.c: revision 1.3
	sys/arch/mips/conf/files.mips: revision 1.54
Update FPE trapsignal functions for new siginfo,
based on a patch provided by Matthias Drochner.
Ok'ed by christos, and fixes PR port-mips/26410.

sync with head - hopefully this will work

sync with head.

Merge 2006-03-28 NetBSD-current into the "peter-altq" branch.

Update FPE trapsignal functions for new siginfo,
based on a patch provided by Matthias Drochner.

Ok'ed by christos, and fixes PR port-mips/26410.

merge ktrace-lwp.

Sync with HEAD. Here we go again...

Add MI mips3 wired map functions based on patch in port-mips/31915
from Garrett D'Amore of Tadpole Computer Inc.
Please refer discussion filed in the PR for details.

sync with -current

Sync with HEAD.

-remove definition of "struct sigframe" -- haven't found a use of it
 (should fix build problems w/o COMPAT_16 reported by Markus W Kilbinger
  per PR port-mips/29041 and by Havard Eidnes)
-further shuffle COMPAT_* conditionals to allow COMPAT_ULTRIX
 w/o COMPAT_16

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

fix some problems with FPU exception signaling:
-The MachFPTrap did generate pre-siginfo arguments to trapsignal(),
 leading to an immediate crash.
 Put the siginfo generation into a separate .c file for simplicity.
-The exception bits in MIPS_FPU_CSR didn't get cleared, leading to
 trouble later ("kernel used FPU" on pmax).
 XXX This should probably be done for the "unimplemented fpu instruction"
  case as well, but I don't know how to test this. Or, even better -
  centralize the CSR clearing before the branch in MachFPTrap.

Remove preprocessor conditional MIPS3_L2CACHE_ABSENT, which was rendered
superfluous by Tsutsui-san's previous changes.

(this change differs slightly from that posted to port-mips@, as
mips_flushcache_allpvh should be compiled iff MIPS3_PLUS is defined and
MIPS3_L2CACHE_ABSENT should be removed from files.mips as well)

add compat_16_machdep.c

Add R10000 cache ops, written by KIYOHARA Takashi and posted on port-sgimips.
Enabled by options ENABLE_MIPS4_CACHE_R10K for now.

Add support for R5k secondary caches, from code Chris Sekiya sent me a long
time ago, with small tweaks by me.  Since the R5k doesn't do VCE, the pmap
still needs to be whacked for R5kSC CPUs to work correctly, but this is a
start.

Sync with HEAD.

Put the MIPS64_SB1 option in opt_cputype.h.

Catch up to -current

- Make monolistic files into smaller manageable pieces, resulting
three new files;
    sig_machdep.c (from mips_machdep.c)
    copy.S and sigcode.S (from locore.S)
- Nuke the local use of struct sigframe, which is now identical to
struct sigcontext, from sendsig() as the consequence of new signal
trampoline.

Note a new MIPS64_SB1 option that should be included in opt_cputype.h
one day.

sync kqueue branch with HEAD

Catch up to -current.

catch up with -current.

catch up with -current.

Overhaul the emulation facility.  We do this by:

- accumulating all emulation code (including floating-point) in one place
- steal MachFPInterrupt() back from SOFTFLOAT for use only with interrupts
  and traps from *real* FPUs
- introducing MachEmulateInst() as a common dispatch point for all
  emulated instructions
- cleaning up emulation dispatch in trap()

Also, while we're here, implement MIPS2 LL/SC/SYNC emulation for MIPS1.

Tested on r3k with and without SOFTFLOAT enabled.

catch up with -current on kqueue branch

Catch up to -current.

Use the current MIPS in_cksum for in4_cksum too.

Catch up to -current.

Don't make arch/mips/mips/mips_mcclock.c mandatory for all mips ports
with an mcclock - pmax is the only one currently using this.

Catch up to -current.
(CVS: It's not just a program. It's an adventure!)

Catch up with -current.

All the mips ports had an identical procfs_machdep.c, so use a common
file under arch/mips/mips.

Add support for MIPS32 and MIPS64 architectures:
 - Build mips3/5900/32/64 support subroutines.
 - Move arch/mips/mips/fp.S to central location.
 - Move NOFPU to opt_cputype.h.

Catch up to -current.

Sync w/ -current.

Options MIPS3_5200 and MIPS3_L2CACHE_PRESENT are gone.

Sync kqueue branch with -current.

Catch up to -current.

TX39, R5900 cache configuration.

- convert usage of "defopt" to "defflag" where the relevant option does
  not support a value (e.g., it's to be used as "options FOO" instead of
  "options FOO=xxx"). options that take a value were converted to
  defparam recently.
- minor whitespace & formatting cleanups

Added COMPAT_IRIX (being developped, not functionnal at that time)

cleanup:
	options SPACE TAB
	makeoptions TAB
	psuedo-device TAB
	remove trailing whitespace
	replace multiple spaces -> tabs
	options "FOO" -> options FOO
	options "FOO=bar" -> options FOO=bar
	options "FOO=\"bar\"" -> options FOO="\"bar\""

file files.mips was added on branch nathanw_sa on 2002-01-08 00:26:15 +0000

Merge the thorpej-mips-cache branch onto the trunk.  This is an
overhaul of how caches are handled for NetBSD's MIPS ports.

Pull in new cache code, conditional on which CPU arch's are configured
into the kernel.

Catch up with -current.

Moved COMPAT_LINUX config stuff from arch/sgimips to arch/mips, so that it's
available on all Mips ports.

Sync with head (for UBC+NFS fixes, mostly).

New syscall entry implementation based on the Alpha version
as hacked by mycroft.
- Use syscall_intern() to give a process a plain or fancy
  syscall based on ktrace flags.
- Avoid copying from the trapframe into a local array as much
  as possible.

Yields roughly 5% improvement on a 25MHz R3000 (DECstation 5000/200)
on a simple syscall benchmark.

There's still some work that can be done using __HAVE_MINIMAL_EMUL.

Sync with HEAD.

Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.

Add MIPS3_NO_PV_UNCACHED option to handle virtual coherency issues by
only allowing one mapping at a time instead of mapping uncached.  Done
by removing conflicting mappings from the pmap when entering a new
mapping.  UVM will remember and re-fault the requested page when needed
for the original mapping.  Originally done to support our internal machine
that does not support uncached memory completely.  Not enabled by default
currently.  It may make sense to try on the cobalt or sgi ports.

provide indicators of a few more things that might go in opt_cputype.h

Pull in geocast mips ddb improvements and start bringing in kgdb support.
Add ddb support for QED opcodes, fill in enough routines so "next" usually
works, kdbpoke support for any size.  Add callback that ports can hook when
entering and leaving ddb.  This can be used for things like turning
off watchdogs while in ddb.

MachForceCacheUpdate and cacheflush_bug have never been used in NetBSD,
so remove references them, and do a little other cleanup.

Populate the cputype defopt (not enabled yet).

Allow non-pmax to use COMPAT_ULTRIX.

Allow arch-specific code to specify in4_cksum() like it can specify
in_cksum().

Pull up to last week's -current.

FIX:
port-mips/9016 [serious/medium]:
        MIPS FPU emulator points wrong epc on exception case

	Responsible:    port-mips-maintainer (NetBSD/mips Portmasters)
	State:          open
	Class:          sw-bug
	Originator:     Shuichiro URATA
	Release:        current 12/11/1999
	Arrival-Date:   Fri Dec 17 10:18:00 1999
commit patch
     http://www.a-r.org/~ur/softfloat1211.diff.gz
     by Shuichiro URATA (ur@a-r.org)

on port-mips@netbsd.org:
Shuichiro URATA <ur@a-r.org> makes kernel softfloat emulation code.

http://www.a-r.org/~ur/softfloat1116.diff.gz

is Patch for
      sys/arch/mips/conf/files.mips
      sys/arch/mips/mips/fp.S
      sys/arch/mips/mips/fpemu.c
      sys/arch/mips/mips/genassym.cf
      sys/arch/mips/mips/locore.S
      sys/arch/mips/mips/mips_machdep.c
      sys/arch/mips/mips/process_machdep.c
      sys/arch/mips/mips/trap.c
      sys/arch/mips/mips/vm_machdep.c
After apply this patch,pmax package binary works on hpcmips!

Sync w/ -current.

Nuke register and remove trailling white space.

Add defopt opt_mips_cache.h and allow 'clock' device to not require the mc6xx files

compat_13_sigreturn is needed for compat_ultrix too

Make signal delivery work again.

Add empty opt_cputype.h to satisfy changes committed during
defopt'ing of network options.

Configure mips_mclock if  "clock|mccclock".

All(?) ARC boxes use mcclock, but QBus decstations use the same
time-of-year clock architecturally mandated for VAXes.

RCSID Police.

Update marc-pcmcia branch from trunk.

Fix for mbufs that start on odd-byte-aligned   boundaries, and use.

MIPS cpu-speed detection using mc146818 clock.

Compute CPU speed(MHz) and loop multiplier for DELAY() based on
counting empty loop between mcclock ticks.  New global: cpu_mhz.
Change pmax/pmax/machdep.c to build baseboard model names from cpu_mhz.
Set  'cpuspeed' for more realistic DELAY() on mips3 models.

Mips CPU constants, testing, and calibration from D. Sean Davidson
<davidson@zk3.dec.com> and Simon Burge <simonb@telstra.com.au>.

revert to MI in_cksum code.

mips-tuned bcopy from Jon Kay (UCSD) released under BSD copyright,
with standard BSD in_cksum() interface by Jonathan Stone.

Add ddb to mips/conf/files.mips. Garbage-collect mdb.

Fix typo.
Include minidebug.c with options MDB.

Use  generic MIPS pmap vm_machdep.c

Move the mips sys_machdep.c from pmax/pmax to mips/mips, to enforce a
common sysarch on all mips ports.

Eliminate old mips/mips/elf.c ELF exec code.
Don't call into from the a.out exec hook; don't configure it into kernels.

Change pmax port over to using ``mips MI'' trap handler.

Add arch/mips/mips/mips_machdep.c, it's now compiled as a separate file.

Add mips/mips/mem.c and mips/mips/process_machdep.c

Kernel config file for source code shared by mips-based NetBSD ports.