CVS log for src/sys/arch/i386/i386/mptramp.S

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update from HEAD

Pack the useful variables at the end of the trampoline page; eliminates
a hard-coded dependency on KERNBASE. Note that I cannot test this change
on i386 right now, but it seems fine enough.

Sync with HEAD

Clean up, it is easier to debug with qemu+gdb anyway.

Define MINGDTSIZ/MAXGDTSIZ in bytes, not in number of slots; same as
amd64.

Sync with HEAD

Fix the secondary CPUs bug in i386. Same as amd64.

KNF, and reduce the diff between amd64 and i386.

Rebase to HEAD as of a few days ago.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Minor fpu initialisation cleanups:
Set default CR) so that the FPU is enabled (unset CR0_EM) and initialise
  i386_fpu_present to 1.
No need to call the npx trap indirectly, rename to fpunda() to match amd64.
Remove the i386_fpu_exception variable and sysctl (It used to indicate
  which irq was used for fpu exceptions, but we only support 'internal'
  now).  Hopefully no one cares.
fpuinit() now only needs to clear TS before the fninit(). Apart from the
  checks for 486SX and the 'fdiv bug' this matches the amd64 version.
Exclude fpuinit() from XEN kernels, they don't call it - which rather begs
  the question as to whether it is needed at all!

LLVM doesn't support data32/addr32, but is smart enough to figure the
necessary prefixes out.

A few END() markers.

sync with head.

Pull up following revision(s) (requested by rmind in ticket #202):
	sys/arch/x86/include/cpuvar.h: revision 1.46
	sys/arch/xen/include/xenpmap.h: revision 1.34
	sys/arch/i386/include/param.h: revision 1.77
	sys/arch/x86/x86/pmap_tlb.c: revision 1.5
	sys/arch/x86/x86/pmap_tlb.c: revision 1.6
	sys/arch/i386/i386/genassym.cf: revision 1.92
	sys/arch/xen/x86/cpu.c: revision 1.91
	sys/arch/x86/x86/pmap.c: revision 1.177
	sys/arch/xen/x86/xen_pmap.c: revision 1.21
	sys/arch/x86/acpi/acpi_wakeup.c: revision 1.31
	sys/kern/subr_kcpuset.c: revision 1.5
	sys/arch/amd64/include/param.h: revision 1.18
	sys/sys/kcpuset.h: revision 1.5
	sys/arch/x86/x86/mtrr_i686.c: revision 1.26
	sys/arch/x86/x86/mtrr_i686.c: revision 1.27
	sys/arch/xen/x86/x86_xpmap.c: revision 1.43
	sys/arch/x86/x86/cpu.c: revision 1.98
	sys/arch/amd64/amd64/mptramp.S: revision 1.14
	sys/kern/sys_sched.c: revision 1.42
	sys/arch/amd64/amd64/genassym.cf: revision 1.50
	sys/arch/i386/i386/mptramp.S: revision 1.24
	sys/arch/x86/include/pmap.h: revision 1.52
	sys/arch/x86/include/cpu.h: revision 1.50
- Convert x86 MD code, mainly pmap(9) e.g. TLB shootdown code, to use
  kcpuset(9) and thus replace hardcoded CPU bitmasks.  This removes the
  limitation of maximum CPUs.
- Support up to 256 CPUs on amd64 architecture by default.
Bug fixes, improvements, completion of Xen part and testing on 64-core
AMD Opteron(tm) Processor 6282 SE (also, as Xen HVM domU with 128 CPUs)
by Manuel Bouyer.
- pmap_tlb_shootdown: do not overwrite tp_cpumask with pm_cpus, but merge
  like pm_kernel_cpus.  Remove unecessary intersection with kcpuset_running.
  Do not reset tp_userpmap if pmap_kernel().
- Remove pmap_tlb_mailbox_t wrapping, which is pointless after recent changes.
- pmap_tlb_invalidate, pmap_tlb_intr: constify for packet structure.
i686_mtrr_init_first: handle the case when there are no variable-size MTRR
registers available (i686_mtrr_vcnt == 0).

sync to latest -current.

Pull up following revision(s) (requested by jym in ticket #189):
	sys/arch/x86/include/psl.h: revision 1.7
	sys/arch/i386/i386/locore.S: revision 1.98
	sys/arch/amd64/acpi/acpi_wakecode.S: revision 1.11
	sys/arch/amd64/amd64/mptramp.S: revision 1.13
	sys/arch/i386/acpi/acpi_wakecode.S: revision 1.15
	sys/arch/i386/i386/mptramp.S: revision 1.23
	sys/arch/amd64/amd64/locore.S: revision 1.68
Set the CR0_AM bit so processes can enable alignment check errors under
x86 through PSL_AC bit.
ATF test incoming shortly.
PSL_AC is user-settable.

- Convert x86 MD code, mainly pmap(9) e.g. TLB shootdown code, to use
  kcpuset(9) and thus replace hardcoded CPU bitmasks.  This removes the
  limitation of maximum CPUs.

- Support up to 256 CPUs on amd64 architecture by default.

Bug fixes, improvements, completion of Xen part and testing on 64-core
AMD Opteron(tm) Processor 6282 SE (also, as Xen HVM domU with 128 CPUs)
by Manuel Bouyer.

Set the CR0_AM bit so processes can enable alignment check errors under
x86 through PSL_AC bit.

ATF test incoming shortly.

sync with head

Sync with HEAD

Sync with HEAD.

sync with head.

Enable the NX bit feature early in i386 MP trampoline code (do not rely on
cpu_init_msrs() to do it). Having NX bit set on a page will raise a #GP
on fetch if NXE is not enabled, which can happen early when structures
(like idlelwp) are allocated with just rw- rights.

NX is enabled with PAE (if host supports it).

Exact same issue as for amd64, some weeks ago. Same player, shoot again...

Welcome PAE inside i386 current.

This patch is inspired by work previously done by Jeremy Morse, ported by me
to -current, merged with the work previously done for port-xen, together with
additionals fixes and improvements.

PAE option is disabled by default in GENERIC (but will be enabled in ALL in
the next few days).

In quick, PAE switches the CPU to a mode where physical addresses become
36 bits (64 GiB). Virtual address space remains at 32 bits (4 GiB). To cope
with the increased size of the physical address, they are manipulated as
64 bits variables by kernel and MMU.

When supported by the CPU, it also allows the use of the NX/XD bit that
provides no-execution right enforcement on a per physical page basis.

Notes:

- reworked locore.S

- introduce cpu_load_pmap(), used to switch pmap for the curcpu. Due to the
different handling of pmap mappings with PAE vs !PAE, Xen vs native, details
are hidden within this function. This helps calling it from assembly,
as some features, like BIOS calls, switch to pmap_kernel before mapping
trampoline code in low memory.

- some changes in bioscall and kvm86_call, to reflect the above.

- the L3 is "pinned" per-CPU, and is only manipulated by a
reduced set of functions within pmap. To track the L3, I added two
elements to struct cpu_info, namely ci_l3_pdirpa (PA of the L3), and
ci_l3_pdir (the L3 VA). Rest of the code considers that it runs "just
like" a normal i386, except that the L2 is 4 pages long (PTP_LEVELS is
still 2).

- similar to the ci_pae_l3_pdir{,pa} variables, amd64's xen_current_user_pgd
becomes an element of cpu_info (slowly paving the way for MP world).

- bootinfo_source struct declaration is modified, to cope with paddr_t size
change with PAE (it is not correct to assume that bs_addr is a paddr_t when
compiled with PAE - it should remain 32 bits). bs_addrs is now a
void * array (in bootloader's code under i386/stand/, the bs_addrs
is a physaddr_t, which is an unsigned long).

- fixes in multiboot code (same reason as bootinfo): paddr_t size
change. I used Elf32_* types, use RELOC() where necessary, and move the
memcpy() functions out of the if/else if (I do not expect sym and str tables
to overlap with ELF).

- 64 bits atomic functions for pmap

- all pmap_pdirpa access are now done through the pmap_pdirpa macro. It
hides the L3/L2 stuff from PAE, as well as the pm_pdirpa change in
struct pmap (it now becomes a PDP_SIZE array, with or without PAE).

- manipulation of recursive mappings ( PDIR_SLOT_{,A}PTEs ) is done via
loops on PDP_SIZE.

See also http://mail-index.netbsd.org/port-i386/2010/07/17/msg002062.html

No objection raised on port-i386@ and port-xen@R for about a week.

XXX kvm(3) will be fixed in another patch to properly handle both PAE and !PAE
kernel dumps (VA => PA macros are slightly different, and need proper 64 bits
PA support in kvm_i386).

XXX Mixing PAE and !PAE modules may lead to unwanted/unexpected results. This
cannot be solved easily, and needs lots of thinking before being declared
safe (paddr_t/bus_addr_t size handling, PD/PT macros abstractions).

Sync with HEAD.

sync with head

Use CR0_PE (enable protected mode) instead of hardcoding constant.

- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places.  Reduce sys/user.h inclusions.

sync with head.

Sync with HEAD.

Sync with HEAD.

Sync with wrstuden-revivesa-base-2.

remove stray .globl declaration for nonexistent cpu_id, from
Henning Petersen per PR port-i386/39398
being here, remove some more unneeded .globls

Sync with HEAD.

Sync with head.

Replace lines beginning with assembler-style comments with c-style comments,
since '#' can be interpretted as a preprocessor directive.  Remove single
quote ''' from assembler-style comments, as the preprocessor may ignore
everything between them.

Fixes compilation with pcc.

Sync w/ -current. 34 merge conflicts to follow.

Sync with HEAD.

sync with head.

sync with head.

Be more conservative during AP startup. Don't let the AP access the lapic
or do any setup until the boot processor has finished the init sequence,
and add a few more delays.

- Decouple the APIC ID from cpu_info[].
- Probe TSC frequency on each AP when hatching.

Remove clause 3 and 4 from TNF licenses

sync with head

sync with HEAD

Sync with HEAD.

Sync with head.

Sync with HEAD

sync with head.

Use __KERNEL_RCSID().  For these .S files, the following style was
adopted, a la .C files and <sys/cdefs.h>:
  *  move <machine/asm.h> to the top
  *  use __KERNEL_RCSID() immediately after it

Sync with HEAD.

Sync with HEAD.

Sync with HEAD

sync with head.

Sync with HEAD.

Nit.

sync with HEAD

sync with head.

Sync with HEAD.

Follow the merge of pmap.c on i386 and amd64 and move
pmap_init_tmp_pgtbl into arch/x86/x86/pmap.c. Modify the ACPI wakeup
code to restore CR4 before jumping back into kernel space as the large
page option might cover that.

Sync with HEAD.

Sync with head.

merge yamt-x86pmap branch.

- reduce differences between amd64 and i386.  notably, share pmap.c
  between them.  it makes several i386 pmap improvements available to
  amd64, including tlb shootdown reduction and bug fixes from Stephan Uphoff.
- implement deferred pmap switching for amd64.
- remove LARGEPAGES option.  always use large pages if available.
  also, make it work on amd64.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

remove LARGEPAGES option.  always use large pages if available.

fix LARGEPAGES + MP.  PR/23450 from Wojciech Puchar.

sync with head.

Sync with head.

Sync with head.

Update to HEAD.

merge yamt-idlelwp branch.  asked by core@.  some ports still needs work.

from doc/BRANCHES:

	idle lwp, and some changes depending on it.

	1. separate context switching and thread scheduling.
	   (cf. gmcgarry_ctxsw)
	2. implement idle lwp.
	3. clean up related MD/MI interfaces.
	4. make scheduler(s) modular.

- separate context switching and thread scheduling.
- introduce idle lwp.
- change some related MD/MI interfaces and implement i386 version.

sync with head.

merge ktrace-lwp.

Sync with HEAD. Here we go again...

some assym cleanup.
- move copyin and friends from locore.S to their own file, copy.S.
  share it between i386 and xen.
- defparam KERNBASE and kill KERNBASE_LOCORE hack.
- add more symbols to assym.h and use it where appropriate.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

Uppercase CPU, plural is CPUs.

KERNBASE -> KERNBASE_LOCORE (make it compile again)

remove unneeded cpu_feature declaration

Use PAGE_SIZE rather than NBPG.

Follow the spec more closely, and do an ljmp immediately after enabling
protected mode, not several instructions afterwards.

Sync with HEAD.

file mptramp.S was added on branch nathanw_sa on 2002-12-11 06:00:57 +0000

.s -> .S rename. New files: vector.S and spl.S, they have been split
off from locore.s, plus parts of isa/vector.s and isa/icu.s