CVS log for src/sys/arch/i386/i386/locore.S

Up to [cvs.NetBSD.org] / src / sys / arch / i386 / i386

Request diff between arbitrary revisions

Keyword substitution: kv
Default branch: MAIN

s/brinds/brings/ in comments.

Pull up following revision(s) (requested by bouyer in ticket #427):

	sys/arch/xen/include/hypervisor.h: revision 1.58
	sys/arch/i386/i386/locore.S: revision 1.197
	sys/arch/amd64/amd64/locore.S: revision 1.224

Xen's start_info_t is larger than 512 bytes these days, so bump the copy
size to a whole PAGE_SIZE, and CTASSERT() that start_info_t is smaller.

Luckily we didn't use yet the parts skipped

Xen's start_info_t is larger than 512 bytes these days, so bump the copy
size to a whole PAGE_SIZE, and CTASSERT() that start_info_t is smaller.
Luckily we didn't use yet the parts skipped

x86: Sprinkle extensive commentary about %fs/%gs initialization.

Plus some other side quests like the three-stage GDT metamorphosis
lifecycle.

No functional change intended.

x86/locore.S: Nix trailing whitespace.

Revert "x86: Add kthread_fpu_enter/exit support, take two -- forgot i386 bits."

kthread_fpu_enter/exit changes broke some hardware, unclear why, to
investigate before fixing and reapplying these changes.

x86: Expand on comments on ordering around stores to ci_curlwp.

No functional change intended.

PR kern/57240

x86: Add kthread_fpu_enter/exit support, take two -- forgot i386 bits.

Pull up following revision(s) (requested by khorben in ticket #76):

	sys/arch/i386/i386/locore.S: revision 1.191

Make multiboot1 continue with common boot code and not skip CPU type
detection.

Fixes PR 57017 and PR 56935.

Make multiboot1 continue with common boot code and not skip CPU type
detection.

Fixes PR 57017 and PR 56935.

NetBSD/x86: Raise the number of interrupt sources per CPU from 32 to 56.

There has been no objection for three years.
    https://mail-index.netbsd.org/port-amd64/2019/09/22/msg003012.html
Implemented by nonaka@n.o, updated by me.

XenPV: in cpu_switchto(), reset ci_xen_clockf_usermode/ci_xen_clockf_pc,
in case a clock interrupt is deffered while we're switching lwp.
Fix a (rare) panic:
panic: kernel diagnostic assertion "p != NULL" failed: file "/usr/src/sys/kern/kern_clock.c", line 438
seen when xen_timer_handler() is called from the splx() at the end of
mi_switch()

For some reason on my system, the guest starts with a pending event in
the shared structure. On i386, this cause hypervisor_callback to be
entered before cpu_info_primary is fully initialised, especially on i386
ci_intrstack is still NULL, which cause a crash when we try to use it.
Work around by recycling the boot's tmp stack for this until cpu_attach()
is called.

s/annouce/announce/ in comment.

s/struture/structure/ s/structre/structure/

- Add a couple of wrapper functions around STOS and MOVS and use them to zero
  and copy PTEs in preference to memset()/memcpy().

- Remove related SSE / pageidlezero stuff.

build start_xenpvh only if XEN. Fixes NET4501 build issue reported by
John D. Baker

HANDLE_DEFERRED_FPU has to be donne with interrupt disabled;
move it before STIC.
Fix fpudna panic on i386 PV

Introduce Xen PVH support in GENERIC.
This is compiled in with
options XENPVHVM
x86 changes:
- add Xen section and xen pvh entry points to locore.S. Set vm_guest
  to VM_GUEST_XENPVH in this entry point.
  Most of the boot procedure (especially page table setup and switch to
  paged mode) is shared with native.
- change some x86_delay() to delay_func(), which points to x86_delay() for
  native/HVM, and xen_delay() for PVH

Xen changes:
- remove Xen bits from init_x86_64_ksyms() and init386_ksyms()
  and move to xen_init_ksyms(), used for both PV and PVH
- set ISA no-legacy-devices property for PVH
- factor out code from Xen's cpu_bootconf() to xen_bootconf()
  in xen_machdep.c
- set up a specific pvh_consinit() which starts with printk()
  (which uses a simple hypercall that is available early) and switch to
  xencons when we can use pmap_kenter_pa().

Switch to templates.

Merge the bouyer-xenpvh branch, bringing in Xen PV drivers support under HVM
guests in GENERIC.
Xen support can be disabled at runtime with
boot -c
disable hypervisor

Call stipending() only on XenPV. Fix spurious fpudna from kernel mode

Mostly merge changes from HEAD upto 20200411

Get rid of xen-specific ci_x* interrupt handling:
- use the general SIR mechanism, reserving 3 more slots for IPL_VM, IPL_SCHED
  and IPL_HIGH
- remove specific handling from C sources, or change to ipending
- convert IPL number to SIR number in various places
- Remove XUNMASK/XPENDING in assembly or change to IUNMASK/IPENDING
- remove Xen-specific ci_xsources, ci_xmask, ci_xunmask, ci_xpending from
  struct cpu_info
- for now remove a KASSERT that there are no pending interrupts in
  idle_block(). We can get there with some software interrupts pending
  in autoconf XXX needs to be looked at.

Remove VM_GUEST_XEN and define only Xen subtypes:
VM_GUEST_XENPV
VM_GUEST_XENPVH
VM_GUEST_XENHVM
VM_GUEST_XENPVHVM

Set vm_guest in the start routine, if it is hypervisor-specific (e.g Xen PV).
If vm_guest was not set early and we detect Xen in identify_hypervisor(),
assume it is VM_GUEST_XENHVM. Refine to VM_GUEST_PVXENHVM in
hypervisor_match().

PR kern/55114: Install fails with "cpu_switchto: switching above IPL_SCHED (8)"

cpu_switch(): Remove stuff dealing with interrupt levels.  From memory it
was something to do with TLB shootdown interrupts but they have long been
outside the SPL framework.

Sync with head.

Fix a comment

Sync with head.

Back out the cpu_switchto() workaround now that it's no longer needed.

It looks like Xen cpu_hatch() calls cpu_switchto() with prevlwp=NULL,
instead of calling idle_loop() directly.  I can't test a change to
cpu_hatch() right now so allow for prevlwp=NULL.

Hopefully fix some problems seen with MP support on non-x86, in particular
where curcpu() is defined as curlwp->l_cpu:

- mi_switch(): undo the ~2007ish optimisation to unlock curlwp before
  calling cpu_switchto().  It's not safe to let other actors mess with the
  LWP (in particular l->l_cpu) while it's still context switching.  This
  removes l->l_ctxswtch.

- Move the LP_RUNNING flag into l->l_flag and rename to LW_RUNNING since
  it's now covered by the LWP's lock.

- Ditch lwp_exit_switchaway() and just call mi_switch() instead.  Everything
  is in cache anyway so it wasn't buying much by trying to avoid saving old
  state.  This means cpu_switchto() will never be called with prevlwp ==
  NULL.

- Remove some KERNEL_LOCK handling which hasn't been needed for years.

x86: abort pageidlezero unconditionally if there is something to run.

Multiboot2 kernel support for i386

That implementation works either with BIOS or UEFI bootstrap

This requires the following kernel changes:

Add UEFI boot services and I/O method protoypes
src/sys/arch/x86/include/efi.h 1.8 - 1.9

Fix EFI system table mapping in virtual space
src/sys/arch/x86/x86/efi.c 1.19 - 1.20

Make sure no bioscall is issued when booting off UEFI system
src/sys/arch/i386/i386/machdep.c 1.821 - 1.822
src/sys/arch/i386/pci/piixpcib.c 1.22 - 1.23

And the following bootstrap changes:

Add kernel symbols for multiboot1
src/sys/arch/i386/stand/lib/exec_multiboot1.c 1.2 - 1.3
src/sys/arch/i386/stand/lib/libi386.h 1.45 - 1.47

Fix kernel symbols for multiboot2
src/sys/arch/i386/stand/lib/exec_multiboot2.c 1.2 - 1.3

Rewrite the FPU code on x86. This greatly simplifies the logic and removes
the dependency on IPL_HIGH. NVMM is updated accordingly. Posted on
port-amd64 a week ago.

Bump the kernel version to 9.99.16.

Misc reordering, to clarify and reduce the diff against amd64.

Rename fpu_eagerswitch to fpu_switch, and add fpu_xstate_reload to
simplify.

Remove the LazyFPU code, as posted 5 months ago on port-amd64@.

Sync with HEAD

Misc changes in the x86 FPU code. Reduces a future diff. No real functional
change.

Enable EagerFPU on Xen PV. Should work as-is. Sent on port-amd64@.

Start replacing the x86 PTE bits.

Drop PG_RO, PG_KR and PG_PROT, they are useless and create confusion.

Rig the hypercall callback page such that when the kernel happens to
run without a XEN domain loader having previously overwritten the
hypercall page with its hypercall trampoline machine code, we still
get to detect its presence by calling the xen_version hypercall stub.

We use this hack to detect the presence or absence of the hypervisor,
without relying on the MSR support on HVM domains.

This works as an added sanity check that the hypercall page
registration has indeed succeeded in HVM mode.

We reorganise definitions for XEN source support as follows:

XEN - common sources required for baseline XEN support.
XENPV - sources required for support of XEN in PV mode.
XENPVHVM - sources required for support for XEN in HVM mode.
XENPVH - sources required for support for XEN in PVH mode.

Bring in some fixes from HEAD to address a couple of build breaks (in
i386 ipmi driver and sun2 rump tests).  Also fix a 'resolve conflict'
from previous commit in sparc64

With this, I am able to successfully build 66 out of 67 architectures
(the same architectures as handled by the releng build server.  The
only exception is evbarm64 which has a strange build failure during
the installcd step - the same failure occurs on HEAD.  It seems to be
something in the build itself, perhaps a difference between handling
of -O vs -M (MAKEOBJDIR vs MAKEOBJDIRPREFIX).

Missed a file during previous commit completing transition to
separate handler queues for i386.

This should fix the build (hopefully!)

Thanks to Robert Elz for pointing it out.

Sync with HEAD

Resolve a couple of conflicts (result of the uimin/uimax changes)

Xen is PAE, so remove ifdefs.

Sync with HEAD

Rework dbregs, to switch the registers during context switches, and not on
each user->kernel transition via userret. Reloads of DR6/DR7 are expensive
on both native and xen.

Drop NENTRY() from the x86 kernels, use ENTRY(). With PMCs (and other hardware
tracing facilities) we have a much better ways of monitoring the CPU activity
than GPROF, without software modification.

Also I think GPROF has never worked, because the 'start' functions of both
i386 and amd64 use ENTRY(), and it would have caused a function call while the
kernel was not yet relocated.

Pull up the following, requested by maxv in ticket #910:

	sys/arch/amd64/amd64/locore.S	r1.167 (patch)
	sys/arch/i386/i386/locore.S	r1.158 (patch)
	sys/arch/x86/x86/fpu.c		r1.44 (patch)

Don't switch the FPU when leaving a softint. This fixes
several problems when EagerFPU is enabled.

Call fpu_eagerswitch a little later, after we make sure newlwp is not
pinned.

Because if it is, the fpu state of the lwp we are context-switching to
is already installed on the current cpu, so no point re-installing it.
Or, it isn't, and in this case we don't want to install it.

This wrong re-installation can occur when we leave a softint.

It may fix bugs in places that call fpusave_lwp with spl != IPL_HIGH,
and that expect the fpu state to stay in memory. As far as I can tell
only cpu_lwp_free meets these conditions, and as far as I can tell
again, there it's harmless.

Should help PR/53399.

Sync with HEAD

Pull up the following, via patch, requested by maxv in ticket #897:

	sys/arch/amd64/amd64/locore.S           1.166 (patch)
	sys/arch/i386/i386/locore.S             1.157 (patch)
	sys/arch/x86/include/cpu.h              1.92 (patch)
	sys/arch/x86/include/fpu.h              1.9 (patch)
	sys/arch/x86/x86/fpu.c                  1.33-1.39 (patch)
	sys/arch/x86/x86/identcpu.c             1.72 (patch)
	sys/arch/x86/x86/vm_machdep.c           1.34 (patch)
	sys/arch/x86/x86/x86_machdep.c          1.116,1.117 (patch)

Support eager fpu switch, to work around INTEL-SA-00145.
Provide a sysctl machdep.fpu_eager, which gets automatically
initialized to 1 on affected CPUs.

Eager FPU on i386.

Pullup the following revisions via patch, requested by maxv in ticket #629:

	sys/arch/amd64/amd64/genassym.cf		1.63,1.64
	sys/arch/amd64/amd64/locore.S			1.144
	sys/arch/amd64/amd64/machdep.c			1.281-1.283
	sys/arch/i386/i386/genassym.cf			1.105-1.106
	sys/arch/i386/i386/locore.S			1.155
	sys/arch/i386/i386/machdep.c			1.802 (adapted),1.803
	sys/arch/x86/include/cpu.h			1.85
	sys/arch/x86/x86/intr.c				1.115-1.116
	sys/arch/x86/x86/pmap.c				1.275
	sys/arch/x86/x86/sys_machdep.c			1.45
	sys/arch/xen/x86/cpu.c				1.117

Stop sharing the double-fault stack.
Merge the TSS structures into one single cpu_tss structure, and
allocate it dynamically.

Declare IOMAP_VALIDOFF, not to use ci_tss pointers.

Allocate the TSS area dynamically. This way cpu_info and cpu_tss can be
put in separate pages.

update from HEAD

Fix (once again) Xen boot

Add a bootspace structure. It describes the physical and virtual space
layout created by the early kernel bootstrap code. Start using it, and
eliminate several references to KERNBASE and other global symbols. While
here clean up xen-i386, it's really tiring.

Declare INTRFASTEXIT as a function, like amd64; will be expanded soon.

Pull up following revision(s) (requested by maxv in ticket #258):
	sys/arch/amd64/conf/ALL: 1.68
	sys/arch/i386/conf/ALL: 1.428
	sys/arch/i386/i386/i386_trap.S: 1.12
	sys/arch/i386/i386/locore.S: 1.149-1.150
	sys/arch/x86/x86/sys_machdep.c: 1.38
Remove undocumented hack.
--
Switch to the temporary stack right away when booted via multiboot. GRUB
happens to give a correct stack, but it is not guaranteed by the spec. This
temporary stack will be reset later, which is fine.
Fixes PR/50245.
--
Pfff, use %ss and not %ds. The latter is controlled by userland, the former
contains the kernel value (flat); FreeBSD fixed this too a few weeks ago.
As I said earlier, this dtrace code is complete bullshit.
--
Don't allow userland to create 286/386 call gates anymore - they are not
used by Wine. While here, don't allow it to overwrite the static entries
either, don't allow unknown entry types, remove LDT_DEBUG, and style.

Sync with HEAD

Remove vm86.

Pass 3.

Switch to the temporary stack right away when booted via multiboot. GRUB
happens to give a correct stack, but it is not guaranteed by the spec. This
temporary stack will be reset later, which is fine.

Fixes PR/50245.

Pull up following revision(s) (requested by maxv in ticket #1464):

	sys/arch/i386/i386/trap.c:     revision 1.288		(patch)
	sys/arch/i386/i386/machdep.c:  revision 1.783		(patch)
	sys/arch/i386/i386/locore.S:   revision 1.146		(patch)
	sys/arch/amd64/amd64/locore.S: revision 1.122,1.124	(patch)
	sys/arch/amd64/amd64/machdep.c revision 1.254		(patch)
	sys/arch/amd64/amd64/trap.c:   revision 1.95-1.96	(patch)

Remove the osyscall call gate and emulate it. There is a
one-instruction race in it that could panic the kernel.

Restore the ability to run netbsd 1.0 32-bit executables by checking
for the relevant lcall instruction in the trap handler and treating it
as a syscall.

Pull up following revision(s) (requested by maxv in ticket #1464):

	sys/arch/i386/i386/trap.c:     revision 1.288		(patch)
	sys/arch/i386/i386/machdep.c:  revision 1.783		(patch)
	sys/arch/i386/i386/locore.S:   revision 1.146		(patch)
	sys/arch/amd64/amd64/locore.S: revision 1.122,1.124	(patch)
	sys/arch/amd64/amd64/machdep.c revision 1.254		(patch)
	sys/arch/amd64/amd64/trap.c:   revision 1.95-1.96	(patch)

Remove the osyscall call gate and emulate it. There is a
one-instruction race in it that could panic the kernel.

Restore the ability to run netbsd 1.0 32-bit executables by checking
for the relevant lcall instruction in the trap handler and treating it
as a syscall.

Pull up following revision(s) (requested by maxv in ticket #1464):

	sys/arch/i386/i386/trap.c:     revision 1.288		(patch)
	sys/arch/i386/i386/machdep.c:  revision 1.783		(patch)
	sys/arch/i386/i386/locore.S:   revision 1.146		(patch)
	sys/arch/amd64/amd64/locore.S: revision 1.122,1.124	(patch)
	sys/arch/amd64/amd64/machdep.c revision 1.254		(patch)
	sys/arch/amd64/amd64/trap.c:   revision 1.95-1.96	(patch)

Remove the osyscall call gate and emulate it. There is a
one-instruction race in it that could panic the kernel.

Restore the ability to run netbsd 1.0 32-bit executables by checking
for the relevant lcall instruction in the trap handler and treating it
as a syscall.

Remove undocumented hack.

Drop support for svr4 on i386. This feature is not maintained, not
reliable, and of a limited use case. Most svr4 applications got time to be
ported to linux, and we do have a functional, maintained linux emulation.

Reduces the number of entry points into the kernel, the number of
places that need special care (cpu context).

Note that compat_svr4 is still available on sparc.

Remove the remaining parts of compat_oldboot.

Pull up following revision(s) (requested by maxv in ticket #1441):
	sys/arch/i386/i386/trap.c: revision 1.288 via patch
	sys/arch/i386/i386/machdep.c: revision 1.783 via patch
	sys/arch/i386/i386/locore.S: revision 1.146 via patch
	sys/arch/amd64/amd64/locore.S: revision 1.124 via patch
Remove the osyscall call gate on i386, and emulate it. There is a one-
instruction race in it that could panic the kernel.

Pull up following revision(s) (requested by maxv in ticket #1441):
	sys/arch/i386/i386/trap.c: revision 1.288 via patch
	sys/arch/i386/i386/machdep.c: revision 1.783 via patch
	sys/arch/i386/i386/locore.S: revision 1.146 via patch
	sys/arch/amd64/amd64/locore.S: revision 1.124 via patch
Remove the osyscall call gate on i386, and emulate it. There is a one-
instruction race in it that could panic the kernel.

Pull up following revision(s) (requested by maxv in ticket #1441):
	sys/arch/i386/i386/trap.c: revision 1.288 via patch
	sys/arch/i386/i386/machdep.c: revision 1.783 via patch
	sys/arch/i386/i386/locore.S: revision 1.146 via patch
	sys/arch/amd64/amd64/locore.S: revision 1.124 via patch
Remove the osyscall call gate on i386, and emulate it. There is a one-
instruction race in it that could panic the kernel.

Pull up following revision(s) (requested by maxv in ticket #88):
	sys/arch/amd64/amd64/locore.S: revision 1.124
	sys/arch/i386/i386/locore.S: revision 1.146
	sys/arch/i386/i386/machdep.c: revision 1.783
	sys/arch/i386/i386/trap.c: revision 1.288
Remove the osyscall call gate on i386, and emulate it. There is a one-
instruction race in it that could panic the kernel.

Remove the osyscall call gate on i386, and emulate it. There is a one-
instruction race in it that could panic the kernel.

Sync with HEAD

Sync with HEAD

Sync with HEAD

Fix these comments, we probably won't want to keep them up to date.

Sync with HEAD.  (Note that most of these changes are simply $NetBSD$
tag issues.)

Explain the computation

The way the xen dummy page is taken care of makes absolutely no sense at
all, with magic offsets here and there in different layers of the system.
It is just blind luck that everything has always worked as expected so
far.

Due to this wrong design we have a problem now: we allocate one physical
page for lapic, and it happens to overlap with the dummy page, which
causes the system to crash.

Fix this by keeping the dummy va directly in a variable instead of magic
offsets. The asm locore now increments the first pa to hide the dummy page
to machdep and pmap.

Use __kernel_end instead. Does not change anything, but will be meaningful
soon.

Sync with HEAD

Move the virtual address of the LAPIC page out of the data segment on amd64
and i386. The old design was error-prone, and it didn't allow us to map the
data segment with large pages.

Now, the VA is allocated dynamically in the pmap bootstrap code, and entered
manually later. We go from using &local_apic to using *local_apic_va, and we
therefore need one more level of indirection in the asm code.

Discussed on tech-kern.

Rename xen_pmap_bootstrap to xen_locore, it really has nothing to do with
pmap and is just a C version of what amd64 and i386 do in asm.

KNF and simplify Xen, and reduce the diff with amd64 a little

Sync with HEAD

Remove lapic_tpr on amd64 and i386, unused. Now, we have only one pointer
to the LAPIC page, and each register access is done with relative offsets.

Sync with HEAD

Sync with HEAD

Remove lapic_id, lapic_ppr and lapic_isr. We need to be careful though: the
offset of lapic_tpr must not change, and the whole area must be exactly one
page.

This needs to be page-aligned anyway.

Sync with HEAD

The CPU considers a given va as executable if none of its levels have
the NOX bit. With the top level recursive slot, however, several levels
are recursively omitted, which implies that each entry that is not the
child of NOX-ed parents actually appears somewhere in the virtual space
as executable via this slot, even if it is followed by an underlying
entry that has the NOX bit.

This recursive slot is only used to edit the page tree itself. Make it
non-executable.

The preloaded modules are now reallocated dynamically by the kernel. This
area does not need to be executable anymore.

Make the execution flow canonical instead of jumping back and forth, and
complete the userland check.

Try to make this part more readable. No functional change.

The ISA I/O MEM does not need to be executable. Remove the X permission
on it.

Use the same instruction layout to map the ISA I/O. No functional
change.

The comment is still wrong: we are not on (4), we are actually below
the kernel area in physical memory. I'll fix that later.

Define and use fillkpt_blank on i386, like amd64. The PAE case is
included in fillkpt_blank, since PDE_SIZE is either 4 or 8 bytes.

Initialize cpuid_level at compile-time, not run-time. Same as amd64.

Reorder some definitions. Reduces the diff between amd64 and i386.

Define tablesize. Useful when debugging.

Sync with HEAD

There is an issue in the way the fillkpt macro sets up pages on both
amd64 and i386.

The fillkpt loop is equivalent to the following:

	do {
		/* fill in the slot */
		/* increment %ebx to the next slot */
		/* increment %eax to the next pa */
	} while (%ecx > 0)

The issue here is that if %ecx = 0 (i.e., the chunk we are trying to
map is zero-sized), there is still one entry created in the page table.
The kernel expects the va<->pa translation to be linear in low memory.
If there is a zero-sized chunk, the dead entry creates a +4096 offset in
the virtual space, with two consecutive entries that point to the same
physical address. In other words, the mappings are not linear anymore,
which causes the kernel to die.

Before my recent changes, there were only two big chunks that were
mapped, and neither of these could be zero-sized. Now, with multiple,
fine-grained chunks, it is possible that the [SYMS]+[PRELOADED_MODULES]
chunk could be zero-sized.

[PRELOADED_MODULES] is almost never here, and [SYMS] is always here on
default kernels. Except for floppies, where the bootloader does not load
[SYMS].

Should fix PR 51148.

Split the PRELOADED_MODULES+BOOTSTRAP_TABLES chunk into two separate
chunks mapped independently with RWX and RW, on both amd64 and i386.

This way the BOOTSTRAP TABLES are non-executable.

Reduce the diff between amd64 and i386. We invert two instructions on
amd64, but it makes no difference since PDE_SIZE = 8.

Actually, put the NOX identification above. Old CPUs do not support the
cpuid instruction.

Map rodata and data+bss independently, and give them R and RW with
fillkpt_nox. The code is exactly the same as amd64's.

Define fillkpt_nox on i386, same as amd64.

But there is a difference in the way it is done here. If PAE is not enabled,
PDE_SIZE = 4, so there is no NOX bit set. If PAE is enabled, PDE_SIZE = 8,
so the NOX bit is set.

This works exactly as intended, since NOX does not exist in the non-PAE
case.

Fix the secondary CPUs bug in i386. Same as amd64.

Define killkpt, and don't use _RELOC. Same as amd64.

Bring some amd64 swag. No functional changes.

Split the {text+rodata} chunk in two separate chunks on x86. The
rodata segment now loses the large page optimization, gets mapped inside
the data segment, and therefore becomes RWX. It may break the build on
Xen.

Switch to C-style comments, and reduce a little the diff between i386 and
amd64. No functional changes.

Sync with HEAD

Use makeoptions_COPY_SYMTAB via opt_copy_symtab.h in sources.  Remove a hack
to set -DCOPY_SYMTAB from sys/conf/Makefile.kern.inc.  Remove unnecessary
dependencies too.

Rebase to HEAD as of a few days ago.

Reorganize symbol table embedding.  The existing option SYMTAB_SPACE is
replaced by the make option COPY_SYMTAB set to any value. The copy of
the symbol table is no longer put into a buffer in kern_ksyms.o, but a
small helper object. This object is build first with a dummy size, then
the kernel is linked to compute the real dimension of the symbol table
buffer. After that, the helper object is rebuild and the kernel linked
again.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Move the amd64 and i386 pcb to the bottom of the uarea, and move the
  kernel stack to the top.
Change the pcb layouts so that fpu save area is at the end and is
  64byte aligned ready for xsave (saving the ymm registers).
Welcome to 6.99.32

Minor fpu initialisation cleanups:
Set default CR) so that the FPU is enabled (unset CR0_EM) and initialise
  i386_fpu_present to 1.
No need to call the npx trap indirectly, rename to fpunda() to match amd64.
Remove the i386_fpu_exception variable and sysctl (It used to indicate
  which irq was used for fpu exceptions, but we only support 'internal'
  now).  Hopefully no one cares.
fpuinit() now only needs to clear TS before the fninit(). Apart from the
  checks for 486SX and the 'fdiv bug' this matches the amd64 version.
Exclude fpuinit() from XEN kernels, they don't call it - which rather begs
  the question as to whether it is needed at all!

Remove support for 'external' floating point units and the MS-DOS
  compatible method of handling floating point exceptions.
Make kernel support for teh fpu non-optional (486SX should still work).
Only 386 cpus support external fpu, and i386 support was removed years ago.
This means that the npx code no longer uses port 0xf0 or interupt 13.
All the "npx at isa" lines go from the configs, arch/i386/isa/npx.c
  is now mandatory for all i386 kernels.
I've renamed npxinit() to fpuinit() and npxinit_cpu() to fpuinit_cpu()
  to match the very similar amd64 functions.
The fpu of the boot cpu is now initialised by a direct call from
  cpu_configure(), this enables FP emulation for a 486SX.
  (for amd64 the cr0 values are set in locore.S and similar).
This fixes a long-standing bug in linux_setregs() - which did not
  save the fpu regsiters if they were active.
I've test booted a single cpu i386 kernel (using anita).
amd64 builds - none of teh changes should affect it.
The i386 XEN kernels build, but I'm not sure where they set cr0, and
  it might have got lost!

fix a comment (cpu_switch() -> cpu_switchto()) (Richard Hansen)

revert fpu/pcu changes until we figure out what's wrong; they cause random
freezes

Use the MI "pcu" framework for bookkeeping of npx/fpu states on x86.
This reduces the amount of MD code enormously, and makes it easier
to implement support for newer CPU features which require more fpu
state, or for fpu usage by the kernel.
For access to FPU state across CPUs, an xcall kthread is used now
rather than a dedicated IPI.
No user visible changes intended.

Whitespace, comment, NBPG -> PAGE_SIZE.

Whitespace.

Use END() markers, etc.  Pure ELF .symtab (size) changes.

Resync to 2012-11-19 00:00:00 UTC

Pull up following revision(s) (requested by chs in ticket #642):
	sys/arch/i386/i386/locore.S: revision 1.103
in osyscall, set the PSL_I bit into the correct field of the trapframe.
it was going into tf_eip instead of tf_eflags, which would sometimes
corrupt %eip and always return to user mode with interrupts disabled.
this was found with a netbsd 1.0 binary, and dsl@ points out that
this should also fix PR 41342.

Pull up following revision(s) (requested by chs in ticket #1810):
	sys/arch/i386/i386/locore.S: revision 1.103
in osyscall, set the PSL_I bit into the correct field of the trapframe.
it was going into tf_eip instead of tf_eflags, which would sometimes
corrupt %eip and always return to user mode with interrupts disabled.
this was found with a netbsd 1.0 binary, and dsl@ points out that
this should also fix PR 41342.

sync with head

in osyscall, set the PSL_I bit into the correct field of the trapframe.
it was going into tf_eip instead of tf_eflags, which would sometimes
corrupt %eip and always return to user mode with interrupts disabled.
this was found with a netbsd 1.0 binary, and dsl@ points out that
this should also fix PR 41342.

Restrict export of the tmpgdt symbol to XEN kernels

Spotted by uwe@

Retire XEN_COMPAT_030001 as detailed on port-xen@:

http://mail-index.netbsd.org/port-xen/2012/06/25/msg007431.html

The xen_p2m API comes next.

ok bouyer@.
Tested on i386 PAE and amd64 (Xen 3.3 on private test bed, and
Xen 3.4 for Amazon EC2).

FWIW, Amazon always reported:

hypervisor0 at mainbus0: Xen version 3.4.3-kaos_t1micro

multiple times for Europe and US West-1, so I guess they are now at
3.4 (32 and 64 bits).

rename the global variable "cpu" to "cputype" to avoid conflicting with
dtrace, which wants to use "cpu" as a local variable.

sync with head.

sync to latest -current.

Pull up following revision(s) (requested by jym in ticket #189):
	sys/arch/x86/include/psl.h: revision 1.7
	sys/arch/i386/i386/locore.S: revision 1.98
	sys/arch/amd64/acpi/acpi_wakecode.S: revision 1.11
	sys/arch/amd64/amd64/mptramp.S: revision 1.13
	sys/arch/i386/acpi/acpi_wakecode.S: revision 1.15
	sys/arch/i386/i386/mptramp.S: revision 1.23
	sys/arch/amd64/amd64/locore.S: revision 1.68
Set the CR0_AM bit so processes can enable alignment check errors under
x86 through PSL_AC bit.
ATF test incoming shortly.
PSL_AC is user-settable.

Mirror what is done for amd64 boot and ACPI wakeup code by setting
CR0_WP (write protection bit) early on boot. Although it is set later via
cpu_init(), this can help tracking down invalid writes to pages mapped
as read only from ring 0.

No regression observed when booting under anita (QEMU) or a P4 host.

Depending on your hardware or setup, you may trigger code paths I have
overlooked. So if your machine does not start properly, or you get
page faults early during boot, please report them to me.

Set the CR0_AM bit so processes can enable alignment check errors under
x86 through PSL_AC bit.

ATF test incoming shortly.

sync with head

sync to -current

sync to -current

Pull up the following revisions(s) (requested by bouyer in ticket #80):
	sys/arch/xen/x86/x86_xpmap.c:	revision 1.42
	sys/arch/x86/include/specialreg.h:	revision 1.56
	sys/arch/amd64/amd64/machdep.c:	revision 1.179
	sys/arch/i386/i386/locore.S:	revision 1.97
	sys/arch/i386/i386/machdep.c:	revision 1.723 via patch
	sys/arch/x86/include/cpu.h:	revision 1.49

Fix possible FPU registers corruption on context switches.
Fix type of pointers passed to some hypercalls.

sync to latest -current.

Follow locore.S and move FPU handling from x86_64_switch_context() to
x86_64_tls_switch(); raise IPL to IPL_HIGH in x86_64_switch_context()
and test ci_fpcurlwp to decide to disable FPU or not.
Change the Xen i386 context switch code to be like the amd64 one.

(xen) - remove the (*xpq_cpu)() shim.We hasten the %fs/%gs setup process during boot.Although this is hacky, it lets us use the non-xen specificpmap_pte_xxx() functions in pmap code (and others).

Sync with HEAD.

sync with head

Cure sync hiccups. Code with compile errors is not really useful, heh.

Sync with HEAD. TODO before merge:
- shortcut for suspend code in sysmon, when powerd(8) is not running.
Borrow ``xs_watch'' thread context?
- bug hunting in xbd + xennet resume. Rings are currently thrashed upon
resume, so current implementation force flush them on suspend. It's not
really needed.

Remove static branch prediction hints. They pessimize code for all CPUs
but Pentium IV. Discussed with ad@ and dsl@

sync with head

Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits.  Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

Apply patch, requested by dholland in ticket #1410:
	sys/arch/i386/i386/locore.S: patch
In cpu_switch, avoid flipping interrupts on while holding the
scheduler lock. Doing so can cause locking against oneself via
endtsleep(). Fixes PR kern/38183, where the overt symptom was
that LOCKDEBUG + INSTALL_LARGE would panic during boot.
Should fix PR 38183.

Sync with HEAD.

sync with head.

Welcome PAE inside i386 current.

This patch is inspired by work previously done by Jeremy Morse, ported by me
to -current, merged with the work previously done for port-xen, together with
additionals fixes and improvements.

PAE option is disabled by default in GENERIC (but will be enabled in ALL in
the next few days).

In quick, PAE switches the CPU to a mode where physical addresses become
36 bits (64 GiB). Virtual address space remains at 32 bits (4 GiB). To cope
with the increased size of the physical address, they are manipulated as
64 bits variables by kernel and MMU.

When supported by the CPU, it also allows the use of the NX/XD bit that
provides no-execution right enforcement on a per physical page basis.

Notes:

- reworked locore.S

- introduce cpu_load_pmap(), used to switch pmap for the curcpu. Due to the
different handling of pmap mappings with PAE vs !PAE, Xen vs native, details
are hidden within this function. This helps calling it from assembly,
as some features, like BIOS calls, switch to pmap_kernel before mapping
trampoline code in low memory.

- some changes in bioscall and kvm86_call, to reflect the above.

- the L3 is "pinned" per-CPU, and is only manipulated by a
reduced set of functions within pmap. To track the L3, I added two
elements to struct cpu_info, namely ci_l3_pdirpa (PA of the L3), and
ci_l3_pdir (the L3 VA). Rest of the code considers that it runs "just
like" a normal i386, except that the L2 is 4 pages long (PTP_LEVELS is
still 2).

- similar to the ci_pae_l3_pdir{,pa} variables, amd64's xen_current_user_pgd
becomes an element of cpu_info (slowly paving the way for MP world).

- bootinfo_source struct declaration is modified, to cope with paddr_t size
change with PAE (it is not correct to assume that bs_addr is a paddr_t when
compiled with PAE - it should remain 32 bits). bs_addrs is now a
void * array (in bootloader's code under i386/stand/, the bs_addrs
is a physaddr_t, which is an unsigned long).

- fixes in multiboot code (same reason as bootinfo): paddr_t size
change. I used Elf32_* types, use RELOC() where necessary, and move the
memcpy() functions out of the if/else if (I do not expect sym and str tables
to overlap with ELF).

- 64 bits atomic functions for pmap

- all pmap_pdirpa access are now done through the pmap_pdirpa macro. It
hides the L3/L2 stuff from PAE, as well as the pm_pdirpa change in
struct pmap (it now becomes a PDP_SIZE array, with or without PAE).

- manipulation of recursive mappings ( PDIR_SLOT_{,A}PTEs ) is done via
loops on PDP_SIZE.

See also http://mail-index.netbsd.org/port-i386/2010/07/17/msg002062.html

No objection raised on port-i386@ and port-xen@R for about a week.

XXX kvm(3) will be fixed in another patch to properly handle both PAE and !PAE
kernel dumps (VA => PA macros are slightly different, and need proper 64 bits
PA support in kvm_i386).

XXX Mixing PAE and !PAE modules may lead to unwanted/unexpected results. This
cannot be solved easily, and needs lots of thinking before being declared
safe (paddr_t/bus_addr_t size handling, PD/PT macros abstractions).

In Xen PAE case, fix argument size passed to init386(), by pushing the
upper bits onto stack (we do not expect first_avail to be above 4GiB, so
assume their value is 0).

Remove macros (PROC0PDIR and PROC0STACK) that were never used.

sync with head

- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places.  Reduce sys/user.h inclusions.

Remove IPL_LPT and IPL_IPI aliases, use the actual IPLs.
Fix some broken comments.

Sync with HEAD.

Remove closes 3 & 4 from my licence. Lots of thanks to Soren Jacobsen
for the booring work !

sync with head.

remove Xen2 support.
ok bouyer@

sync with head

Sync with HEAD.

Commit is split, to avoid a "too many arguments" protocol error.

PR kern/41342: BSDi binaries cause panic

XXX Manuel, please have a look as I am not sure what to do for XEN here!

sync with head.

Sync with HEAD.

Pull up following revision(s) (requested by ad in ticket #656):
	sys/arch/amd64/amd64/gdt.c: revision 1.21 via patch
	sys/arch/amd64/amd64/machdep.c: revision 1.129 via patch
	sys/arch/i386/i386/gdt.c: revision 1.47 via patch
	sys/arch/i386/i386/kvm86.c: revision 1.17 via patch
	sys/arch/i386/i386/locore.S: revision 1.85 via patch
	sys/arch/i386/i386/machdep.c: revision 1.666 via patch
	sys/arch/i386/i386/vector.S: revision 1.45 via patch
	sys/arch/i386/include/pcb.h: revision 1.47 via patch
	sys/arch/x86/include/pmap.h: revision 1.22 via patch
	sys/arch/x86/include/sysarch.h: revision 1.8 via patch
	sys/arch/x86/x86/pmap.c: revision 1.80 via patch
	sys/arch/x86/x86/sys_machdep.c: revision 1.17 via patch
	sys/compat/linux/arch/i386/linux_machdep.c: revision 1.143 via patch
	sys/kern/init_main.c: revision 1.384 via patch
PR port-i386/40143 Viewing an mpeg transport stream with mplayer causes crash
Fix numerous problems:
1. LDT updates are not atomic.
2. Number of processes running with private LDTs and/or I/O bitmaps
   is not capped. System with high maxprocs can be paniced.
3. LDTR can be leaked over context switch.
4. GDT slot allocations can race, giving the same LDT slot to two procs.
5. Incomplete interrupt/trap frames can be stacked.
6. In some rare cases segment faults are not handled correctly.

Add 2 event counters:

"x86", "io bitmap copy"
"x86", "ldt sync"

PR port-i386/40143 Viewing an mpeg transport stream with mplayer causes crash

Fix numerous problems:

1. LDT updates are not atomic.

2. Number of processes running with private LDTs and/or I/O bitmaps
   is not capped. System with high maxprocs can be paniced.

3. LDTR can be leaked over context switch.

4. GDT slot allocations can race, giving the same LDT slot to two procs.

5. Incomplete interrupt/trap frames can be stacked.

6. In some rare cases segment faults are not handled correctly.

printf -> panic so MP panics work correctly

Sync with HEAD.

Use "defopt MODULAR" in sys/conf/files, and #include "opt_modular.h"
in all kernel sources that use the MODULAR option.
Proposed in tech-kern on 18 Jan 2009.

Pull up following revision(s) (requested by ad in ticket #345):
	sys/arch/amd64/amd64/genassym.cf: revision 1.39
	sys/arch/i386/i386/genassym.cf: revision 1.79
	sys/arch/i386/i386/locore.S: revision 1.82
	sys/arch/x86/x86/x86_machdep.c: revision 1.26
Don't abort pageidlezero unless a realtime thread wants to run.

Sync with HEAD.

Sync with HEAD.

Update haad-dm branch to haad-dm-base2.

Don't abort pageidlezero unless a realtime thread wants to run.

Make the emulations, exec formats, coredump, NFS, and the NFS server
into modules. By and large this commit:

- shuffles header files and ifdefs
- splits code out where necessary to be modular
- adds module glue for each of the components
- adds/replaces hooks for things that can be installed at runtime

Pull up following revision(s) (requested by ad in ticket #74):
	sys/arch/i386/isa/npx.c: revision 1.131
	sys/arch/amd64/amd64/fpu.c: revision 1.28
	sys/arch/i386/i386/genassym.cf: revision 1.77
	sys/arch/i386/i386/autoconf.c: revision 1.93
	sys/arch/amd64/amd64/locore.S: revision 1.48
	sys/arch/amd64/amd64/machdep.c: revision 1.104
	sys/arch/i386/i386/machdep.c: revision 1.646
	sys/arch/amd64/amd64/genassym.cf: revision 1.38
	sys/arch/i386/i386/locore.S: revision 1.79
PR port-amd64/38293 panic: fp_save ipi didn't
Fix race conditions in FPU IPI handling.

LKM -> MODULAR

PR port-amd64/38293 panic: fp_save ipi didn't

Fix race conditions in FPU IPI handling.

Include opt_multiboot.h to allow the option to work.

Sync with wrstuden-revivesa-base-2.

Sync with HEAD.

Sync with head.

Replace lines beginning with assembler-style comments with c-style comments,
since '#' can be interpretted as a preprocessor directive.  Remove single
quote ''' from assembler-style comments, as the preprocessor may ignore
everything between them.

Fixes compilation with pcc.

Sync w/ -current. 34 merge conflicts to follow.

Sync with HEAD.

Also fix build.

sync with head

- Don't bother using sse to copy/zero pages on demand.  It turns out not
  to be worth it.
- If the machine has sse, re-enable zeroing pages in the idle loop and
  use the sse instructions so that we don't blow out the cache.

Sync with HEAD.

- sse2_zero_page: do 64-bytes (1 cache line) at a time.
- sse2_copy_page: increase from 16 to 32 bytes per loop.

fix typo and add level to the printf.

sync with head.

sync with head.

Simplify x86 identcpu code, and share between i386/amd64.

sprinkle END/IDTVEC_END.

- Give x86 BIOS boot the ability to load new style modules and pass them
  into the kernel. Based on a patch by jmcneill@, with many fixes and
  improvements by me.

- Put MEMORY_DISK_DYNAMIC and MODULAR into the GENERIC kernels, so that
  you can load miniroot.kmod from the boot blocks and boot into the
  installer!

cpu_switchto: if DIAGNOSTIC, assert not above IPL_SCHED.

Remove clause 3 and 4 from TNF licenses

- Make some entry/exit points preemption safe.
- Avoid mispredicted branches in Xsyscall.

Sync with HEAD.

sync with head.

sync with HEAD

sync with head.

Make context switch + syscall counters optionally per-CPU and accumulate
in schedclock() at "about 16 hz".

Sync with HEAD.

sync with head.

Merge the bouyer-xeni386 branch. This brings in PAE support to NetBSD xeni386
(domU only). PAE support is enabled by 'options PAE', see the new XEN3PAE_DOMU
and INSTALL_XEN3PAE_DOMU kernel config files.

See the comments in arch/i386/include/{pte.h,pmap.h} to see how it works.
In short, we still handle it as a 2-level MMU, with the second level page
directory being 4 pages in size. pmap switching is done by switching the
L2 pages in the L3 entries, instead of loading %cr3. This is almost required
by Xen, which handle the last L2 page (the one mapping 0xc0000000 - 0xffffffff)
in a very special way. But this approach should also work for native PAE
support if ever supported (in fact, the pmap should almost suport native
PAE, what's missing is bootstrap code in locore.S).

Sync with HEAD.

sync with head

Slightly better version of dumpsys from ad via simonb.

Sync with HEAD

Do the dumpsys/dodumpsys thing on i386...

dumpsys() now mimics cpu_switchto() (pushes a switchframe onto the stack)
for postmortem debugging.

From simonb.

Sync with HEAD

Work in progress on xeni386 PAE support:
Make xeni386 build with a 64bit paddr_t. For this vaddr_t vs paddr_t vs
pointers usages had to be clarified.
If 'options PAE' is present in a Xen3 kernel, switch paddr_t, pd_entry_t
and pt_entry_t to 64bits, and add the PAE entry in the __xen_guest ELF section.

Revert tmpstk size to 512 bytes, it was bumped to 1024 by mistake when
bouyer-xeni386 was merged.

Merge the bouyer-xeni386 branch to head, at tag bouyer-xeni386-merge1 (the
branch is still active and will see i386PAE support developement).
Sumary of changes:
- switch xeni386 to the x86/x86/pmap.c, and the xen/x86/x86_xpmap.c
  pmap bootstrap.
- merge back most of xen/i386/ to i386/i386
- change the build to reduce diffs between i386 and amd64 in file locations
- remove include files that were identical to the i386/amd64 counterparts,
  the build will find them via the xen-ma/machine link.

Sync with HEAD

- Fix a memory order problem with non-interlocked mutex release.
- Give kernel_lock its own cache line.

sync with HEAD

Sync with HEAD

Merge needed changes to genassym.cf and locore.S for xeni386 back to
arch/i386. Switch xeni386 to use the arch/i386 cpu.h.

i386:
	- make tss per-cpu.  this considerably speeds up context switch for,
	  at least, pentium4, where ltr instruction seems very slow.
i386, xen:
	- kill cpu_maxproc.
kvm86:
	- adapt to per-cpu tss.
	- cleanup and simplify.
	- move kvm86_mp_lock to more meaningful place.
	- disable preemption during a call.

Sync with HEAD.

Sync with head.

Sync with HEAD

sync with head.

Use __KERNEL_RCSID().  For these .S files, the following style was
adopted, a la .C files and <sys/cdefs.h>:
  *  move <machine/asm.h> to the top
  *  use __KERNEL_RCSID() immediately after it

Sync with HEAD.

Sync with HEAD.

sync with head

Merge from vmlocking.

Sync with HEAD.

Sync with HEAD.

Sync with HEAD.

Sync with HEAD

- Don't bother entering the debugger for WARNING: SPL NOT LOWERED ...
  It's nearly impossible to debug at that point. Just patch things
  up and continue.
- Don't assign to ci_ilevel to drop the IPL, it can cause deadlock.
  Use spllower() instead.

sync with head.

Sync with HEAD.

- Remove I486_CPU, I586_CPU, I686_CPU options. They buy us nothing and
  clutter the code significantly.
- Remove pccons.

Fix the fsbase/gsbase stuff to work in combination with RAS.
Still not working reliably on my AMD K7 for some reason.

Sync with HEAD

Sync with HEAD.

fsbase/gsbase:

- Fix a few bugs with it, in particular fork/exec handling.
- Store the descriptors in the PCB, not in the LWP.

- When computing the TSC frequency, call i8254_delay() and not DELAY().
- Use atomics to adjust the pmap reference count, instead of taking locks.
- Implement I386_{SET,GET}_{FS,GS}BASE, allowing %fs and %gs to be used
  as per-thread registers. This is compatible with FreeBSD.
- Run patches after we have attached CPUs, since we then know if the
  system is uniprocessor or not. Eliminates a lot of #ifdef MULTIPROCESSOR
  and makes running MP kernels on UP systems cheaper.
- Patch out many of the 'lock' prefixes to nops if uniprocessor.
- Do a wbinvd after patching to ensure that the trace/instruction cache
  is up to date.

sync with HEAD

sync with head.

Sync with HEAD.

Follow the merge of pmap.c on i386 and amd64 and move
pmap_init_tmp_pgtbl into arch/x86/x86/pmap.c. Modify the ACPI wakeup
code to restore CR4 before jumping back into kernel space as the large
page option might cover that.

Sync with HEAD.

Sync with head.

merge yamt-x86pmap branch.

- reduce differences between amd64 and i386.  notably, share pmap.c
  between them.  it makes several i386 pmap improvements available to
  amd64, including tlb shootdown reduction and bug fixes from Stephan Uphoff.
- implement deferred pmap switching for amd64.
- remove LARGEPAGES option.  always use large pages if available.
  also, make it work on amd64.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

allocate one more ptp for VAs which will be allocated by pmap_bootstrap.

Sync with head.

Sync with head.

fix off-by-one.

sync with head.

- move etext before rodata.  define __data_start at the start of
  .data section and use it instead of etext where appropriate.
- put .rodata.* into .rodata section as well.
- pmap_bootstrap: don't assume NBPD_L2 alignment.
- pmap_bootstrap: if DEBUG, print how many large pages and normal pages are
  used to map kernel text.

Sync with HEAD

Sync with HEAD.

fix recovery from DIAGNOSTIC check in syscall.

DO_DEFERRED_SWITCH, CHECK_DEFERRED_SWITCH: remove an unused argument.

x86 changes for pcc and LKMs.

- Replace most inline assembly with proper functions. As a side effect
  this reduces the size of amd64 GENERIC by about 120kB, and i386 by a
  smaller amount. Nearly all of the inlines did something slow, or something
  that does not need to be fast.
- Make curcpu() and curlwp functions proper, unless __GNUC__ && _KERNEL.
  In that case make them inlines. Makes curlwp LKM and preemption safe.
- Make bus_space and bus_dma more LKM friendly.
- Share a few more files between the ports.
- Other minor changes.

fix nkptp calculation.

remove hardcoded numbers of PTPs used for kernel image and bootstrap tables.

- sync with amd64.
- pmap_alloc_level: remove fast call special case.
- tweak some printf to work for both of LP64 and LP32.
- remove machdep.nkpde sysctl.
- remove automatic adjustment of nkpde for now.  will revisit later.

Sync with HEAD.

sync with head.

Sync with HEAD.

Merge most x86 changes from the vmlocking branch, except the threaded soft
interrupt stuff. This is mostly comprised of changes to the pmap modules to
work on multiprocessor systems without kernel_lock, and changes to speed up
tlb shootdowns.

Sync with HEAD.

Sync with HEAD.

cpu_switchto: fix a well dodgy bit of assembly that broke RAS.

sse2_copy_page:
	- save and restore a callee-saved register.
	- s/4096/PAGE_SIZE/

- When zeroing/copying pages, use SSE2 movtni to avoid polluting the cache.
- By default, align assembly routines on 32-byte starting boundaries.
- There are now 8 interrupt priority levels, half of which are softints.
  Update intrdefs.h to match.
- Always clear/set spinlock words - removes lots of ifdefs.
- Remove the horrible ci_self150 hack that I introduced.
- Overhaul how TLB shootdown is performed. Inspired by a similar change in
  OpenBSD but implemented quite differently. This should be a lot faster
  but I have not benchmarked it yet.

Sync with head.

- Increase the number of thread priorities from 128 to 256. How the space
  is set up is to be revisited.
- Implement soft interrupts as kernel threads. A generic implementation
  is provided, with hooks for fast-path MD code that can run the interrupt
  threads over the top of other threads executing in the kernel.
- Split vnode::v_flag into three fields, depending on how the flag is
  locked (by the interlock, by the vnode lock, by the file system).
- Miscellaneous locking fixes and improvements.

Sync with head.

Update to HEAD.

merge yamt-idlelwp branch.  asked by core@.  some ports still needs work.

from doc/BRANCHES:

	idle lwp, and some changes depending on it.

	1. separate context switching and thread scheduling.
	   (cf. gmcgarry_ctxsw)
	2. implement idle lwp.
	3. clean up related MD/MI interfaces.
	4. make scheduler(s) modular.

- Move setting curlwp back to cpu_switchto(). Necessary because if
  curlwp is made a register variable, we may also need to keep a
  copy in struct cpu_info for other CPUs to inspect. Okay yamt@.
- Clearing ci_need_resched is now done in mi_switch().

%cr0:0 is PE, not TS. Pointed out by yamt@.

- Tidy up slightly: remove pointless #ifdefs, make function descriptions
  consistent, remove checks for options that were removed 4+ years ago, ...
- Don't reload %cr0 or check for RAS if switching to a kthread.
- Don't try dropping the ipl using "movl $IPL_SCHED,CPUVAR(ILEVEL)". Causes
  deadlocks because the later drop of priority (possibly by mi_switch) can
  fail to notice pending IPIs. Just leave the level at IPL_IPI (for a very
  short time) at let it be dropped in mi_switch(). Spotted by yamt@.

cpu_switchto:

- Replace cli/sti with raising the priority level to IPL_IPI.
- Don't reload %cr0 unless necessary.

Improves timings for a pthread condvar benchmark I have by a further 45%
on a dual core system. Reviewed by yamt@.

cpu_switchto(): Pass the correct argument for ras_lookup(), fixes
crash with pthreads. From ad@

- sync with head.
- move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.

sync with head.

Correct a comment

Change the process/lwp flags seen by userland via sysctl back to the
P_*/L_* naming convention, and rename the in-kernel flags to avoid
conflict. (P_ -> PK_, L_ -> LW_ ). Add back the (now unused) LSDEAD
constant.

Restores source compatibility with pre-newlock2 tools like ps or top.

Reviewed by Andrew Doran.

fix a comment.

- separate context switching and thread scheduling.
- introduce idle lwp.
- change some related MD/MI interfaces and implement i386 version.

Merge newlock2 to head.

Call spllower() from the idle loop, not Xspllower().

For now always call sched_unlock_idle/sched_lock_idle. They will be
removed by yamt's cpu_switchto() changes.

Add x86_flush(): flush pipelines by doing a far return.

cpu_exit: be more conservative and only clear curlwp after TR has been
loaded.

- cpu_exit(): move 'cli' behind clearing curlwp to close a race with
  lwp_free(). Noted by yamt@.
- Don't bother calling lwp_exit2() any more.

Checkpoint work in progress.

sync with head.

Checkpoint work in progress.

sync with head.

Sync with head.

Remove the usage of Multiboot's "a.out kludge" to tell the boot loader to
reserve some more space for the BSS section than the binary says.  This
trick was used to leave room after the kernel's image to copy the symbol
table following the format required by ksyms_init.  (It was also used to
workaround a bug in the physical address fields of the binary, but this has
been long fixed.)  Yes, the MULTIBOOT_SYMTAB_SPACE option goes away; yay!

Instead, copy the required data after the kernel in a way that avoids having
to reserve space and use the new ksyms_init_explicit function to avoid the
need to construct a minimal ELF image.

Fixes ksyms when using an "unpatched" GRUB (one that does not contain the
fix to honour the "a.out kludge" for ELF images, even when present) -- i.e.
ddb and lkms.  As a side effect, the new code is much clearer to read and
digest.

Closes PR port-i386/32865.

- Redo LWP locking slightly and fix some races.
- Fix some locking botches.
- Make signal mask / stack per-proc for SA processes.
- Add _lwp_kill().

- Acquire/release sched_mutex in the correct places.
- Donate ci->ci_sched_mutex to newly scheduled LWPs.

sync with head

sync with head

fix a typo in a comment and a very minor KNF.

Merge from HEAD.

- apm.c -> apmbios.c and s/NAPM/NAPMBIOS/
- adjust to new function call signatures.

Fix order of biosbasemem and biosextmem order in a comment to match reality.
Closes PR kern/32082 by Dave J. Barnes.

sync with head.

Sync with head.

Sync with head.

Merge 2006-05-24 NetBSD-current into the "peter-altq" branch.

sync with head.

i386 and xen: move struct user to the highest address in uarea
and reduce UPAGES from 4 to 3 in the case of !NOREDZONE.

Fix some more comments.

Sync with head.

sync with head - hopefully this will work

Convert the code that fetches bootinfo information and stores it into the
kernel from assembler to C and add several comments to make things clearer.
I've been running with these changes for a couple of months without problems.

sync with head.

Implement support for 'The Multiboot Specification' so that i386 kernels
can be booted directly from Multiboot-compliant boot loaders (e.g. GRUB).
See the added multiboot(8) manual page for more information.

No objections in tech-kern@; only positive comments.

merge ktrace-lwp.

Sync with HEAD. Here we go again...

some assym cleanup.
- move copyin and friends from locore.S to their own file, copy.S.
  share it between i386 and xen.
- defparam KERNBASE and kill KERNBASE_LOCORE hack.
- add more symbols to assym.h and use it where appropriate.

sync with -current

Sync with HEAD.

merge yamt-km branch.
- don't use managed mappings/backing objects for wired memory allocations.
  save some resources like pv_entry.  also fix (most of) PR/27030.
- simplify kernel memory management API.
- simplify pmap bootstrap of some ports.
- some related cleanups.

sync with head.  xen and whitespace.  xen part is not finished.