CVS log for src/sys/arch/i386/i386/genassym.cf

Up to [cvs.NetBSD.org] / src / sys / arch / i386 / i386

Request diff between arbitrary revisions

Keyword substitution: kv
Default branch: MAIN

Eliminate l->l_ncsw and l->l_nivcsw.  From memory think they were added
before we had per-LWP struct rusage; the same is now tracked there.

Remove unused L_KPRIORITY.

Revert "x86: Add kthread_fpu_enter/exit support, take two -- forgot i386 bits."

kthread_fpu_enter/exit changes broke some hardware, unclear why, to
investigate before fixing and reapplying these changes.

x86: Add kthread_fpu_enter/exit support, take two -- forgot i386 bits.

Move some definitions. Add comment. No functional change.

Reduce diff between i386/i386/genassym.cf and amd64/amd64/genassym.cf. NFCI.

Sort lines. Add comment. No functional change.

Reduce diff between i386/i386/genassym.cf and amd64/amd64/genassym.cf. NFCI.

 - Whitespace fix.
 - Sort lines.

Remove duplicated IPL_SCHED. No functional change.

NetBSD/x86: Raise the number of interrupt sources per CPU from 32 to 56.

There has been no objection for three years.
    https://mail-index.netbsd.org/port-amd64/2019/09/22/msg003012.html
Implemented by nonaka@n.o, updated by me.

x86: Split most of pmap.h into pmap_private.h or vmparam.h.

This way pmap.h only contains the MD definition of the MI pmap(9)
API, which loads of things in the kernel rely on, so changing x86
pmap internals no longer requires recompiling the entire kernel every
time.

Callers needing these internals must now use machine/pmap_private.h.
Note: This is not x86/pmap_private.h because it contains three parts:

1. CPU-specific (different for i386/amd64) definitions used by...

2. common definitions, including Xenisms like xpmap_ptetomach,
   further used by...

3. more CPU-specific inlines for pmap_pte_* operations

So {amd64,i386}/pmap_private.h defines 1, includes x86/pmap_private.h
for 2, and then defines 3.  Maybe we should split that out into a new
pmap_pte.h to reduce this trouble.

No functional change intended, other than that some .c files must
include machine/pmap_private.h when previously uvm/uvm_pmap.h
polluted the namespace with pmap internals.

Note: This migrates part of i386/pmap.h into i386/vmparam.h --
specifically the parts that are needed for several constants defined
in vmparam.h:

VM_MAXUSER_ADDRESS
VM_MAX_ADDRESS
VM_MAX_KERNEL_ADDRESS
VM_MIN_KERNEL_ADDRESS

Since i386 needs PDP_SIZE in vmparam.h, I added it there on amd64
too, just to keep things parallel.

XenPV: in cpu_switchto(), reset ci_xen_clockf_usermode/ci_xen_clockf_pc,
in case a clock interrupt is deffered while we're switching lwp.
Fix a (rare) panic:
panic: kernel diagnostic assertion "p != NULL" failed: file "/usr/src/sys/kern/kern_clock.c", line 438
seen when xen_timer_handler() is called from the splx() at the end of
mi_switch()

Some devices (e.g. ixg in MSI-X mode) don't to have their handlers called
when no interrupt are pending. So add an extra ih_pending field
to struct intrhand, which is incremeted when the handler is not called because
of IPL level and reset to 0 when called. Check this in Xen's resume
assembly to call only handlers that are really pending.

Introduce Xen PVH support in GENERIC.
This is compiled in with
options XENPVHVM
x86 changes:
- add Xen section and xen pvh entry points to locore.S. Set vm_guest
  to VM_GUEST_XENPVH in this entry point.
  Most of the boot procedure (especially page table setup and switch to
  paged mode) is shared with native.
- change some x86_delay() to delay_func(), which points to x86_delay() for
  native/HVM, and xen_delay() for PVH

Xen changes:
- remove Xen bits from init_x86_64_ksyms() and init386_ksyms()
  and move to xen_init_ksyms(), used for both PV and PVH
- set ISA no-legacy-devices property for PVH
- factor out code from Xen's cpu_bootconf() to xen_bootconf()
  in xen_machdep.c
- set up a specific pvh_consinit() which starts with printk()
  (which uses a simple hypercall that is available early) and switch to
  xencons when we can use pmap_kenter_pa().

Merge the bouyer-xenpvh branch, bringing in Xen PV drivers support under HVM
guests in GENERIC.
Xen support can be disabled at runtime with
boot -c
disable hypervisor

Sync with bouyer-xenpvh-base2 (HEAD)

Switch to the new PTE naming. The old naming is now unused, remove it.

Mostly merge changes from HEAD upto 20200411

Get rid of xen-specific ci_x* interrupt handling:
- use the general SIR mechanism, reserving 3 more slots for IPL_VM, IPL_SCHED
  and IPL_HIGH
- remove specific handling from C sources, or change to ipending
- convert IPL number to SIR number in various places
- Remove XUNMASK/XPENDING in assembly or change to IUNMASK/IPENDING
- remove Xen-specific ci_xsources, ci_xmask, ci_xunmask, ci_xpending from
  struct cpu_info
- for now remove a KASSERT that there are no pending interrupts in
  idle_block(). We can get there with some software interrupts pending
  in autoconf XXX needs to be looked at.

Include ci_isources[] for XenPV too.
Adjust spllower() to XenPV needs, and switch XenPV to the native spllower().
Remove xen_spllower().

Remove VM_GUEST_XEN and define only Xen subtypes:
VM_GUEST_XENPV
VM_GUEST_XENPVH
VM_GUEST_XENHVM
VM_GUEST_XENPVHVM

Set vm_guest in the start routine, if it is hypervisor-specific (e.g Xen PV).
If vm_guest was not set early and we detect Xen in identify_hypervisor(),
assume it is VM_GUEST_XENHVM. Refine to VM_GUEST_PVXENHVM in
hypervisor_match().

Sync with head.

G/C LS{SLEEP,RUN,ONPROC}

LWP status manipulation was moved out of assembly long ago.

Back out previous.

Adaptive rwlocks proposed on tech-kern and working well on this branch
with vnode locks.

Sync with head.

Hopefully fix some problems seen with MP support on non-x86, in particular
where curcpu() is defined as curlwp->l_cpu:

- mi_switch(): undo the ~2007ish optimisation to unlock curlwp before
  calling cpu_switchto().  It's not safe to let other actors mess with the
  LWP (in particular l->l_cpu) while it's still context switching.  This
  removes l->l_ctxswtch.

- Move the LP_RUNNING flag into l->l_flag and rename to LW_RUNNING since
  it's now covered by the LWP's lock.

- Ditch lwp_exit_switchaway() and just call mi_switch() instead.  Everything
  is in cache anyway so it wasn't buying much by trying to avoid saving old
  state.  This means cpu_switchto() will never be called with prevlwp ==
  NULL.

- Remove some KERNEL_LOCK handling which hasn't been needed for years.

Fix a problem with intr_unmask() that can cause a forever-loop:
- When handling the source-is-masked case in the interrupt vector, set the
  interrupt bit in a new ci_imasked field and ensure the bit is cleared
  from ci_ipending.
- In intr_unmask(), transfer the bit from ci_imasked to ci_ipending for
  non-level-sensitive interrupts (the PIC does the work for us in the
  level-sensitive case), and only force pending interrupts to be processed
  in this case.  (In all cases, make sure the now-unmasked bit is cleared
  from ci_imasked.)

Before, the bit was left in ci_ipending so as not to use edge-triggered
interrupts while the source is masked, but Xspllower() relies on the
pending bits getting cleared.

Tested by forcing all wm(4) interrupts on my test system though an
intr_mask() / softint / intr_unmask() cycle and exercising the network
heavily.

Add intr_mask() and corresponding intr_unmask() calls that allow specific
interrupt lines / sources to be masked as needed (rather than making a
set of sources by IPL as with spl*()).

x86: abort pageidlezero unconditionally if there is something to run.

Rewrite the FPU code on x86. This greatly simplifies the logic and removes
the dependency on IPL_HIGH. NVMM is updated accordingly. Posted on
port-amd64 a week ago.

Bump the kernel version to 9.99.16.

Sync with HEAD

Pull up following revision(s) via patch (requested by nonaka in ticket #1210):

	sys/dev/hyperv/vmbusvar.h: revision 1.1
	sys/dev/hyperv/hvs.c: revision 1.1
	sys/dev/hyperv/if_hvn.c: revision 1.1
	sys/dev/hyperv/vmbusic.c: revision 1.1
	sys/arch/x86/x86/lapic.c: revision 1.69
	sys/arch/x86/isa/clock.c: revision 1.34
	sys/arch/x86/include/intrdefs.h: revision 1.22
	sys/arch/i386/conf/GENERIC: revision 1.1201
	sys/arch/x86/x86/hyperv.c: revision 1.1
	sys/arch/x86/include/cpu.h: revision 1.105
	sys/arch/x86/x86/x86_machdep.c: revision 1.124
	sys/arch/i386/conf/GENERIC: revision 1.1203
	sys/arch/amd64/amd64/genassym.cf: revision 1.74
	sys/arch/i386/conf/GENERIC: revision 1.1204
	sys/arch/amd64/conf/GENERIC: revision 1.520
	sys/arch/x86/x86/hypervreg.h: revision 1.1
	sys/arch/amd64/amd64/vector.S: revision 1.69
	sys/dev/hyperv/hvshutdown.c: revision 1.1
	sys/dev/hyperv/hvshutdown.c: revision 1.2
	sys/dev/usb/if_urndisreg.h: file removal
	sys/arch/x86/x86/cpu.c: revision 1.167
	sys/arch/x86/conf/files.x86: revision 1.107
	sys/dev/usb/if_urndis.c: revision 1.20
	sys/dev/hyperv/vmbusicreg.h: revision 1.1
	sys/dev/hyperv/hvheartbeat.c: revision 1.1
	sys/dev/hyperv/vmbusicreg.h: revision 1.2
	sys/dev/hyperv/hvheartbeat.c: revision 1.2
	sys/dev/hyperv/files.hyperv: revision 1.1
	sys/dev/ic/rndisreg.h: revision 1.1
	sys/arch/i386/i386/genassym.cf: revision 1.111
	sys/dev/ic/rndisreg.h: revision 1.2
	sys/dev/hyperv/hyperv_common.c: revision 1.1
	sys/dev/hyperv/hvtimesync.c: revision 1.1
	sys/dev/hyperv/hypervreg.h: revision 1.1
	sys/dev/hyperv/hvtimesync.c: revision 1.2
	sys/dev/hyperv/vmbusicvar.h: revision 1.1
	sys/dev/hyperv/if_hvnreg.h: revision 1.1
	sys/arch/x86/x86/lapic.c: revision 1.70
	sys/arch/amd64/amd64/vector.S: revision 1.70
	sys/dev/ic/ndisreg.h: revision 1.1
	sys/arch/amd64/conf/GENERIC: revision 1.516
	sys/dev/hyperv/hypervvar.h: revision 1.1
	sys/arch/amd64/conf/GENERIC: revision 1.518
	sys/arch/amd64/conf/GENERIC: revision 1.519
	sys/arch/i386/conf/files.i386: revision 1.400
	sys/dev/acpi/vmbus_acpi.c: revision 1.1
	sys/dev/hyperv/vmbus.c: revision 1.1
	sys/dev/hyperv/vmbus.c: revision 1.2
	sys/arch/x86/x86/intr.c: revision 1.144
	sys/arch/i386/i386/vector.S: revision 1.83
	sys/arch/amd64/conf/files.amd64: revision 1.112

separate RNDIS definitions from urndis(4) for use with Hyper-V NetVSC.

 -

Added Microsoft Hyper-V support.  It ported from OpenBSD and FreeBSD.
graphical console is not work on Gen.2 VM yet. To use the serial console,
enter "consdev com,0x3f8,115200" on efiboot.

 -

Add __diagused.

 -

PR/53984: Partial revert of modify lapic_calibrate_timer() in lapic.c r1.69.

 -

Update Hyper-V related drivers description.

 -

Remove unused definition.

 -

Rename the MODULE_*_HOOK() macros to MODULE_HOOK_*() as briefly
discussed on irc.
NFCI intended.

 -

commented out hvkvp entry.

 -

fix typo. pointed out by pgoyette@n.o.

 -

Use IDTVEC instead of NENTRY for handle_hyperv_hypercall.

 -

Rename the MODULE_*_HOOK() macros to MODULE_HOOK_*() as briefly
discussed on irc.

Start replacing the x86 PTE bits.

Drop PG_RO, PG_KR and PG_PROT, they are useless and create confusion.

Added Microsoft Hyper-V support.  It ported from OpenBSD and FreeBSD.

graphical console is not work on Gen.2 VM yet. To use the serial console,
enter "consdev com,0x3f8,115200" on efiboot.

We reorganise definitions for XEN source support as follows:

XEN - common sources required for baseline XEN support.
XENPV - sources required for support of XEN in PV mode.
XENPVHVM - sources required for support for XEN in HVM mode.
XENPVH - sources required for support for XEN in PVH mode.

Switch NetBSD/xen to use XEN api tag RELEASE-4.11.1

The headers for this api are in sys/external/mit/xen-include-public/dist/

Sync with HEAD, resolve a few conflicts

Excise XEN specific code out of x86/x86/intr.c into xen/x86/xen_intr.c

While at it, separate the source function tracking so that the interrupt
paths are truly independant.

Use weak symbol exporting to provision for future PVHVM co-existence
of both files, but with independant paths. Introduce assembler code
such that in a unified scenario, native interrupts get first priority
in spllower(), followed by XEN event callbacks. IPL management and
semantics are unchanged - native handlers and xen callbacks are
expected to maintain their ipl related semantics.

In summary, after this commit, native and XEN now have completely
unrelated interrupt handling mechanisms, including
intr_establish_xname() and assembler stubs and intr handler
management.

Happy Christmas!

Pullup the following revisions via patch, requested by maxv in ticket #629:

	sys/arch/amd64/amd64/genassym.cf		1.63,1.64
	sys/arch/amd64/amd64/locore.S			1.144
	sys/arch/amd64/amd64/machdep.c			1.281-1.283
	sys/arch/i386/i386/genassym.cf			1.105-1.106
	sys/arch/i386/i386/locore.S			1.155
	sys/arch/i386/i386/machdep.c			1.802 (adapted),1.803
	sys/arch/x86/include/cpu.h			1.85
	sys/arch/x86/x86/intr.c				1.115-1.116
	sys/arch/x86/x86/pmap.c				1.275
	sys/arch/x86/x86/sys_machdep.c			1.45
	sys/arch/xen/x86/cpu.c				1.117

Stop sharing the double-fault stack.
Merge the TSS structures into one single cpu_tss structure, and
allocate it dynamically.

Declare IOMAP_VALIDOFF, not to use ci_tss pointers.

Allocate the TSS area dynamically. This way cpu_info and cpu_tss can be
put in separate pages.

Group the different TSSes into a cpu_tss structure. And pack this
structure to make sure there is no padding between 'tss' and 'iomap'.

update from HEAD

Remove TRAPLOG from i386. Nowadays there are better instrumentation tools,
in both software and hardware.

Sync with HEAD

Remove references to PSL_VM (implicitly vm86).

Move freebsd_machdep.h into sys/compat/freebsd, and don't install it. Now,
the compat_freebsd files are all contained in sys/compat/freebsd.

Unlink svr4_machdep.h.

2302677

file genassym.cf was added on branch perseant-stdc-iso10646 on 2017-07-16 14:02:49 +0000

Unify the xen and native x86/ interrupt setup functions and
spl traversal data structures.

This is towards PVHVM.

Sync with HEAD

Have MI genassym.cf.

Replace a constant in ldscript.

Rebase to HEAD as of a few days ago.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

Remove all references to MDL_USEDFPU and deferred fpu initialisation.
The cost of zeroing the save area on exec is minimal.
This stops the FP registers of a random process being used the first
  time an lwp uses the fpu.
sendsig_siginfo() and get_mcontext() now unconditionally copy the FP
registers.
I'll remove the double-copy for signal handlers soon.
get_mcontext() might have been leaking kernel memory to userspace - and
  may still do so if i386_use_fxsave is false (short copies).

revert fpu/pcu changes until we figure out what's wrong; they cause random
freezes

Use the MI "pcu" framework for bookkeeping of npx/fpu states on x86.
This reduces the amount of MD code enormously, and makes it easier
to implement support for newer CPU features which require more fpu
state, or for fpu usage by the kernel.
For access to FPU state across CPUs, an xcall kthread is used now
rather than a dedicated IPI.
No user visible changes intended.

Resync to 2012-11-19 00:00:00 UTC

sync with head

Fix build.
I've removed 'option apmbios' so config no longer generates apmbios.h
Not to be confused with dev/apm/apmbios.h :-)

Remove the obvious parts of i386 Advanced power management 'apm' support.
This is the code that predates ACPI, and might once have been able to
  power down some laptops.
It hasn't been compiled for ages (it isn't it i386/ALL or any other
  standard kernel) and hasn't worked for even longer.
The APM specification was made obsolete by ACPI before it was widely
  implemented.
This will allow some other, even more dubious code be removed.
Unfortunately apmbios.h is used by the world !

sync with head.

Pull up following revision(s) (requested by rmind in ticket #202):
	sys/arch/x86/include/cpuvar.h: revision 1.46
	sys/arch/xen/include/xenpmap.h: revision 1.34
	sys/arch/i386/include/param.h: revision 1.77
	sys/arch/x86/x86/pmap_tlb.c: revision 1.5
	sys/arch/x86/x86/pmap_tlb.c: revision 1.6
	sys/arch/i386/i386/genassym.cf: revision 1.92
	sys/arch/xen/x86/cpu.c: revision 1.91
	sys/arch/x86/x86/pmap.c: revision 1.177
	sys/arch/xen/x86/xen_pmap.c: revision 1.21
	sys/arch/x86/acpi/acpi_wakeup.c: revision 1.31
	sys/kern/subr_kcpuset.c: revision 1.5
	sys/arch/amd64/include/param.h: revision 1.18
	sys/sys/kcpuset.h: revision 1.5
	sys/arch/x86/x86/mtrr_i686.c: revision 1.26
	sys/arch/x86/x86/mtrr_i686.c: revision 1.27
	sys/arch/xen/x86/x86_xpmap.c: revision 1.43
	sys/arch/x86/x86/cpu.c: revision 1.98
	sys/arch/amd64/amd64/mptramp.S: revision 1.14
	sys/kern/sys_sched.c: revision 1.42
	sys/arch/amd64/amd64/genassym.cf: revision 1.50
	sys/arch/i386/i386/mptramp.S: revision 1.24
	sys/arch/x86/include/pmap.h: revision 1.52
	sys/arch/x86/include/cpu.h: revision 1.50
- Convert x86 MD code, mainly pmap(9) e.g. TLB shootdown code, to use
  kcpuset(9) and thus replace hardcoded CPU bitmasks.  This removes the
  limitation of maximum CPUs.
- Support up to 256 CPUs on amd64 architecture by default.
Bug fixes, improvements, completion of Xen part and testing on 64-core
AMD Opteron(tm) Processor 6282 SE (also, as Xen HVM domU with 128 CPUs)
by Manuel Bouyer.
- pmap_tlb_shootdown: do not overwrite tp_cpumask with pm_cpus, but merge
  like pm_kernel_cpus.  Remove unecessary intersection with kcpuset_running.
  Do not reset tp_userpmap if pmap_kernel().
- Remove pmap_tlb_mailbox_t wrapping, which is pointless after recent changes.
- pmap_tlb_invalidate, pmap_tlb_intr: constify for packet structure.
i686_mtrr_init_first: handle the case when there are no variable-size MTRR
registers available (i686_mtrr_vcnt == 0).

sync to latest -current.

- Convert x86 MD code, mainly pmap(9) e.g. TLB shootdown code, to use
  kcpuset(9) and thus replace hardcoded CPU bitmasks.  This removes the
  limitation of maximum CPUs.

- Support up to 256 CPUs on amd64 architecture by default.

Bug fixes, improvements, completion of Xen part and testing on 64-core
AMD Opteron(tm) Processor 6282 SE (also, as Xen HVM domU with 128 CPUs)
by Manuel Bouyer.

sync with head

merge to -current.

switch from xen3-public to xen-public.

Sync with HEAD. Most notably: uvm/pmap work done by rmind@, and MP Xen
work of cherry@.

No regression observed on suspend/restore.

#include <sys/bus.h> instead of <machine/bus.h>.

Catchup with rmind-uvmplock merge.

Welcome to 5.99.53!  Merge rmind-uvmplock branch:

- Reorganize locking in UVM and provide extra serialisation for pmap(9).
  New lock order: [vmpage-owner-lock] -> pmap-lock.

- Simplify locking in some pmap(9) modules by removing P->V locking.

- Use lock object on vmobjlock (and thus vnode_t::v_interlock) to share
  the locks amongst UVM objects where necessary (tmpfs, layerfs, unionfs).

- Rewrite and optimise x86 TLB shootdown code, make it simpler and cleaner.
  Add TLBSTATS option for x86 to collect statistics about TLB shootdowns.

- Unify /dev/mem et al in MI code and provide required locking (removes
  kernel-lock on some ports).  Also, avoid cache-aliasing issues.

Thanks to Andrew Doran and Joerg Sonnenberger, as their initial patches
formed the core changes of this branch.

Cure sync hiccups. Code with compile errors is not really useful, heh.

- Fix tlbflushg() to behave like tlbflush(), if page global extension (PGE)
  is not (yet) enabled.  This fixes the issue of stale TLB entry, experienced
  early on boot, when PGE is not yet set on primary CPU.
- Rewrite i386/amd64 TLB interrupt handlers in C (only stubs are in assembly),
  which simplifies and unifies (under x86) code, plus fixes few bugs.
- cpu_attach: remove assignment to cpus_running, as primary CPU might not be
  attached first, which causes reset (and thus missed secondary CPUs).

sync with head

Move counting of faults, traps, intrs, soft[intr]s, syscalls, and nswtch
from uvmexp to per-cpu cpu_data and move them to 64bits.  Remove unneeded
includes of <uvm/uvm_extern.h> and/or <uvm/uvm.h>.

sync with head.

sync with head

Sync with HEAD.

On x86, change the bus_space_tag_t to a pointer to a struct
bus_space_tag.  For now, bus_space_tag's only member is
bst_type, the type of space, which is either X86_BUS_SPACE_IO
or X86_BUS_SPACE_MEM.  In the future, new bus_space_tag members
will refer to override-functions installed by a new function,
bus_space_tag_create(9).

Add pointers to constant struct bus_space_tag, x86_bus_space_io and
x86_bus_space_mem.  Use them to replace most uses of X86_BUS_SPACE_IO
and X86_BUS_SPACE_MEM.

Add an x86-specific bus_space_is_equal(9) implementation that compares
the two tags' bst_type.

Apply renovated patch to significantly reduce TLB shootdowns in x86 pmap,
also provide TLBSTATS option to measure and track TLB shootdowns.  Details:

http://mail-index.netbsd.org/port-i386/2009/01/11/msg001018.html

Patch from Andrew Doran, proposed on tech-x86 [sic], in January 2009.

XXX: amd64 and xen are not yet; work in progress.

This patch fixes the NX regression issue observed on amd64 kernels, where
per-page execution right was disabled (therefore leading to the inability
of the kernel to detect fraudulent use of memory mappings marked as not
being executable).

- replace cpu_feature and ci_feature_flags variables by cpu_feature and
ci_feat_val arrays. This makes it cleaner and brings kernel code closer
to the design of cpuctl(8). A warning will be raised for each CPU that
does not expose the same features as the Boot Processor (BP).

- the blacklist of CPU features is now a macro defined in the
specialreg.h header, instead of hardcoding it inside MD initialization
code; fix comments.

- replace checks against CPUID_TSC with the cpu_hascounter() function.

- clean up the code in init_x86_64(), as cpu_feature variables are set
inside cpu_probe().

- use cpu_init_msrs() for i386. It will be eventually used later for NX
feature under i386 PAE kernels.

- remove code that checks for CPUID_NOX in amd64 mptramp.S, this is already
performed by cpu_hatch() through cpu_init_msrs().

- remove cpu_signature and feature_flags members from struct mpbios_proc
(they were never used).

This patch was tested with i386 MONOLITHIC, XEN3PAE_DOM0 and XEN3_DOM0 under
a native i386 host, and amd64 GENERIC, XEN3_DOM0 via QEMU virtual machines.

XXX Should kernel rev be bumped?

XXX A similar patch should be pulled-up for NetBSD-5, hopefully tomorrow.

sync with head

Remove a duplicate entry for PTE_BASE.

While here, introduce PDP_SIZE and PDE_SIZE. They will be used by asm code
to make it more generic (PAE related).

- Use uvm_lwp_setuarea() instead of directly setting address to lwp_t::l_addr.
- Replace most remaining uses of l_addr with uvm_lwp_getuarea() or lwp_getpcb().
- Amend assembly in ports where it accesses PCB via struct user.
- Rename L_ADDR to L_PCB in few places.  Reduce sys/user.h inclusions.

Remove IPL_LPT and IPL_IPI aliases, use the actual IPLs.
Fix some broken comments.

Use lwp_getpcb() on x86 MD code, clean from struct user usage.

Sync with HEAD.

sync with head.

remove Xen2 support.
ok bouyer@

sync with head.

Pull up following revision(s) (requested by ad in ticket #345):
	sys/arch/amd64/amd64/genassym.cf: revision 1.39
	sys/arch/i386/i386/genassym.cf: revision 1.79
	sys/arch/i386/i386/locore.S: revision 1.82
	sys/arch/x86/x86/x86_machdep.c: revision 1.26
Don't abort pageidlezero unless a realtime thread wants to run.

Sync with HEAD.

Sync with HEAD.

!defined(_LKM) -> defined(_KERNEL_OPT)

Update haad-dm branch to haad-dm-base2.

Don't abort pageidlezero unless a realtime thread wants to run.

Pull up following revision(s) (requested by ad in ticket #74):
	sys/arch/i386/isa/npx.c: revision 1.131
	sys/arch/amd64/amd64/fpu.c: revision 1.28
	sys/arch/i386/i386/genassym.cf: revision 1.77
	sys/arch/i386/i386/autoconf.c: revision 1.93
	sys/arch/amd64/amd64/locore.S: revision 1.48
	sys/arch/amd64/amd64/machdep.c: revision 1.104
	sys/arch/i386/i386/machdep.c: revision 1.646
	sys/arch/amd64/amd64/genassym.cf: revision 1.38
	sys/arch/i386/i386/locore.S: revision 1.79
PR port-amd64/38293 panic: fp_save ipi didn't
Fix race conditions in FPU IPI handling.

Finish preparation to new interface.
New interface not yet used by default. It needs some testing first.

PR port-amd64/38293 panic: fp_save ipi didn't

Fix race conditions in FPU IPI handling.

Sync with HEAD.

Sync with HEAD.

Sync with HEAD.

Remove advertising clause for UCB in various genassym.cf files,
which were derived from genassym.c in 4.4BSD-Lite2 (or 386BSD).
Closes PR misc/39573.  Approved by martin@.

Sync with wrstuden-revivesa-base-2.

Sync with head.

Remove "struct device" from "struct pic", where it was only real
for ioapics and faked up for others. Add it to "struct ioapic_softc"
for now, until device/softc get split.
This required all typecasts between "struct pic" and "struct ioapic_softc"
to be replaced, I hope I got them all.
functionally tested on i386, compile-tested on xen, untested on amd64

Sync w/ -current. 34 merge conflicts to follow.

sync with head.

Sync with HEAD.

Also fix build.

Remove ref to uvm.page_idle_zero

sync with head

Sync with HEAD.

need CPU_INFO_NTRAP

sync with head.

sync with head.

Don't reload LDTR unless a new value, which only happens for USER_LDT.

Share cpu.h between the x86 ports.

Simplify x86 identcpu code, and share between i386/amd64.

Improve x86 tsc handling:

- Ditch the cross-CPU calibration stuff. It didn't work properly, and it's
  near impossible to synchronize the CPUs in a running system, because bus
  traffic will interfere with any calibration attempt, messing up the
  timings.

- Only enable the TSC on CPUs where we are sure it does not drift. If we are
  On a known good CPU, give the TSC high timecounter quality, making it the
  default.

- When booting CPUs, detect TSC skew and account for it. Most Intel MP
  systems have synchronized counters, but that need not be true if the
  system has a complicated bus structure. As far as I know, AMD systems
  do not have synchronized TSCs and so we need to handle skew.

- While an AP is waiting to be set running, try and make the TSC drift by
  entering a reduced power state. If we detect drift, ensure that the TSC
  does not get a high timecounter quality. This should not happen and is
  only for safety.

- Make cpu_counter() stuff LKM safe.

Add support for kernel preeemption to the i386 and amd64 ports. Notes:

- I have seen one isolated panic in the x86 pmap, but otherwise i386
  seems stable with preemption enabled.

- amd64 is missing the FPU handling changes and it's not yet safe to
  enable it there.

- The usual level for kern.sched.kpreempt_pri will be 128 once enabled
  by default. For testing, setting it to 0 helps to shake out bugs.

Remove clause 3 and 4 from TNF licenses

+L_NOPREEMPT, L_DOPREEMPT

Access Xen's vcpu info structure per-CPU.
Tested on i386 and amd64 (both dom0 and domU) by me.
Xen2 tested (both dom0 and domU) by bouyer.
OK bouyer

Sync with HEAD.

Correct pasto in the cc_microtime defs. From tsutsui@.

sync with head.

sync with HEAD

sync with head.

Make context switch + syscall counters optionally per-CPU and accumulate
in schedclock() at "about 16 hz".

Implement an optimized, preemption-safe asm version of tsc_get_timecount().
The C version needs work to be preemption safe. Cuts the clock cycles
for microtime() from 950 down to 300 on a Pentium D.

revert the rest of lazy mapping code.

Sync with HEAD.

sync with head

Merge the bouyer-xeni386 branch to head, at tag bouyer-xeni386-merge1 (the
branch is still active and will see i386PAE support developement).
Sumary of changes:
- switch xeni386 to the x86/x86/pmap.c, and the xen/x86/x86_xpmap.c
  pmap bootstrap.
- merge back most of xen/i386/ to i386/i386
- change the build to reduce diffs between i386 and amd64 in file locations
- remove include files that were identical to the i386/amd64 counterparts,
  the build will find them via the xen-ma/machine link.

Change xeni386 build to match xenamd64:
- machine/ points to xen/include/i386
- remove includes that were identical to the i386/include/ ones; the build
  will find them though the xen-ma/machine link.
- include xen files using xen/ not machine/

sync with HEAD

Sync with HEAD

Merge needed changes to genassym.cf and locore.S for xeni386 back to
arch/i386. Switch xeni386 to use the arch/i386 cpu.h.

i386:
	- make tss per-cpu.  this considerably speeds up context switch for,
	  at least, pentium4, where ltr instruction seems very slow.
i386, xen:
	- kill cpu_maxproc.
kvm86:
	- adapt to per-cpu tss.
	- cleanup and simplify.
	- move kvm86_mp_lock to more meaningful place.
	- disable preemption during a call.

Sync with HEAD

Sync with HEAD.

Sync with head.

Add new IPI for saving CPU state explicitly, share high-level part of
ACPI wakeup code and teach it how to start the APs again. As a side
effect the CPU_START interface allows choosing between different
bootstrap codes more easily now.

Sync with HEAD.

Sync with HEAD.

sync with head

Sync with HEAD.

Sync with HEAD.

Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

Sync with HEAD.

Sync with HEAD.

Sync with HEAD

sync with head.

- Remove I486_CPU, I586_CPU, I686_CPU options. They buy us nothing and
  clutter the code significantly.
- Remove pccons.

Sync with HEAD

Sync with HEAD.

fsbase/gsbase:

- Fix a few bugs with it, in particular fork/exec handling.
- Store the descriptors in the PCB, not in the LWP.

- When computing the TSC frequency, call i8254_delay() and not DELAY().
- Use atomics to adjust the pmap reference count, instead of taking locks.
- Implement I386_{SET,GET}_{FS,GS}BASE, allowing %fs and %gs to be used
  as per-thread registers. This is compatible with FreeBSD.
- Run patches after we have attached CPUs, since we then know if the
  system is uniprocessor or not. Eliminates a lot of #ifdef MULTIPROCESSOR
  and makes running MP kernels on UP systems cheaper.
- Patch out many of the 'lock' prefixes to nops if uniprocessor.
- Do a wbinvd after patching to ensure that the trace/instruction cache
  is up to date.

sync with HEAD

sync with head.

Sync with HEAD.

Follow the merge of pmap.c on i386 and amd64 and move
pmap_init_tmp_pgtbl into arch/x86/x86/pmap.c. Modify the ACPI wakeup
code to restore CR4 before jumping back into kernel space as the large
page option might cover that.

Sync with HEAD.

Sync with head.

merge yamt-x86pmap branch.

- reduce differences between amd64 and i386.  notably, share pmap.c
  between them.  it makes several i386 pmap improvements available to
  amd64, including tlb shootdown reduction and bug fixes from Stephan Uphoff.
- implement deferred pmap switching for amd64.
- remove LARGEPAGES option.  always use large pages if available.
  also, make it work on amd64.

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree.  Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches.  The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

Fix merge errors.

Sync with head.

Sync with head.

whitespace changes to reduce diffs.

sync with head.

Sync with HEAD

Sync with HEAD.

x86 changes for pcc and LKMs.

- Replace most inline assembly with proper functions. As a side effect
  this reduces the size of amd64 GENERIC by about 120kB, and i386 by a
  smaller amount. Nearly all of the inlines did something slow, or something
  that does not need to be fast.
- Make curcpu() and curlwp functions proper, unless __GNUC__ && _KERNEL.
  In that case make them inlines. Makes curlwp LKM and preemption safe.
- Make bus_space and bus_dma more LKM friendly.
- Share a few more files between the ports.
- Other minor changes.

ci_astpending is no more.

remove hardcoded numbers of PTPs used for kernel image and bootstrap tables.

- sync with amd64.
- pmap_alloc_level: remove fast call special case.
- tweak some printf to work for both of LP64 and LP32.
- remove machdep.nkpde sysctl.
- remove automatic adjustment of nkpde for now.  will revisit later.

Sync with HEAD.

sync with head.

Sync with HEAD.

Merge most x86 changes from the vmlocking branch, except the threaded soft
interrupt stuff. This is mostly comprised of changes to the pmap modules to
work on multiprocessor systems without kernel_lock, and changes to speed up
tlb shootdowns.

- Add ci_cpumask and use in preference to (1 << ci_cpuid). Some processors
  are bad at shifting by non-constant amounts.
- pmap_tlb_shootdown() must be called with preemption disabled.
- Defer waiting for tlb shootdown to complete after kenter_pa()/kremove().
  Spin in pmap_update() and in pmap_detactivate(), in case the LWP has been
  preempted
- When preparing to send a multicast shootdown IPI, avoid scanning the list
  of CPUs if the pmap's bitmask indicates that it's only active locally.

- When zeroing/copying pages, use SSE2 movtni to avoid polluting the cache.
- By default, align assembly routines on 32-byte starting boundaries.
- There are now 8 interrupt priority levels, half of which are softints.
  Update intrdefs.h to match.
- Always clear/set spinlock words - removes lots of ifdefs.
- Remove the horrible ci_self150 hack that I introduced.
- Overhaul how TLB shootdown is performed. Inspired by a similar change in
  OpenBSD but implemented quite differently. This should be a lot faster
  but I have not benchmarked it yet.

Sync with head.

- Remove the interrupt priority range and use 'kernel RT' instead,
  since only soft interrupts are threaded.
- Rename l->l_pinned to l->l_switchto. It might be useful for (re-)
  implementing SA or doors.
- Simplify soft interrupt dispatch so MD code is doing as little as
  possible that is new.

- Increase the number of thread priorities from 128 to 256. How the space
  is set up is to be revisited.
- Implement soft interrupts as kernel threads. A generic implementation
  is provided, with hooks for fast-path MD code that can run the interrupt
  threads over the top of other threads executing in the kernel.
- Split vnode::v_flag into three fields, depending on how the flag is
  locked (by the interlock, by the vnode lock, by the file system).
- Miscellaneous locking fixes and improvements.

Sync with head.

Update to HEAD.

merge yamt-idlelwp branch.  asked by core@.  some ports still needs work.

from doc/BRANCHES:

	idle lwp, and some changes depending on it.

	1. separate context switching and thread scheduling.
	   (cf. gmcgarry_ctxsw)
	2. implement idle lwp.
	3. clean up related MD/MI interfaces.
	4. make scheduler(s) modular.

PK_SYSTEM -> LW_SYSTEM

remove L_FORW and L_BACK.

- sync with head.
- move sched_changepri back to kern_synch.c as it doesn't know PPQ anymore.

sync with head.

Change the process/lwp flags seen by userland via sysctl back to the
P_*/L_* naming convention, and rename the in-kernel flags to avoid
conflict. (P_ -> PK_, L_ -> LW_ ). Add back the (now unused) LSDEAD
constant.

Restores source compatibility with pre-newlock2 tools like ps or top.

Reviewed by Andrew Doran.

- separate context switching and thread scheduling.
- introduce idle lwp.
- change some related MD/MI interfaces and implement i386 version.

Merge newlock2 to head.

If running on a PPro or later, at boot patch in versions of spllower() and
similar that use cmpxchg8b instead of cli/sti. Cuts the clock cycles for
splx() by a factor of ~6 on the P4, and ~3 on the PIII when bracketed by
serializing instructions (and hopefully more when not).

Sync with head.

Checkpoint work in progress.

sync with head.

Checkpoint work in progress.

sync with head.

- pass intrframe by-pointer, not by-value.
- make i386 and xen use per-cpu interrupt stack.

xen part is reviewed by Manuel Bouyer.

Checkpoint work in progress.

Export/remove new symbols to asm code.

Add updated locking primatives.

sync with head

sync with head

Merge from HEAD.

- apm.c -> apmbios.c and s/NAPM/NAPMBIOS/
- adjust to new function call signatures.

sync with head.

Sync with head.

Sync with head.

Merge 2006-05-24 NetBSD-current into the "peter-altq" branch.

sync with head.

i386 and xen: move struct user to the highest address in uarea
and reduce UPAGES from 4 to 3 in the case of !NOREDZONE.

merge ktrace-lwp.

Sync with HEAD. Here we go again...

some assym cleanup.
- move copyin and friends from locore.S to their own file, copy.S.
  share it between i386 and xen.
- defparam KERNBASE and kill KERNBASE_LOCORE hack.
- add more symbols to assym.h and use it where appropriate.

compat code reorg. Other archs will need similar changes...

handle M_EXT_LAZY in i386 MD in_cksum.

Fix the sync with head I botched.

Sync with HEAD.

Sync with HEAD

defer pmap switching until it's really needed
to avoid frequent loading of cr3 register, which involves tlb flush.

with some fixes/improvements from Stephan Uphoff and Bang Jun-Young.

Remove p_nras from struct proc - use LIST_EMPTY(&p->p_raslist) instead.
Remove p_raslock and rename p_lwplock p_lock (one lock is enough).
Simplify window test when adding a ras and correct test on VM_MAXUSER_ADDRESS.
Avoid unpredictable branch in i386 locore.S
(pad fields left in struct proc to avoid kernel bump)

use the real linux_rt_sigreturn.

Block level-triggered interrupts at the ioapic if they are deferred.
Avoids interrupt storms seen on some systems. Many thanks to
Stoned Elipot for testing.

Use PAGE_SIZE rather than NBPG.

Merge the nathanw_sa branch.

Sync with HEAD.

add offsets for linux_rt_sigframe

Add P_MD_ASTPENDING for the benefit of locore.s after recent changes.

New interrupt code. The basic idea behind it is to hide the differences
in interrupt controllers in struct pic, and try to keep as much
common code as possible. At the lowest (asm) level, this is done
with CPP macros.

The main structure is now struct intrsource, describing an established
interrupt line, of any kind (soft/hard local apic/legacy apic/IO apic).
For quick masking, there may be a maximum of 32 sources per CPU.
Sources can be assigned to any CPU in the MP case, though currently they
all go to the boot CPU.

L_CPU is relative to a struct lwp, not a struct proc.

Catch up to -current.

sync kqueue with -current; this includes merge of gehenna-devsw branch,
merge of i386 MP branch, and part of autoconf rototil work

Merge Bill Sommerfeld's i386 MP branch. This code has some known
caveats, but works quite well in a lot of MP cases, and all
UP cases that I have tested. Parts of this will hopefully be
reworked in the not-too-distant future.

Catch up to -current.

sync kqueue branch with HEAD

SMP branch resync.  Mostly RAS support.

catch up with -current.

RAS support for i386.

Catch up to -current.

Purge SAF_UPCALL.

catch up with -current.

No longer need to pull in lwp.h; proc.h pulls it in for us.

Resynch with -current.

During native signal delivery (and iBCS2, since it uses the native
sigcode), arrange to have the signal handler invoked directly, using
the trampoline only for the return path, saving a call insn.  Play
some other stack trickery in the trampoline to turn 2 pushl's into
one movl.

catch up with -current on kqueue branch

Catch up to -current.

Catch up with -current.  (commons elimination, changes to MI pci framework)

use _KERNEL_OPT rather than _KERNEL && !_LKM

Add options TRAPLOG:

When enabled, each cpu gets a ring buffer; on every trap entry, we add
an entry to the trap log using the new locore "TLOG" macro.  Somewhat
like a flight recorder, this may give some post-mortem clues as to
what was going on as we were spiralling in...

XXX currently depends on various intel MSR's to record the low order
32 bits of the cycle counter as well as last-branch from and to
addresses.

def __MUTEX_PRIVATE

Handle MUTEX_DEBUG.

Allocate proc0 in machine-dependent code (can't specify align(16) in
C code on x86).

Add first-cut mutex and rwlock implementation bits for the x86.
XXX Does not actually handle i386 CPUs yet, only i486 and later.

Set up per-cpu GDT.
Use %fs for per-cpu data access.

Catch up to -current.

checkpoint merge-in-progress from mainline.

Pull up revision 1.28 (requested by sommerfeld):
  Add %fs/%gs to trap frame and save/restore them on trap/interupt/
  syscall entry from userspace.

  Remove special-case ``by hand'' validation of %fs/%gs register
  values s well as special handling of them in various signal
  handling paths.  Now, like %ds and %es, they are validated by
  the hardware on return to userland.

  This paves the way for the use of %fs for per-cpu data on multi-
  processor systems, and fixes an otherwise difficult-to-fix
  interaction between threads/clone(2) and USER_LDT.

Add %fs/%gs to trap frame and save/restore them on
trap/interrupt/syscall entry from userspace.

Remove special-case "by hand" validation of fs/gs register values as
well as special handling of them in various signal handling paths.

Now, like %ds and %es, they are validated by the hardware on return to
userland.

This paves the way for the use of %fs for per-cpu data on
multiprocessor systems, and fixes an otherwise difficult-to-fix
interaction between threads/clone(2) and USER_LDT.

Discussed in advance with Frank van der Linden.

Merge up with -current

Add infrastructure to allow ports to override build of in6_cksum.c by
enabling the INET6_MD_CKSUM option, which is defopted into opt_inet.h.
Supply an i386 assembly version of in6_cksum in in_cksum.s; on
P6-family cpu's, this is is roughly 20% faster than the C code in
sys/netinet6 for ethernet-mtu-sized mbufs in L1 cache.  Turn on
INET6_MD_CKSUM in i386/conf/std.i386

While we're here, also nuke some now-obsolete XXX comments from
in_cksum.s.

Merge sommerfeld_i386mp_1 branch with -current as of today.
GENERIC.MP kernel boots and runs multiuser on my ABIT BP6

Sync with HEAD

Propagate __HAVE_GENERIC_SOFTINTR to assembly files.

Catch up with -current.

Pull up revision 1.25 (requested by fvdl):
  Use optimized i386 assembly version for in4_cksum as well as the
  older in_cksum.  Gets back the 10-15% throughput loss compared
  to the NetBSD 1.4 branch.

Merge branch with -current; top of branch + current builds a working
GENERIC.MP again.

Sync with HEAD.

Use assembly version of in4_cksum (which is a piece of code that
does some of the extra work and then jumps into in_cksum).

Initial commit of scheduler activations and lightweight process support.

Significant rewrite of slave CPU attach and initialization, centering
on identifycpu() and spreading outward.

Separate feature probes (cpuid invocation), which runs on the cpu
being attached, from the display of this information, which runs on
the boot cpu; remove some of the probe code from locore as it doesn't
need to run that early.

We now spin up secondary cpu's during cpu_attach, have them do a cpu
feature probe, and then have them spin waiting for a "go" signal.

We no longer pay attention to the cpu signature and cpuid features
reported by the MP BIOS since those are known to be truncated for at
least some bioses.

We now do npx initialization (including FDIV bug detection) on all
cpus.

XXX Change some of the cyrix bug workarounds to fit the new
identifycpu() system; this is untested.

Snapshot of merge-in-progress with -current.

[Not expected to build].  Catch up with the last N months worth of
changes to -current.

Sync with HEAD (for UBC fixes).

Introduce 2 new flags in types.h:
* __HAVE_SYSCALL_INTERN.  If this is defined, e_syscall is replaced by
  e_syscall_intern, which is called at key places in the kernel.  This can be
  used to set a MD syscall handler pointer.  This obsoletes and replaces the
  *_HAS_SEPARATED_SYSCALL flags.
* __HAVE_MINIMAL_EMUL.  If this is defined, certain (deprecated) elements in
  struct emul are omitted.

make locore.s call emulation-specific syscall code directly
this should improve speed of emulation syscall path (avoids one function call,
and emulations syscall can use the trapframe trick)
Idea: Charles Hannum

Sync with HEAD.

LKMify

Update thorpej_scsipi to -current as of a month ago
A i386 GENERIC kernel compiles without the siop, ahc and bha drivers
(will be updated later). i386 IDE/ATAPI and ncr work, as well as
sparc/esp_sbus. alpha should work as well (untested yet).
siop, ahc and bha will be updated once I've updated the branch to current
-current, as well as machine-dependant code.

Get this to at least build again in the !MULTIPROCESSOR case..

Add PCB_FPCPU

Update from trunk:
Move the TSS selector out of the PCB and put it into mdproc.  We
need to access this when we have the proclist locked for reading,
and thus cannot store it in the PCB (which may be swapped out).

As part of this, call pmap_activate() from cpu_switch() to switch
to the new address space, and refresh the PCB's copy of the LDT
selector from the pmap structure (see above paragraph).  We need
to do this for MP support anyhow.

Fixes a "panic: spinlock_switchcheck: CPU 0 has 1 spin locks" via
gdt_compact() reported by Nathan Williams.

Move the TSS selector out of the PCB and put it into mdproc.  We
need to access this when we have the proclist locked for reading,
and thus cannot store it in the PCB (which may be swapped out).

As part of this, call pmap_activate() from cpu_switch() to switch
to the new address space, and refresh the PCB's copy of the LDT
selector from the pmap structure (see above paragraph).  We need
to do this for MP support anyhow.

Fixes a "panic: spinlock_switchcheck: CPU 0 has 1 spin locks" via
gdt_compact() reported by Nathan Williams.

Merge sommerfeld_i386mp_1 branch forward to 20000806 sources

remove include of <vm/vm.h>. <vm/vm.h> -> <uvm/uvm_extern.h>

MULTIPROCESSOR: Set curproc->p_cpu when context switching

Merge up to just-post-1.5 -current

Introduce a new process state distinct from SRUN called SONPROC
which indicates that the process is actually running on a
processor.  Test against SONPROC as appropriate rather than
combinations of SRUN and curproc.  Update all context switch code
to properly set SONPROC when the process becomes the current
process on the CPU.

Merge with -current

Glue in uvm_pageidlezero().  While here, improve some panic messages
in pmap.c, as requested by Jonathan Stone.

Add offsets in struct cpu_info for the benefit of locore.s and similar
bottom-feeders.

Sync w/ -current.

PMAP_NEW is no longer optional on the i386; the old pmap's page table
allocation strategy no longer works at all.  Move pmap.new.* to pmap.*.

To read the revision history of PMAP_NEW up until this merge, use cvs
rlog of the old pmap.new.* files.

Remove remaining "ifdef UVM" checks.

Don't include "opt_uvm.h" any more.

pull isa_machdep.h in from machine/ instead of from $(MACHINE)/isa/

Correct Linux compat include file names.

Path to linux_machdep.h changed.

Oops; forgot to commit this.

add 32-bit register support and beginnings of APM V1.2 support

Assign my copyrights to TNF.

Include COMPAT_* option headers I forgot earlier, pointed out by
Nathan Williams.

Fix for defopt'd UVM and PMAP_NEW.

add the i386 MD portions for UVM.

Pull rev 1.4 and 1.5 up from trunk (mycroft)

Implement the BSDI kluge for the Pentium `hang'; leave the first 7 IDT
descriptors in an unmapped page, and patch up the trap information inside
the page fault handler if the faulting VA is inside the IDT.

Some general cleanup:
* Call gdt_init() earlier on.
* Don't bother to check for TSS and LDT descriptors in verr_gdt().
* Nuke the sti special case for trace and breakpoint traps.
* Move some variable declarations into more appropriate locations.

Sync w/ trunk.

put in place a proper bioscall.h (sorry about that!)
finish up incomplete job of moving structure used by bioscall() to
<machine/bioscall.h>, with associated changes in include file strategy,
genassym stuff, etc.

New ARP system, supports IPv4 over any hardware link.

Some of the stuff (e.g., rarpd, bootpd, dhcpd etc., libsa) still will
only support Ethernet. Tcpdump itself should be ok, but libpcap needs
lot of work.

For the detailed change history, look at the commit log entries for
the is-newarp branch.

Merge in Changes from The Trunk.

file genassym.cf was added on branch is-newarp on 1997-03-12 14:34:41 +0000

Use genassym.sh, to support cross-compilation.