CVS log for src/sys/arch/i386/i386/autoconf.c

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Default branch: MAIN
Current tag: yamt-pf42-base3

Revision 1.92 / (download) - annotate - [select for diffs], Sat May 10 16:12:32 2008 UTC (15 years, 11 months ago) by ad
Branch: MAIN
CVS Tags: yamt-pf42-base4, yamt-pf42-base3, yamt-pf42-base2, yamt-nfs-mp-base2, wrstuden-revivesa-base-4, wrstuden-revivesa-base-3, wrstuden-revivesa-base-2, wrstuden-revivesa-base-1, wrstuden-revivesa-base, simonb-wapbl-nbase, simonb-wapbl-base, simonb-wapbl, netbsd-5-base, matt-mips64-base2, hpcarm-cleanup-nbase, haad-dm-base1
Branch point for: nick-hppapmap, netbsd-5, haad-dm
Changes since 1.91: +2 -5 lines
Diff to previous 1.91 (colored)

Improve x86 tsc handling:

- Ditch the cross-CPU calibration stuff. It didn't work properly, and it's
  near impossible to synchronize the CPUs in a running system, because bus
  traffic will interfere with any calibration attempt, messing up the
  timings.

- Only enable the TSC on CPUs where we are sure it does not drift. If we are
  On a known good CPU, give the TSC high timecounter quality, making it the
  default.

- When booting CPUs, detect TSC skew and account for it. Most Intel MP
  systems have synchronized counters, but that need not be true if the
  system has a complicated bus structure. As far as I know, AMD systems
  do not have synchronized TSCs and so we need to handle skew.

- While an AP is waiting to be set running, try and make the TSC drift by
  entering a reduced power state. If we detect drift, ensure that the TSC
  does not get a high timecounter quality. This should not happen and is
  only for safety.

- Make cpu_counter() stuff LKM safe.

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