CVS log for src/sys/arch/evbmips/rmixl/machdep.c

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Default branch: MAIN

Move the at-shutdown call to resettodr() from cpu_reboot() to kern_reboot().

It's a small step, but it's a step.

Remove unnecessary <sys/malloc.h>.

fix various typos in comments and log messages.

Sync with HEAD

Remove duplicate ;

update from HEAD

Sync with HEAD

Sync with HEAD.  (Note that most of these changes are simply $NetBSD$
tag issues.)

switch all ports to use uvm_init.c:uvm_md_init()

uvm_setpagesize() is now subsumed within this funciton.

Sync with HEAD

Use cpu_startup_common()

Avoid using curpcb (use lwp_getpcb(curlwp)) instead.

Sync with HEAD

Rework cavium support in preparation for MULTIPROCESSOR support

Rebase to HEAD as of a few days ago.

sync with head.

for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.

this commit was splitted into small chunks to avoid
a limitation of cvs.  ("Protocol error: too many arguments")

sync with head

use cpu_{g,s}etmodel

sync with head

sync to -current

sync to -current

sync to latest -current.

Remove redundant common declaration.

Remove reduntant/conflicting common declarations.

merge to -current.

Change old-style function defintions to C89 prototypes.

Approved by releng.

converting extent(9) from malloc(9) to kmem(9)
preceding kmem-vmem-pool-uvm patch

releng@ acknowledged

Restore RCSID

Use extern for machdep_debug.

Rework Fast Messaging Network support (it's now lockless).
Workaround a problem with bus 0 BAR sizing causing the registers behind
the BAR to become inaccessible.
Move much/most of the startup code from evbmips/rmixl/machdep to
mips/rmi/rmixl_machdep.c
Move the code to find the XLP variant to the early boot so it can be used
early.
8bit and 16bit accessed to PCI bus 0 cause cache errors so chagne the access
of pci mem to 32bits.

Initially mark all GPIO pins as available.

Add commented out AB_DEBUG.

Fix c&p error.

When filling out the physical extent, make sure to probe NOR base/limit pairs.

Rework to add early support.
Add XLP support.  Allow one kernel to support XLR/XLS and XLP.
Do bus_dma init in cpu_configure.

Add earlycons support.

Rework things a bit for the XLR/XLS/XLP TLB.  Before dealing with the TLB when
MP on the XL?, disable interrupts and take out a lock to prevent concurrent
updates to the TLB.  In the TLB miss and invalid exception handlers, if the
lock is already owned by another CPU, simply return from the exception and
let it continue or restart as appropriate.  This prevents concurrent TLB
exceptions in multiple threads from possibly updating the TLB multiple times
for a single address.

Take part of the KSEG2 space and use it to "almost" direct another 256MB
of memory so that N32 kernels can make use of ram outside of KSEG0.  This
allows N32 kernels to be useful on systems with 4GB of RAM or more.

Sync with HEAD.

Use new MIPS64*_RMIXL options
If MP, store address of &pmap_tlb0_info.ti_lock->mtx_lock to OSSCRATCH 2

Major merge to/from current.
Adds MIPS32/MIPS64 R2 support (24k, 74k, etc.) including COP0_USERLOCAL
Adds support for emulation of rdhwr $3,$29 instruction.
Major cleanup of SMP code.  (stable on multi-core / single thread per core)
llsc locking code only used in MP capable kernels.

sync with head

Make sure we init MIPS COP0 OSSCRATCH for UP as well as for MP.

Add code to fixup the text segment to replace loads
from L_CPU(MIPS_CURLWP) or curlwp->l_cpu with
loads from COP0 register OSSCRATCH.

sync with head

Sync with HEAD

Merge forward from matt-nb5-mips64.

Sync with HEAD

Remove clause 3 (UCB advertising clause) from the University of Utah
copyright.  Confirmed by Mike Hibler, mike at cs.utah.edu - thanks!
Also, merge UCB and Utah copyright texts back into one, as they
originally were.

Extra verification by snj@.

- include opt_multiprocessor.h for MULTIPROCESSOR dependency
- in rmixl_pcr_init_core(), ifdef MIPS_DDB_WATCH, clear IEU_DEFEATURE
so we can get T_WATCH execeptions if/when we set COP0 watchpoint

Retire struct user, remove sys/user.h inclusions.  Note sys/user.h header
as obsolete.  Remove USER_TO_UAREA/UAREA_TO_USER macros.

Various #include fixes and review by matt@.

- add rmixl_pcr_init_core() to initialize per-core processor control regs

When doing MP, make sure the TLB is global mode (shared among all threads).

Add new psb_version.

add psb version 0x4b67d03200000056 to the list of known versions

Sync with HEAD.

- include "rmixl_pcix.h" and "rmixl_pcie.h" to get the config flags
- include rmixl_pcixvar.h to get proto for rmixl_physaddr_init_pcix()
- calls to rmixl_physaddr_init_pcix() and rmixl_physaddr_init_pcie()
depend on the config flags
- eliminate vm_clusters[], just use mem_clusters[] for everything
- add mem_cluster_maxaddr to track highest RAM addr,
used to check PCI-X Host BARs; calculate his value just before
calling mips_page_physload() i.e. once mem_clusters[] is stable.

turn off MACHDEP_DEBUG

- add new recognized psb (firmware) ID 0x4b8ead3100000056
- pcie physical regions discovery is moved to rmixl_pcie.c
and is conditional on RMI chip type (XLR has no PCIE)

- specify rmixl_splsw to mips_vector_init
  note that __INTR_PRIVATE must be defined to do that
- print MEMLIMIT if it is defined, after printing memsize
- improve some comments

sync with head

Use dmtc0 too.

Use dmfc0 k0,cop0_osscratch if _LP64

Fix tpyo (missing ;)

Fix gimplish.

For MULTIPROCESSOR kernels, enable exception fixups.

file machdep.c was added on branch yamt-nfs-mp on 2010-03-11 15:02:20 +0000

Remove separate mb_map. The nmbclusters is computed at boot time based
on the amount of physical memory and limited by NMBCLUSTERS if present.
Architectures without direct mapping also limit it based on the kmem_map
size, which is used as backing store. On i386 and ARM, the maximum KVA
used for mbuf clusters is limited to 64MB by default.

The old default limits and limits based on GATEWAY have been removed.
key_registered_sb_max is hard-wired to a value derived from 2048
clusters.

fix fallout from frame/trapframe merger.

- rmiclfw_psb_versions[] is replaced by rmiclfw_psb_id[]
  which now lists type to distinguish between RMI and Dell
  firmware variants
- use MEMLIMIT to limit max mem addr given to uvm

- move firmware info stuff into struct rmixl_config

- memsize and related now uint64_t to handle >4GB mem
- if MULTIPROCESSOR do not 'disable all threads except #0' or
  'set single MMU Thread Mode'

Adjust things to the new world order.

- get cpu wakeup info from firmware
- reserve the cpu_wakeup_info shared memory area from uvm
- initialize cpu_model from mycpu->cpu_name
- dont disable all non-0 threads if MULTIPROCESSOR

- if the firmware version is unknown, we use MEMSIZE instead of
  maps prpovided by firmware; if MEMSIZE if nt configure, print
  error message are halt; if would defer until consinit
  then we could panic.
- fix seg count when MEMSIZE is used to constrain memory  obtained from firmware maps
- cast physmem to to uint64_t before applying ctob() when passing
  bytes count to format_bytes()

- rmixl_reset() now uses RESET bit in RMIXL_GPIO_RESET register to reboot

Use mips_page_physload and mips_init_lwp0_uarea.

Fix few problems in evbmips/rmixl:
- mach_init: use mips_init_lwp0_uarea(), do not hardcode it.  Do not call
  ksyms_init(), it's called in MI.  Also, avoid struct user in few places.
- findroot: use deviter interface.

- delete MACHDEP_DEBUG define
- adjust name of (big endian) obio bus space init function

Merge from matt-nb5-mips64
Merge mips-specific arch files.

- add another known/recognized psb_version ID#
- useing comcnfreq instead of -1 in rmixl_com_cnattach now
- MIPS_RESET_EXC_VEC is physical addr, no need for translation to phys
  when reserving from phys memory (should never be in the list anyway).
- in rmixlfw_init(), when untested psb_version, initialize mem_clusters[]
  (to use MEMSIZE)

set up some Processor Control registers at start of mach_init():
- disable all threads except #0
- disable Unaligned Access
- set single MMU Thread Mode, single TLB partition

- make infop work for N32 or N64; firmware gives us a
non-sign-extended 32 bit pointer in a 64 bit variable
- in rmixlfw_init(), when PSB version not found,
fix rc_io_pbase initialization, and add the missing return MEMSIZE.
- use PRIx64 format to make some printfs work for N32 or N64
- use (intptr_t) as needed to make int to pointer casts work for N32 and N64
- init rc_obio_memt replaces init of rc_eb_memt, rc_el_memt

- rmixl_physaddr_init() instantiates a fixed extent
  used to allocate physical address regions;
  allocate regions known to be occupied by DRAM or I/O BARs
- physmap_print() prints the physmap as provided by boot firmware
- add ram_seg_resv() to reserve regions in a phys_ram_seg_to
  by splitting segments where needed.
- in mem_clusters_init(),
        if possible use avail_mem_map,
        else use psb_physmem_map,
        otherwise use MEMSIZE.
        avail_mem_map and psb_physmem_map can be limited w/ MEMSIZE

fix typo

- if COMFREQ is undefined, define as -1 (inherit BRG settings from FW)
- add a new recognized FW version entry to rmiclfw_psb_versions
- break out initialization of mem_clusters into own function
- imprpove early boot diagnostics
- avoid faulting on possible NULL avail_mem_map pointer from FW
- avoid using possible NULL reset FW callback pointer

initialize the rmixl el and eb bus spaces

improve how some config data are managed

add netbsd support for RMI XLS6ATX_7A board and XL SoC family

file machdep.c was initially added on branch matt-nb5-mips64.